Home
last modified time | relevance | path

Searched refs:SRI_ARR (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h53 SRI_ARR(FMT_422_CONTROL, FMT, id), \
54 SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id)
61 SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \
62 SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
63 SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \
64 SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
65 SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
66 SRI_ARR(VPG_MEM_PWR, VPG, id)
69 SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
70 SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
[all …]
H A Ddcn35_resource.c146 #define SRI_ARR(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.h39 SRI_ARR(HUBP_3DLUT_ADDRESS_HIGH, CURSOR0_, inst),\
40 SRI_ARR(HUBP_3DLUT_ADDRESS_LOW, CURSOR0_, inst),\
41 SRI_ARR(HUBP_3DLUT_CONTROL, CURSOR0_, inst),\
42 SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, inst)
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c131 #define SRI_ARR(reg_name, block, id)\ macro
465 SRI_ARR(OTG_CRC0_DATA_R32, OTG_CRC32, id),\
466 SRI_ARR(OTG_CRC0_DATA_G32, OTG_CRC32, id),\
467 SRI_ARR(OTG_CRC0_DATA_B32, OTG_CRC32, id),\
468 SRI_ARR(OTG_CRC1_DATA_R32, OTG_CRC32, id),\
469 SRI_ARR(OTG_CRC1_DATA_G32, OTG_CRC32, id),\
470 SRI_ARR(OTG_CRC1_DATA_B32, OTG_CRC32, id)
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c126 #define SRI_ARR(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c131 #define SRI_ARR(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c112 #define SRI_ARR(reg_name, block, id)\ macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c131 #define SRI_ARR(reg_name, block, id)\ macro