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Searched refs:SOC15_WAIT_ON_RREG (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c545 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
550 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
556 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
562 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
568 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
573 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
578 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
583 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
619 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_enable_static_power_gating()
625 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_enable_static_power_gating()
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H A Dvcn_v4_0_5.c584 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v4_0_5_disable_static_power_gating()
588 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
593 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
598 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
604 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
608 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
612 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
616 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
650 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_enable_static_power_gating()
655 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_enable_static_power_gating()
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H A Dvcn_v2_5.c792 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
1549 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1554 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1557 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1560 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1562 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1593 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1601 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1612 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1668 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
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H A Djpeg_v4_0_5.c379 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_disable_static_power_gating()
404 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_enable_static_power_gating()
435 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
677 return SOC15_WAIT_ON_RREG(JPEG, i, regUVD_JRBC_STATUS, in jpeg_v4_0_5_wait_for_idle()
H A Djpeg_v5_0_0.c275 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0, in jpeg_v5_0_0_disable_power_gating()
295 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, in jpeg_v5_0_0_enable_power_gating()
578 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, in jpeg_v5_0_0_wait_for_idle()
H A Dumsch_mm_v4_0.c67 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, in umsch_mm_v4_0_load_microcode()
164 r = SOC15_WAIT_ON_RREG(VCN, 0, regVCN_MES_MSTATUS_LO, 0xAAAAAAAA, 0xFFFFFFFF); in umsch_mm_v4_0_load_microcode()
261 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, in umsch_mm_v4_0_ring_stop()
H A Dvpe_v6_1.c292 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ_6_1_1, 0, in vpe_v_6_1_ring_stop()
296 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ, 0, in vpe_v_6_1_ring_stop()
H A Dsoc15_common.h100 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ macro
H A Djpeg_v2_5.c547 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, in jpeg_v2_5_wait_for_idle()