1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Cryptographic API.
4 *
5 * Support for OMAP SHA1/MD5 HW acceleration.
6 *
7 * Copyright (c) 2010 Nokia Corporation
8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
9 * Copyright (c) 2011 Texas Instruments Incorporated
10 *
11 * Some ideas are from old omap-sha1-md5.c driver.
12 */
13
14 #define pr_fmt(fmt) "%s: " fmt, __func__
15
16 #include <crypto/engine.h>
17 #include <crypto/hmac.h>
18 #include <crypto/internal/hash.h>
19 #include <crypto/scatterwalk.h>
20 #include <crypto/sha1.h>
21 #include <crypto/sha2.h>
22 #include <linux/err.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/scatterlist.h>
38 #include <linux/slab.h>
39 #include <linux/string.h>
40 #include <linux/sysfs.h>
41 #include <linux/workqueue.h>
42
43 #define MD5_DIGEST_SIZE 16
44
45 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
46 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
47 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
48
49 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
50
51 #define SHA_REG_CTRL 0x18
52 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
53 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
54 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
55 #define SHA_REG_CTRL_ALGO (1 << 2)
56 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
57 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
58
59 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
60
61 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
62 #define SHA_REG_MASK_DMA_EN (1 << 3)
63 #define SHA_REG_MASK_IT_EN (1 << 2)
64 #define SHA_REG_MASK_SOFTRESET (1 << 1)
65 #define SHA_REG_AUTOIDLE (1 << 0)
66
67 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
68 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
69
70 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
71 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
72 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
73 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
74 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
75
76 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
77 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
78 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
79 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
80 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
81 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
82 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
83
84 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
85
86 #define SHA_REG_IRQSTATUS 0x118
87 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
88 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
89 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
90 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
91
92 #define SHA_REG_IRQENA 0x11C
93 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
94 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
95 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
96 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
97
98 #define DEFAULT_TIMEOUT_INTERVAL HZ
99
100 #define DEFAULT_AUTOSUSPEND_DELAY 1000
101
102 /* mostly device flags */
103 #define FLAGS_FINAL 1
104 #define FLAGS_DMA_ACTIVE 2
105 #define FLAGS_OUTPUT_READY 3
106 #define FLAGS_CPU 5
107 #define FLAGS_DMA_READY 6
108 #define FLAGS_AUTO_XOR 7
109 #define FLAGS_BE32_SHA1 8
110 #define FLAGS_SGS_COPIED 9
111 #define FLAGS_SGS_ALLOCED 10
112 #define FLAGS_HUGE 11
113
114 /* context flags */
115 #define FLAGS_FINUP 16
116
117 #define FLAGS_MODE_SHIFT 18
118 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
119 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
120 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
121 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
122 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
125
126 #define FLAGS_HMAC 21
127 #define FLAGS_ERROR 22
128
129 #define OP_UPDATE 1
130 #define OP_FINAL 2
131
132 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
133 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
134
135 #define BUFLEN SHA512_BLOCK_SIZE
136 #define OMAP_SHA_DMA_THRESHOLD 256
137
138 #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048)
139
140 struct omap_sham_dev;
141
142 struct omap_sham_reqctx {
143 struct omap_sham_dev *dd;
144 unsigned long flags;
145 u8 op;
146
147 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
148 size_t digcnt;
149 size_t bufcnt;
150
151 /* walk state */
152 struct scatterlist *sg;
153 struct scatterlist sgl[2];
154 int offset; /* offset in current sg */
155 int sg_len;
156 unsigned int total; /* total request */
157
158 u8 buffer[BUFLEN] OMAP_ALIGNED;
159 };
160
161 struct omap_sham_hmac_ctx {
162 struct crypto_shash *shash;
163 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
164 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
165 };
166
167 struct omap_sham_ctx {
168 unsigned long flags;
169
170 /* fallback stuff */
171 struct crypto_shash *fallback;
172
173 struct omap_sham_hmac_ctx base[];
174 };
175
176 #define OMAP_SHAM_QUEUE_LENGTH 10
177
178 struct omap_sham_algs_info {
179 struct ahash_engine_alg *algs_list;
180 unsigned int size;
181 unsigned int registered;
182 };
183
184 struct omap_sham_pdata {
185 struct omap_sham_algs_info *algs_info;
186 unsigned int algs_info_size;
187 unsigned long flags;
188 int digest_size;
189
190 void (*copy_hash)(struct ahash_request *req, int out);
191 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
192 int final, int dma);
193 void (*trigger)(struct omap_sham_dev *dd, size_t length);
194 int (*poll_irq)(struct omap_sham_dev *dd);
195 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
196
197 u32 odigest_ofs;
198 u32 idigest_ofs;
199 u32 din_ofs;
200 u32 digcnt_ofs;
201 u32 rev_ofs;
202 u32 mask_ofs;
203 u32 sysstatus_ofs;
204 u32 mode_ofs;
205 u32 length_ofs;
206
207 u32 major_mask;
208 u32 major_shift;
209 u32 minor_mask;
210 u32 minor_shift;
211 };
212
213 struct omap_sham_dev {
214 struct list_head list;
215 unsigned long phys_base;
216 struct device *dev;
217 void __iomem *io_base;
218 int irq;
219 int err;
220 struct dma_chan *dma_lch;
221 struct work_struct done_task;
222 u8 polling_mode;
223 u8 xmit_buf[BUFLEN] OMAP_ALIGNED;
224
225 unsigned long flags;
226 int fallback_sz;
227 struct crypto_queue queue;
228 struct ahash_request *req;
229 struct crypto_engine *engine;
230
231 const struct omap_sham_pdata *pdata;
232 };
233
234 struct omap_sham_drv {
235 struct list_head dev_list;
236 spinlock_t lock;
237 unsigned long flags;
238 };
239
240 static struct omap_sham_drv sham = {
241 .dev_list = LIST_HEAD_INIT(sham.dev_list),
242 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
243 };
244
245 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op);
246 static void omap_sham_finish_req(struct ahash_request *req, int err);
247
omap_sham_read(struct omap_sham_dev * dd,u32 offset)248 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
249 {
250 return __raw_readl(dd->io_base + offset);
251 }
252
omap_sham_write(struct omap_sham_dev * dd,u32 offset,u32 value)253 static inline void omap_sham_write(struct omap_sham_dev *dd,
254 u32 offset, u32 value)
255 {
256 __raw_writel(value, dd->io_base + offset);
257 }
258
omap_sham_write_mask(struct omap_sham_dev * dd,u32 address,u32 value,u32 mask)259 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
260 u32 value, u32 mask)
261 {
262 u32 val;
263
264 val = omap_sham_read(dd, address);
265 val &= ~mask;
266 val |= value;
267 omap_sham_write(dd, address, val);
268 }
269
omap_sham_wait(struct omap_sham_dev * dd,u32 offset,u32 bit)270 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
271 {
272 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
273
274 while (!(omap_sham_read(dd, offset) & bit)) {
275 if (time_is_before_jiffies(timeout))
276 return -ETIMEDOUT;
277 }
278
279 return 0;
280 }
281
omap_sham_copy_hash_omap2(struct ahash_request * req,int out)282 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
283 {
284 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
285 struct omap_sham_dev *dd = ctx->dd;
286 u32 *hash = (u32 *)ctx->digest;
287 int i;
288
289 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
290 if (out)
291 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
292 else
293 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
294 }
295 }
296
omap_sham_copy_hash_omap4(struct ahash_request * req,int out)297 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
298 {
299 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
300 struct omap_sham_dev *dd = ctx->dd;
301 int i;
302
303 if (ctx->flags & BIT(FLAGS_HMAC)) {
304 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
305 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
306 struct omap_sham_hmac_ctx *bctx = tctx->base;
307 u32 *opad = (u32 *)bctx->opad;
308
309 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
310 if (out)
311 opad[i] = omap_sham_read(dd,
312 SHA_REG_ODIGEST(dd, i));
313 else
314 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
315 opad[i]);
316 }
317 }
318
319 omap_sham_copy_hash_omap2(req, out);
320 }
321
omap_sham_copy_ready_hash(struct ahash_request * req)322 static void omap_sham_copy_ready_hash(struct ahash_request *req)
323 {
324 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
325 u32 *in = (u32 *)ctx->digest;
326 u32 *hash = (u32 *)req->result;
327 int i, d, big_endian = 0;
328
329 if (!hash)
330 return;
331
332 switch (ctx->flags & FLAGS_MODE_MASK) {
333 case FLAGS_MODE_MD5:
334 d = MD5_DIGEST_SIZE / sizeof(u32);
335 break;
336 case FLAGS_MODE_SHA1:
337 /* OMAP2 SHA1 is big endian */
338 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
339 big_endian = 1;
340 d = SHA1_DIGEST_SIZE / sizeof(u32);
341 break;
342 case FLAGS_MODE_SHA224:
343 d = SHA224_DIGEST_SIZE / sizeof(u32);
344 break;
345 case FLAGS_MODE_SHA256:
346 d = SHA256_DIGEST_SIZE / sizeof(u32);
347 break;
348 case FLAGS_MODE_SHA384:
349 d = SHA384_DIGEST_SIZE / sizeof(u32);
350 break;
351 case FLAGS_MODE_SHA512:
352 d = SHA512_DIGEST_SIZE / sizeof(u32);
353 break;
354 default:
355 d = 0;
356 }
357
358 if (big_endian)
359 for (i = 0; i < d; i++)
360 put_unaligned(be32_to_cpup((__be32 *)in + i), &hash[i]);
361 else
362 for (i = 0; i < d; i++)
363 put_unaligned(le32_to_cpup((__le32 *)in + i), &hash[i]);
364 }
365
omap_sham_write_ctrl_omap2(struct omap_sham_dev * dd,size_t length,int final,int dma)366 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
367 int final, int dma)
368 {
369 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
370 u32 val = length << 5, mask;
371
372 if (likely(ctx->digcnt))
373 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
374
375 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
376 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
377 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
378 /*
379 * Setting ALGO_CONST only for the first iteration
380 * and CLOSE_HASH only for the last one.
381 */
382 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
383 val |= SHA_REG_CTRL_ALGO;
384 if (!ctx->digcnt)
385 val |= SHA_REG_CTRL_ALGO_CONST;
386 if (final)
387 val |= SHA_REG_CTRL_CLOSE_HASH;
388
389 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
390 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
391
392 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
393 }
394
omap_sham_trigger_omap2(struct omap_sham_dev * dd,size_t length)395 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
396 {
397 }
398
omap_sham_poll_irq_omap2(struct omap_sham_dev * dd)399 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
400 {
401 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
402 }
403
get_block_size(struct omap_sham_reqctx * ctx)404 static int get_block_size(struct omap_sham_reqctx *ctx)
405 {
406 int d;
407
408 switch (ctx->flags & FLAGS_MODE_MASK) {
409 case FLAGS_MODE_MD5:
410 case FLAGS_MODE_SHA1:
411 d = SHA1_BLOCK_SIZE;
412 break;
413 case FLAGS_MODE_SHA224:
414 case FLAGS_MODE_SHA256:
415 d = SHA256_BLOCK_SIZE;
416 break;
417 case FLAGS_MODE_SHA384:
418 case FLAGS_MODE_SHA512:
419 d = SHA512_BLOCK_SIZE;
420 break;
421 default:
422 d = 0;
423 }
424
425 return d;
426 }
427
omap_sham_write_n(struct omap_sham_dev * dd,u32 offset,u32 * value,int count)428 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
429 u32 *value, int count)
430 {
431 for (; count--; value++, offset += 4)
432 omap_sham_write(dd, offset, *value);
433 }
434
omap_sham_write_ctrl_omap4(struct omap_sham_dev * dd,size_t length,int final,int dma)435 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
436 int final, int dma)
437 {
438 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
439 u32 val, mask;
440
441 if (likely(ctx->digcnt))
442 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
443
444 /*
445 * Setting ALGO_CONST only for the first iteration and
446 * CLOSE_HASH only for the last one. Note that flags mode bits
447 * correspond to algorithm encoding in mode register.
448 */
449 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
450 if (!ctx->digcnt) {
451 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
452 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
453 struct omap_sham_hmac_ctx *bctx = tctx->base;
454 int bs, nr_dr;
455
456 val |= SHA_REG_MODE_ALGO_CONSTANT;
457
458 if (ctx->flags & BIT(FLAGS_HMAC)) {
459 bs = get_block_size(ctx);
460 nr_dr = bs / (2 * sizeof(u32));
461 val |= SHA_REG_MODE_HMAC_KEY_PROC;
462 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
463 (u32 *)bctx->ipad, nr_dr);
464 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
465 (u32 *)bctx->ipad + nr_dr, nr_dr);
466 ctx->digcnt += bs;
467 }
468 }
469
470 if (final) {
471 val |= SHA_REG_MODE_CLOSE_HASH;
472
473 if (ctx->flags & BIT(FLAGS_HMAC))
474 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
475 }
476
477 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
478 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
479 SHA_REG_MODE_HMAC_KEY_PROC;
480
481 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
482 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
483 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
484 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
485 SHA_REG_MASK_IT_EN |
486 (dma ? SHA_REG_MASK_DMA_EN : 0),
487 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
488 }
489
omap_sham_trigger_omap4(struct omap_sham_dev * dd,size_t length)490 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
491 {
492 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
493 }
494
omap_sham_poll_irq_omap4(struct omap_sham_dev * dd)495 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
496 {
497 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
498 SHA_REG_IRQSTATUS_INPUT_RDY);
499 }
500
omap_sham_xmit_cpu(struct omap_sham_dev * dd,size_t length,int final)501 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
502 int final)
503 {
504 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
505 int count, len32, bs32, offset = 0;
506 const u32 *buffer;
507 int mlen;
508 struct sg_mapping_iter mi;
509
510 dev_dbg(dd->dev, "xmit_cpu: digcnt: %zd, length: %zd, final: %d\n",
511 ctx->digcnt, length, final);
512
513 dd->pdata->write_ctrl(dd, length, final, 0);
514 dd->pdata->trigger(dd, length);
515
516 /* should be non-zero before next lines to disable clocks later */
517 ctx->digcnt += length;
518 ctx->total -= length;
519
520 if (final)
521 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
522
523 set_bit(FLAGS_CPU, &dd->flags);
524
525 len32 = DIV_ROUND_UP(length, sizeof(u32));
526 bs32 = get_block_size(ctx) / sizeof(u32);
527
528 sg_miter_start(&mi, ctx->sg, ctx->sg_len,
529 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
530
531 mlen = 0;
532
533 while (len32) {
534 if (dd->pdata->poll_irq(dd))
535 return -ETIMEDOUT;
536
537 for (count = 0; count < min(len32, bs32); count++, offset++) {
538 if (!mlen) {
539 sg_miter_next(&mi);
540 mlen = mi.length;
541 if (!mlen) {
542 pr_err("sg miter failure.\n");
543 return -EINVAL;
544 }
545 offset = 0;
546 buffer = mi.addr;
547 }
548 omap_sham_write(dd, SHA_REG_DIN(dd, count),
549 buffer[offset]);
550 mlen -= 4;
551 }
552 len32 -= min(len32, bs32);
553 }
554
555 sg_miter_stop(&mi);
556
557 return -EINPROGRESS;
558 }
559
omap_sham_dma_callback(void * param)560 static void omap_sham_dma_callback(void *param)
561 {
562 struct omap_sham_dev *dd = param;
563
564 set_bit(FLAGS_DMA_READY, &dd->flags);
565 queue_work(system_bh_wq, &dd->done_task);
566 }
567
omap_sham_xmit_dma(struct omap_sham_dev * dd,size_t length,int final)568 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
569 int final)
570 {
571 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
572 struct dma_async_tx_descriptor *tx;
573 struct dma_slave_config cfg;
574 int ret;
575
576 dev_dbg(dd->dev, "xmit_dma: digcnt: %zd, length: %zd, final: %d\n",
577 ctx->digcnt, length, final);
578
579 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
580 dev_err(dd->dev, "dma_map_sg error\n");
581 return -EINVAL;
582 }
583
584 memset(&cfg, 0, sizeof(cfg));
585
586 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
587 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
588 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
589
590 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
591 if (ret) {
592 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
593 return ret;
594 }
595
596 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
597 DMA_MEM_TO_DEV,
598 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
599
600 if (!tx) {
601 dev_err(dd->dev, "prep_slave_sg failed\n");
602 return -EINVAL;
603 }
604
605 tx->callback = omap_sham_dma_callback;
606 tx->callback_param = dd;
607
608 dd->pdata->write_ctrl(dd, length, final, 1);
609
610 ctx->digcnt += length;
611 ctx->total -= length;
612
613 if (final)
614 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
615
616 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
617
618 dmaengine_submit(tx);
619 dma_async_issue_pending(dd->dma_lch);
620
621 dd->pdata->trigger(dd, length);
622
623 return -EINPROGRESS;
624 }
625
omap_sham_copy_sg_lists(struct omap_sham_reqctx * ctx,struct scatterlist * sg,int bs,int new_len)626 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
627 struct scatterlist *sg, int bs, int new_len)
628 {
629 int n = sg_nents(sg);
630 struct scatterlist *tmp;
631 int offset = ctx->offset;
632
633 ctx->total = new_len;
634
635 if (ctx->bufcnt)
636 n++;
637
638 ctx->sg = kmalloc_objs(*sg, n);
639 if (!ctx->sg)
640 return -ENOMEM;
641
642 sg_init_table(ctx->sg, n);
643
644 tmp = ctx->sg;
645
646 ctx->sg_len = 0;
647
648 if (ctx->bufcnt) {
649 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
650 tmp = sg_next(tmp);
651 ctx->sg_len++;
652 new_len -= ctx->bufcnt;
653 }
654
655 while (sg && new_len) {
656 int len = sg->length - offset;
657
658 if (len <= 0) {
659 offset -= sg->length;
660 sg = sg_next(sg);
661 continue;
662 }
663
664 if (new_len < len)
665 len = new_len;
666
667 if (len > 0) {
668 new_len -= len;
669 sg_set_page(tmp, sg_page(sg), len, sg->offset + offset);
670 offset = 0;
671 ctx->offset = 0;
672 ctx->sg_len++;
673 if (new_len <= 0)
674 break;
675 tmp = sg_next(tmp);
676 }
677
678 sg = sg_next(sg);
679 }
680
681 if (tmp)
682 sg_mark_end(tmp);
683
684 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
685
686 ctx->offset += new_len - ctx->bufcnt;
687 ctx->bufcnt = 0;
688
689 return 0;
690 }
691
omap_sham_copy_sgs(struct omap_sham_reqctx * ctx,struct scatterlist * sg,int bs,unsigned int new_len)692 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
693 struct scatterlist *sg, int bs,
694 unsigned int new_len)
695 {
696 int pages;
697 void *buf;
698
699 pages = get_order(new_len);
700
701 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
702 if (!buf) {
703 pr_err("Couldn't allocate pages for unaligned cases.\n");
704 return -ENOMEM;
705 }
706
707 if (ctx->bufcnt)
708 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
709
710 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
711 min(new_len, ctx->total) - ctx->bufcnt, 0);
712 sg_init_table(ctx->sgl, 1);
713 sg_set_buf(ctx->sgl, buf, new_len);
714 ctx->sg = ctx->sgl;
715 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
716 ctx->sg_len = 1;
717 ctx->offset += new_len - ctx->bufcnt;
718 ctx->bufcnt = 0;
719 ctx->total = new_len;
720
721 return 0;
722 }
723
omap_sham_align_sgs(struct scatterlist * sg,int nbytes,int bs,bool final,struct omap_sham_reqctx * rctx)724 static int omap_sham_align_sgs(struct scatterlist *sg,
725 int nbytes, int bs, bool final,
726 struct omap_sham_reqctx *rctx)
727 {
728 int n = 0;
729 bool aligned = true;
730 bool list_ok = true;
731 struct scatterlist *sg_tmp = sg;
732 int new_len;
733 int offset = rctx->offset;
734 int bufcnt = rctx->bufcnt;
735
736 if (!sg || !sg->length || !nbytes) {
737 if (bufcnt) {
738 bufcnt = DIV_ROUND_UP(bufcnt, bs) * bs;
739 sg_init_table(rctx->sgl, 1);
740 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, bufcnt);
741 rctx->sg = rctx->sgl;
742 rctx->sg_len = 1;
743 }
744
745 return 0;
746 }
747
748 new_len = nbytes;
749
750 if (offset)
751 list_ok = false;
752
753 if (final)
754 new_len = DIV_ROUND_UP(new_len, bs) * bs;
755 else
756 new_len = (new_len - 1) / bs * bs;
757
758 if (!new_len)
759 return 0;
760
761 if (nbytes != new_len)
762 list_ok = false;
763
764 while (nbytes > 0 && sg_tmp) {
765 n++;
766
767 if (bufcnt) {
768 if (!IS_ALIGNED(bufcnt, bs)) {
769 aligned = false;
770 break;
771 }
772 nbytes -= bufcnt;
773 bufcnt = 0;
774 if (!nbytes)
775 list_ok = false;
776
777 continue;
778 }
779
780 #ifdef CONFIG_ZONE_DMA
781 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
782 aligned = false;
783 break;
784 }
785 #endif
786
787 if (offset < sg_tmp->length) {
788 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
789 aligned = false;
790 break;
791 }
792
793 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
794 aligned = false;
795 break;
796 }
797 }
798
799 if (offset) {
800 offset -= sg_tmp->length;
801 if (offset < 0) {
802 nbytes += offset;
803 offset = 0;
804 }
805 } else {
806 nbytes -= sg_tmp->length;
807 }
808
809 sg_tmp = sg_next(sg_tmp);
810
811 if (nbytes < 0) {
812 list_ok = false;
813 break;
814 }
815 }
816
817 if (new_len > OMAP_SHA_MAX_DMA_LEN) {
818 new_len = OMAP_SHA_MAX_DMA_LEN;
819 aligned = false;
820 }
821
822 if (!aligned)
823 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
824 else if (!list_ok)
825 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
826
827 rctx->total = new_len;
828 rctx->offset += new_len;
829 rctx->sg_len = n;
830 if (rctx->bufcnt) {
831 sg_init_table(rctx->sgl, 2);
832 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
833 sg_chain(rctx->sgl, 2, sg);
834 rctx->sg = rctx->sgl;
835 } else {
836 rctx->sg = sg;
837 }
838
839 return 0;
840 }
841
omap_sham_prepare_request(struct crypto_engine * engine,void * areq)842 static int omap_sham_prepare_request(struct crypto_engine *engine, void *areq)
843 {
844 struct ahash_request *req = container_of(areq, struct ahash_request,
845 base);
846 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
847 int bs;
848 int ret;
849 unsigned int nbytes;
850 bool final = rctx->flags & BIT(FLAGS_FINUP);
851 bool update = rctx->op == OP_UPDATE;
852 int hash_later;
853
854 bs = get_block_size(rctx);
855
856 nbytes = rctx->bufcnt;
857
858 if (update)
859 nbytes += req->nbytes - rctx->offset;
860
861 dev_dbg(rctx->dd->dev,
862 "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%zd\n",
863 __func__, nbytes, bs, rctx->total, rctx->offset,
864 rctx->bufcnt);
865
866 if (!nbytes)
867 return 0;
868
869 rctx->total = nbytes;
870
871 if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
872 int len = bs - rctx->bufcnt % bs;
873
874 if (len > req->nbytes)
875 len = req->nbytes;
876 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
877 0, len, 0);
878 rctx->bufcnt += len;
879 rctx->offset = len;
880 }
881
882 if (rctx->bufcnt)
883 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
884
885 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
886 if (ret)
887 return ret;
888
889 hash_later = nbytes - rctx->total;
890 if (hash_later < 0)
891 hash_later = 0;
892
893 if (hash_later && hash_later <= sizeof(rctx->buffer)) {
894 scatterwalk_map_and_copy(rctx->buffer,
895 req->src,
896 req->nbytes - hash_later,
897 hash_later, 0);
898
899 rctx->bufcnt = hash_later;
900 } else {
901 rctx->bufcnt = 0;
902 }
903
904 if (hash_later > sizeof(rctx->buffer))
905 set_bit(FLAGS_HUGE, &rctx->dd->flags);
906
907 rctx->total = min(nbytes, rctx->total);
908
909 return 0;
910 }
911
omap_sham_update_dma_stop(struct omap_sham_dev * dd)912 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
913 {
914 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
915
916 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
917
918 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
919
920 return 0;
921 }
922
omap_sham_find_dev(struct omap_sham_reqctx * ctx)923 static struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
924 {
925 struct omap_sham_dev *dd;
926
927 if (ctx->dd)
928 return ctx->dd;
929
930 spin_lock_bh(&sham.lock);
931 dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
932 list_move_tail(&dd->list, &sham.dev_list);
933 ctx->dd = dd;
934 spin_unlock_bh(&sham.lock);
935
936 return dd;
937 }
938
omap_sham_init(struct ahash_request * req)939 static int omap_sham_init(struct ahash_request *req)
940 {
941 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
942 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
943 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
944 struct omap_sham_dev *dd;
945 int bs = 0;
946
947 ctx->dd = NULL;
948
949 dd = omap_sham_find_dev(ctx);
950 if (!dd)
951 return -ENODEV;
952
953 ctx->flags = 0;
954
955 dev_dbg(dd->dev, "init: digest size: %d\n",
956 crypto_ahash_digestsize(tfm));
957
958 switch (crypto_ahash_digestsize(tfm)) {
959 case MD5_DIGEST_SIZE:
960 ctx->flags |= FLAGS_MODE_MD5;
961 bs = SHA1_BLOCK_SIZE;
962 break;
963 case SHA1_DIGEST_SIZE:
964 ctx->flags |= FLAGS_MODE_SHA1;
965 bs = SHA1_BLOCK_SIZE;
966 break;
967 case SHA224_DIGEST_SIZE:
968 ctx->flags |= FLAGS_MODE_SHA224;
969 bs = SHA224_BLOCK_SIZE;
970 break;
971 case SHA256_DIGEST_SIZE:
972 ctx->flags |= FLAGS_MODE_SHA256;
973 bs = SHA256_BLOCK_SIZE;
974 break;
975 case SHA384_DIGEST_SIZE:
976 ctx->flags |= FLAGS_MODE_SHA384;
977 bs = SHA384_BLOCK_SIZE;
978 break;
979 case SHA512_DIGEST_SIZE:
980 ctx->flags |= FLAGS_MODE_SHA512;
981 bs = SHA512_BLOCK_SIZE;
982 break;
983 }
984
985 ctx->bufcnt = 0;
986 ctx->digcnt = 0;
987 ctx->total = 0;
988 ctx->offset = 0;
989
990 if (tctx->flags & BIT(FLAGS_HMAC)) {
991 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
992 struct omap_sham_hmac_ctx *bctx = tctx->base;
993
994 memcpy(ctx->buffer, bctx->ipad, bs);
995 ctx->bufcnt = bs;
996 }
997
998 ctx->flags |= BIT(FLAGS_HMAC);
999 }
1000
1001 return 0;
1002
1003 }
1004
omap_sham_update_req(struct omap_sham_dev * dd)1005 static int omap_sham_update_req(struct omap_sham_dev *dd)
1006 {
1007 struct ahash_request *req = dd->req;
1008 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1009 int err;
1010 bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1011 !(dd->flags & BIT(FLAGS_HUGE));
1012
1013 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %zd, final: %d",
1014 ctx->total, ctx->digcnt, final);
1015
1016 if (ctx->total < get_block_size(ctx) ||
1017 ctx->total < dd->fallback_sz)
1018 ctx->flags |= BIT(FLAGS_CPU);
1019
1020 if (ctx->flags & BIT(FLAGS_CPU))
1021 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1022 else
1023 err = omap_sham_xmit_dma(dd, ctx->total, final);
1024
1025 /* wait for dma completion before can take more data */
1026 dev_dbg(dd->dev, "update: err: %d, digcnt: %zd\n", err, ctx->digcnt);
1027
1028 return err;
1029 }
1030
omap_sham_final_req(struct omap_sham_dev * dd)1031 static int omap_sham_final_req(struct omap_sham_dev *dd)
1032 {
1033 struct ahash_request *req = dd->req;
1034 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1035 int err = 0, use_dma = 1;
1036
1037 if (dd->flags & BIT(FLAGS_HUGE))
1038 return 0;
1039
1040 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1041 /*
1042 * faster to handle last block with cpu or
1043 * use cpu when dma is not present.
1044 */
1045 use_dma = 0;
1046
1047 if (use_dma)
1048 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1049 else
1050 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1051
1052 ctx->bufcnt = 0;
1053
1054 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1055
1056 return err;
1057 }
1058
omap_sham_hash_one_req(struct crypto_engine * engine,void * areq)1059 static int omap_sham_hash_one_req(struct crypto_engine *engine, void *areq)
1060 {
1061 struct ahash_request *req = container_of(areq, struct ahash_request,
1062 base);
1063 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1064 struct omap_sham_dev *dd = ctx->dd;
1065 int err;
1066 bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1067 !(dd->flags & BIT(FLAGS_HUGE));
1068
1069 dev_dbg(dd->dev, "hash-one: op: %u, total: %u, digcnt: %zd, final: %d",
1070 ctx->op, ctx->total, ctx->digcnt, final);
1071
1072 err = omap_sham_prepare_request(engine, areq);
1073 if (err)
1074 return err;
1075
1076 err = pm_runtime_resume_and_get(dd->dev);
1077 if (err < 0) {
1078 dev_err(dd->dev, "failed to get sync: %d\n", err);
1079 return err;
1080 }
1081
1082 dd->err = 0;
1083 dd->req = req;
1084
1085 if (ctx->digcnt)
1086 dd->pdata->copy_hash(req, 0);
1087
1088 if (ctx->op == OP_UPDATE)
1089 err = omap_sham_update_req(dd);
1090 else if (ctx->op == OP_FINAL)
1091 err = omap_sham_final_req(dd);
1092
1093 if (err != -EINPROGRESS)
1094 omap_sham_finish_req(req, err);
1095
1096 return 0;
1097 }
1098
omap_sham_finish_hmac(struct ahash_request * req)1099 static int omap_sham_finish_hmac(struct ahash_request *req)
1100 {
1101 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1102 struct omap_sham_hmac_ctx *bctx = tctx->base;
1103 int bs = crypto_shash_blocksize(bctx->shash);
1104 int ds = crypto_shash_digestsize(bctx->shash);
1105 SHASH_DESC_ON_STACK(shash, bctx->shash);
1106
1107 shash->tfm = bctx->shash;
1108
1109 return crypto_shash_init(shash) ?:
1110 crypto_shash_update(shash, bctx->opad, bs) ?:
1111 crypto_shash_finup(shash, req->result, ds, req->result);
1112 }
1113
omap_sham_finish(struct ahash_request * req)1114 static int omap_sham_finish(struct ahash_request *req)
1115 {
1116 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1117 struct omap_sham_dev *dd = ctx->dd;
1118 int err = 0;
1119
1120 if (ctx->digcnt) {
1121 omap_sham_copy_ready_hash(req);
1122 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1123 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1124 err = omap_sham_finish_hmac(req);
1125 }
1126
1127 dev_dbg(dd->dev, "digcnt: %zd, bufcnt: %zd\n", ctx->digcnt, ctx->bufcnt);
1128
1129 return err;
1130 }
1131
omap_sham_finish_req(struct ahash_request * req,int err)1132 static void omap_sham_finish_req(struct ahash_request *req, int err)
1133 {
1134 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1135 struct omap_sham_dev *dd = ctx->dd;
1136
1137 if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1138 free_pages((unsigned long)sg_virt(ctx->sg),
1139 get_order(ctx->sg->length));
1140
1141 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1142 kfree(ctx->sg);
1143
1144 ctx->sg = NULL;
1145
1146 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED) |
1147 BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) |
1148 BIT(FLAGS_OUTPUT_READY));
1149
1150 if (!err)
1151 dd->pdata->copy_hash(req, 1);
1152
1153 if (dd->flags & BIT(FLAGS_HUGE)) {
1154 /* Re-enqueue the request */
1155 omap_sham_enqueue(req, ctx->op);
1156 return;
1157 }
1158
1159 if (!err) {
1160 if (test_bit(FLAGS_FINAL, &dd->flags))
1161 err = omap_sham_finish(req);
1162 } else {
1163 ctx->flags |= BIT(FLAGS_ERROR);
1164 }
1165
1166 /* atomic operation is not needed here */
1167 dd->flags &= ~(BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1168 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1169
1170 pm_runtime_put_autosuspend(dd->dev);
1171
1172 ctx->offset = 0;
1173
1174 crypto_finalize_hash_request(dd->engine, req, err);
1175 }
1176
omap_sham_handle_queue(struct omap_sham_dev * dd,struct ahash_request * req)1177 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1178 struct ahash_request *req)
1179 {
1180 return crypto_transfer_hash_request_to_engine(dd->engine, req);
1181 }
1182
omap_sham_enqueue(struct ahash_request * req,unsigned int op)1183 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1184 {
1185 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1186 struct omap_sham_dev *dd = ctx->dd;
1187
1188 ctx->op = op;
1189
1190 return omap_sham_handle_queue(dd, req);
1191 }
1192
omap_sham_update(struct ahash_request * req)1193 static int omap_sham_update(struct ahash_request *req)
1194 {
1195 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1196 struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1197
1198 if (!req->nbytes)
1199 return 0;
1200
1201 if (ctx->bufcnt + req->nbytes <= sizeof(ctx->buffer)) {
1202 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1203 0, req->nbytes, 0);
1204 ctx->bufcnt += req->nbytes;
1205 return 0;
1206 }
1207
1208 if (dd->polling_mode)
1209 ctx->flags |= BIT(FLAGS_CPU);
1210
1211 return omap_sham_enqueue(req, OP_UPDATE);
1212 }
1213
omap_sham_final_shash(struct ahash_request * req)1214 static int omap_sham_final_shash(struct ahash_request *req)
1215 {
1216 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1217 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1218 int offset = 0;
1219
1220 /*
1221 * If we are running HMAC on limited hardware support, skip
1222 * the ipad in the beginning of the buffer if we are going for
1223 * software fallback algorithm.
1224 */
1225 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1226 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1227 offset = get_block_size(ctx);
1228
1229 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset,
1230 ctx->bufcnt - offset, req->result);
1231 }
1232
omap_sham_final(struct ahash_request * req)1233 static int omap_sham_final(struct ahash_request *req)
1234 {
1235 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1236
1237 ctx->flags |= BIT(FLAGS_FINUP);
1238
1239 if (ctx->flags & BIT(FLAGS_ERROR))
1240 return 0; /* uncompleted hash is not needed */
1241
1242 /*
1243 * OMAP HW accel works only with buffers >= 9.
1244 * HMAC is always >= 9 because ipad == block size.
1245 * If buffersize is less than fallback_sz, we use fallback
1246 * SW encoding, as using DMA + HW in this case doesn't provide
1247 * any benefit.
1248 */
1249 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1250 return omap_sham_final_shash(req);
1251 else if (ctx->bufcnt)
1252 return omap_sham_enqueue(req, OP_FINAL);
1253
1254 /* copy ready hash (+ finalize hmac) */
1255 return omap_sham_finish(req);
1256 }
1257
omap_sham_finup(struct ahash_request * req)1258 static int omap_sham_finup(struct ahash_request *req)
1259 {
1260 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1261 int err1, err2;
1262
1263 ctx->flags |= BIT(FLAGS_FINUP);
1264
1265 err1 = omap_sham_update(req);
1266 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1267 return err1;
1268 /*
1269 * final() has to be always called to cleanup resources
1270 * even if udpate() failed, except EINPROGRESS
1271 */
1272 err2 = omap_sham_final(req);
1273
1274 return err1 ?: err2;
1275 }
1276
omap_sham_digest(struct ahash_request * req)1277 static int omap_sham_digest(struct ahash_request *req)
1278 {
1279 return omap_sham_init(req) ?: omap_sham_finup(req);
1280 }
1281
omap_sham_setkey(struct crypto_ahash * tfm,const u8 * key,unsigned int keylen)1282 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1283 unsigned int keylen)
1284 {
1285 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1286 struct omap_sham_hmac_ctx *bctx = tctx->base;
1287 int bs = crypto_shash_blocksize(bctx->shash);
1288 int ds = crypto_shash_digestsize(bctx->shash);
1289 int err, i;
1290
1291 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1292 if (err)
1293 return err;
1294
1295 if (keylen > bs) {
1296 err = crypto_shash_tfm_digest(bctx->shash, key, keylen,
1297 bctx->ipad);
1298 if (err)
1299 return err;
1300 keylen = ds;
1301 } else {
1302 memcpy(bctx->ipad, key, keylen);
1303 }
1304
1305 memset(bctx->ipad + keylen, 0, bs - keylen);
1306
1307 if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1308 memcpy(bctx->opad, bctx->ipad, bs);
1309
1310 for (i = 0; i < bs; i++) {
1311 bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1312 bctx->opad[i] ^= HMAC_OPAD_VALUE;
1313 }
1314 }
1315
1316 return err;
1317 }
1318
omap_sham_cra_init_alg(struct crypto_tfm * tfm,const char * alg_base)1319 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1320 {
1321 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1322 const char *alg_name = crypto_tfm_alg_name(tfm);
1323
1324 /* Allocate a fallback and abort if it failed. */
1325 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1326 CRYPTO_ALG_NEED_FALLBACK);
1327 if (IS_ERR(tctx->fallback)) {
1328 pr_err("omap-sham: fallback driver '%s' "
1329 "could not be loaded.\n", alg_name);
1330 return PTR_ERR(tctx->fallback);
1331 }
1332
1333 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1334 sizeof(struct omap_sham_reqctx));
1335
1336 if (alg_base) {
1337 struct omap_sham_hmac_ctx *bctx = tctx->base;
1338 tctx->flags |= BIT(FLAGS_HMAC);
1339 bctx->shash = crypto_alloc_shash(alg_base, 0,
1340 CRYPTO_ALG_NEED_FALLBACK);
1341 if (IS_ERR(bctx->shash)) {
1342 pr_err("omap-sham: base driver '%s' "
1343 "could not be loaded.\n", alg_base);
1344 crypto_free_shash(tctx->fallback);
1345 return PTR_ERR(bctx->shash);
1346 }
1347
1348 }
1349
1350 return 0;
1351 }
1352
omap_sham_cra_init(struct crypto_tfm * tfm)1353 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1354 {
1355 return omap_sham_cra_init_alg(tfm, NULL);
1356 }
1357
omap_sham_cra_sha1_init(struct crypto_tfm * tfm)1358 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1359 {
1360 return omap_sham_cra_init_alg(tfm, "sha1");
1361 }
1362
omap_sham_cra_sha224_init(struct crypto_tfm * tfm)1363 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1364 {
1365 return omap_sham_cra_init_alg(tfm, "sha224");
1366 }
1367
omap_sham_cra_sha256_init(struct crypto_tfm * tfm)1368 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1369 {
1370 return omap_sham_cra_init_alg(tfm, "sha256");
1371 }
1372
omap_sham_cra_md5_init(struct crypto_tfm * tfm)1373 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1374 {
1375 return omap_sham_cra_init_alg(tfm, "md5");
1376 }
1377
omap_sham_cra_sha384_init(struct crypto_tfm * tfm)1378 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1379 {
1380 return omap_sham_cra_init_alg(tfm, "sha384");
1381 }
1382
omap_sham_cra_sha512_init(struct crypto_tfm * tfm)1383 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1384 {
1385 return omap_sham_cra_init_alg(tfm, "sha512");
1386 }
1387
omap_sham_cra_exit(struct crypto_tfm * tfm)1388 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1389 {
1390 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1391
1392 crypto_free_shash(tctx->fallback);
1393 tctx->fallback = NULL;
1394
1395 if (tctx->flags & BIT(FLAGS_HMAC)) {
1396 struct omap_sham_hmac_ctx *bctx = tctx->base;
1397 crypto_free_shash(bctx->shash);
1398 }
1399 }
1400
omap_sham_export(struct ahash_request * req,void * out)1401 static int omap_sham_export(struct ahash_request *req, void *out)
1402 {
1403 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1404
1405 memcpy(out, rctx, offsetof(struct omap_sham_reqctx, buffer) +
1406 rctx->bufcnt);
1407
1408 return 0;
1409 }
1410
omap_sham_import(struct ahash_request * req,const void * in)1411 static int omap_sham_import(struct ahash_request *req, const void *in)
1412 {
1413 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1414 const struct omap_sham_reqctx *ctx_in = in;
1415
1416 memcpy(rctx, in, offsetof(struct omap_sham_reqctx, buffer) +
1417 ctx_in->bufcnt);
1418
1419 return 0;
1420 }
1421
1422 static struct ahash_engine_alg algs_sha1_md5[] = {
1423 {
1424 .base.init = omap_sham_init,
1425 .base.update = omap_sham_update,
1426 .base.final = omap_sham_final,
1427 .base.finup = omap_sham_finup,
1428 .base.digest = omap_sham_digest,
1429 .base.halg.digestsize = SHA1_DIGEST_SIZE,
1430 .base.halg.base = {
1431 .cra_name = "sha1",
1432 .cra_driver_name = "omap-sha1",
1433 .cra_priority = 400,
1434 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1435 CRYPTO_ALG_ASYNC |
1436 CRYPTO_ALG_NEED_FALLBACK,
1437 .cra_blocksize = SHA1_BLOCK_SIZE,
1438 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1439 .cra_module = THIS_MODULE,
1440 .cra_init = omap_sham_cra_init,
1441 .cra_exit = omap_sham_cra_exit,
1442 },
1443 .op.do_one_request = omap_sham_hash_one_req,
1444 },
1445 {
1446 .base.init = omap_sham_init,
1447 .base.update = omap_sham_update,
1448 .base.final = omap_sham_final,
1449 .base.finup = omap_sham_finup,
1450 .base.digest = omap_sham_digest,
1451 .base.halg.digestsize = MD5_DIGEST_SIZE,
1452 .base.halg.base = {
1453 .cra_name = "md5",
1454 .cra_driver_name = "omap-md5",
1455 .cra_priority = 400,
1456 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1457 CRYPTO_ALG_ASYNC |
1458 CRYPTO_ALG_NEED_FALLBACK,
1459 .cra_blocksize = SHA1_BLOCK_SIZE,
1460 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1461 .cra_module = THIS_MODULE,
1462 .cra_init = omap_sham_cra_init,
1463 .cra_exit = omap_sham_cra_exit,
1464 },
1465 .op.do_one_request = omap_sham_hash_one_req,
1466 },
1467 {
1468 .base.init = omap_sham_init,
1469 .base.update = omap_sham_update,
1470 .base.final = omap_sham_final,
1471 .base.finup = omap_sham_finup,
1472 .base.digest = omap_sham_digest,
1473 .base.setkey = omap_sham_setkey,
1474 .base.halg.digestsize = SHA1_DIGEST_SIZE,
1475 .base.halg.base = {
1476 .cra_name = "hmac(sha1)",
1477 .cra_driver_name = "omap-hmac-sha1",
1478 .cra_priority = 400,
1479 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1480 CRYPTO_ALG_ASYNC |
1481 CRYPTO_ALG_NEED_FALLBACK,
1482 .cra_blocksize = SHA1_BLOCK_SIZE,
1483 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1484 sizeof(struct omap_sham_hmac_ctx),
1485 .cra_module = THIS_MODULE,
1486 .cra_init = omap_sham_cra_sha1_init,
1487 .cra_exit = omap_sham_cra_exit,
1488 },
1489 .op.do_one_request = omap_sham_hash_one_req,
1490 },
1491 {
1492 .base.init = omap_sham_init,
1493 .base.update = omap_sham_update,
1494 .base.final = omap_sham_final,
1495 .base.finup = omap_sham_finup,
1496 .base.digest = omap_sham_digest,
1497 .base.setkey = omap_sham_setkey,
1498 .base.halg.digestsize = MD5_DIGEST_SIZE,
1499 .base.halg.base = {
1500 .cra_name = "hmac(md5)",
1501 .cra_driver_name = "omap-hmac-md5",
1502 .cra_priority = 400,
1503 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1504 CRYPTO_ALG_ASYNC |
1505 CRYPTO_ALG_NEED_FALLBACK,
1506 .cra_blocksize = SHA1_BLOCK_SIZE,
1507 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1508 sizeof(struct omap_sham_hmac_ctx),
1509 .cra_module = THIS_MODULE,
1510 .cra_init = omap_sham_cra_md5_init,
1511 .cra_exit = omap_sham_cra_exit,
1512 },
1513 .op.do_one_request = omap_sham_hash_one_req,
1514 }
1515 };
1516
1517 /* OMAP4 has some algs in addition to what OMAP2 has */
1518 static struct ahash_engine_alg algs_sha224_sha256[] = {
1519 {
1520 .base.init = omap_sham_init,
1521 .base.update = omap_sham_update,
1522 .base.final = omap_sham_final,
1523 .base.finup = omap_sham_finup,
1524 .base.digest = omap_sham_digest,
1525 .base.halg.digestsize = SHA224_DIGEST_SIZE,
1526 .base.halg.base = {
1527 .cra_name = "sha224",
1528 .cra_driver_name = "omap-sha224",
1529 .cra_priority = 400,
1530 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1531 CRYPTO_ALG_ASYNC |
1532 CRYPTO_ALG_NEED_FALLBACK,
1533 .cra_blocksize = SHA224_BLOCK_SIZE,
1534 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1535 .cra_module = THIS_MODULE,
1536 .cra_init = omap_sham_cra_init,
1537 .cra_exit = omap_sham_cra_exit,
1538 },
1539 .op.do_one_request = omap_sham_hash_one_req,
1540 },
1541 {
1542 .base.init = omap_sham_init,
1543 .base.update = omap_sham_update,
1544 .base.final = omap_sham_final,
1545 .base.finup = omap_sham_finup,
1546 .base.digest = omap_sham_digest,
1547 .base.halg.digestsize = SHA256_DIGEST_SIZE,
1548 .base.halg.base = {
1549 .cra_name = "sha256",
1550 .cra_driver_name = "omap-sha256",
1551 .cra_priority = 400,
1552 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1553 CRYPTO_ALG_ASYNC |
1554 CRYPTO_ALG_NEED_FALLBACK,
1555 .cra_blocksize = SHA256_BLOCK_SIZE,
1556 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1557 .cra_module = THIS_MODULE,
1558 .cra_init = omap_sham_cra_init,
1559 .cra_exit = omap_sham_cra_exit,
1560 },
1561 .op.do_one_request = omap_sham_hash_one_req,
1562 },
1563 {
1564 .base.init = omap_sham_init,
1565 .base.update = omap_sham_update,
1566 .base.final = omap_sham_final,
1567 .base.finup = omap_sham_finup,
1568 .base.digest = omap_sham_digest,
1569 .base.setkey = omap_sham_setkey,
1570 .base.halg.digestsize = SHA224_DIGEST_SIZE,
1571 .base.halg.base = {
1572 .cra_name = "hmac(sha224)",
1573 .cra_driver_name = "omap-hmac-sha224",
1574 .cra_priority = 400,
1575 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1576 CRYPTO_ALG_ASYNC |
1577 CRYPTO_ALG_NEED_FALLBACK,
1578 .cra_blocksize = SHA224_BLOCK_SIZE,
1579 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1580 sizeof(struct omap_sham_hmac_ctx),
1581 .cra_module = THIS_MODULE,
1582 .cra_init = omap_sham_cra_sha224_init,
1583 .cra_exit = omap_sham_cra_exit,
1584 },
1585 .op.do_one_request = omap_sham_hash_one_req,
1586 },
1587 {
1588 .base.init = omap_sham_init,
1589 .base.update = omap_sham_update,
1590 .base.final = omap_sham_final,
1591 .base.finup = omap_sham_finup,
1592 .base.digest = omap_sham_digest,
1593 .base.setkey = omap_sham_setkey,
1594 .base.halg.digestsize = SHA256_DIGEST_SIZE,
1595 .base.halg.base = {
1596 .cra_name = "hmac(sha256)",
1597 .cra_driver_name = "omap-hmac-sha256",
1598 .cra_priority = 400,
1599 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1600 CRYPTO_ALG_ASYNC |
1601 CRYPTO_ALG_NEED_FALLBACK,
1602 .cra_blocksize = SHA256_BLOCK_SIZE,
1603 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1604 sizeof(struct omap_sham_hmac_ctx),
1605 .cra_module = THIS_MODULE,
1606 .cra_init = omap_sham_cra_sha256_init,
1607 .cra_exit = omap_sham_cra_exit,
1608 },
1609 .op.do_one_request = omap_sham_hash_one_req,
1610 },
1611 };
1612
1613 static struct ahash_engine_alg algs_sha384_sha512[] = {
1614 {
1615 .base.init = omap_sham_init,
1616 .base.update = omap_sham_update,
1617 .base.final = omap_sham_final,
1618 .base.finup = omap_sham_finup,
1619 .base.digest = omap_sham_digest,
1620 .base.halg.digestsize = SHA384_DIGEST_SIZE,
1621 .base.halg.base = {
1622 .cra_name = "sha384",
1623 .cra_driver_name = "omap-sha384",
1624 .cra_priority = 400,
1625 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1626 CRYPTO_ALG_ASYNC |
1627 CRYPTO_ALG_NEED_FALLBACK,
1628 .cra_blocksize = SHA384_BLOCK_SIZE,
1629 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1630 .cra_module = THIS_MODULE,
1631 .cra_init = omap_sham_cra_init,
1632 .cra_exit = omap_sham_cra_exit,
1633 },
1634 .op.do_one_request = omap_sham_hash_one_req,
1635 },
1636 {
1637 .base.init = omap_sham_init,
1638 .base.update = omap_sham_update,
1639 .base.final = omap_sham_final,
1640 .base.finup = omap_sham_finup,
1641 .base.digest = omap_sham_digest,
1642 .base.halg.digestsize = SHA512_DIGEST_SIZE,
1643 .base.halg.base = {
1644 .cra_name = "sha512",
1645 .cra_driver_name = "omap-sha512",
1646 .cra_priority = 400,
1647 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1648 CRYPTO_ALG_ASYNC |
1649 CRYPTO_ALG_NEED_FALLBACK,
1650 .cra_blocksize = SHA512_BLOCK_SIZE,
1651 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1652 .cra_module = THIS_MODULE,
1653 .cra_init = omap_sham_cra_init,
1654 .cra_exit = omap_sham_cra_exit,
1655 },
1656 .op.do_one_request = omap_sham_hash_one_req,
1657 },
1658 {
1659 .base.init = omap_sham_init,
1660 .base.update = omap_sham_update,
1661 .base.final = omap_sham_final,
1662 .base.finup = omap_sham_finup,
1663 .base.digest = omap_sham_digest,
1664 .base.setkey = omap_sham_setkey,
1665 .base.halg.digestsize = SHA384_DIGEST_SIZE,
1666 .base.halg.base = {
1667 .cra_name = "hmac(sha384)",
1668 .cra_driver_name = "omap-hmac-sha384",
1669 .cra_priority = 400,
1670 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1671 CRYPTO_ALG_ASYNC |
1672 CRYPTO_ALG_NEED_FALLBACK,
1673 .cra_blocksize = SHA384_BLOCK_SIZE,
1674 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1675 sizeof(struct omap_sham_hmac_ctx),
1676 .cra_module = THIS_MODULE,
1677 .cra_init = omap_sham_cra_sha384_init,
1678 .cra_exit = omap_sham_cra_exit,
1679 },
1680 .op.do_one_request = omap_sham_hash_one_req,
1681 },
1682 {
1683 .base.init = omap_sham_init,
1684 .base.update = omap_sham_update,
1685 .base.final = omap_sham_final,
1686 .base.finup = omap_sham_finup,
1687 .base.digest = omap_sham_digest,
1688 .base.setkey = omap_sham_setkey,
1689 .base.halg.digestsize = SHA512_DIGEST_SIZE,
1690 .base.halg.base = {
1691 .cra_name = "hmac(sha512)",
1692 .cra_driver_name = "omap-hmac-sha512",
1693 .cra_priority = 400,
1694 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1695 CRYPTO_ALG_ASYNC |
1696 CRYPTO_ALG_NEED_FALLBACK,
1697 .cra_blocksize = SHA512_BLOCK_SIZE,
1698 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1699 sizeof(struct omap_sham_hmac_ctx),
1700 .cra_module = THIS_MODULE,
1701 .cra_init = omap_sham_cra_sha512_init,
1702 .cra_exit = omap_sham_cra_exit,
1703 },
1704 .op.do_one_request = omap_sham_hash_one_req,
1705 },
1706 };
1707
omap_sham_done_task(struct work_struct * t)1708 static void omap_sham_done_task(struct work_struct *t)
1709 {
1710 struct omap_sham_dev *dd = from_work(dd, t, done_task);
1711 int err = 0;
1712
1713 dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags);
1714
1715 if (test_bit(FLAGS_CPU, &dd->flags)) {
1716 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1717 goto finish;
1718 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1719 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1720 omap_sham_update_dma_stop(dd);
1721 if (dd->err) {
1722 err = dd->err;
1723 goto finish;
1724 }
1725 }
1726 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1727 /* hash or semi-hash ready */
1728 clear_bit(FLAGS_DMA_READY, &dd->flags);
1729 goto finish;
1730 }
1731 }
1732
1733 return;
1734
1735 finish:
1736 dev_dbg(dd->dev, "update done: err: %d\n", err);
1737 /* finish curent request */
1738 omap_sham_finish_req(dd->req, err);
1739 }
1740
omap_sham_irq_common(struct omap_sham_dev * dd)1741 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1742 {
1743 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1744 queue_work(system_bh_wq, &dd->done_task);
1745
1746 return IRQ_HANDLED;
1747 }
1748
omap_sham_irq_omap2(int irq,void * dev_id)1749 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1750 {
1751 struct omap_sham_dev *dd = dev_id;
1752
1753 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1754 /* final -> allow device to go to power-saving mode */
1755 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1756
1757 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1758 SHA_REG_CTRL_OUTPUT_READY);
1759 omap_sham_read(dd, SHA_REG_CTRL);
1760
1761 return omap_sham_irq_common(dd);
1762 }
1763
omap_sham_irq_omap4(int irq,void * dev_id)1764 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1765 {
1766 struct omap_sham_dev *dd = dev_id;
1767
1768 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1769
1770 return omap_sham_irq_common(dd);
1771 }
1772
1773 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1774 {
1775 .algs_list = algs_sha1_md5,
1776 .size = ARRAY_SIZE(algs_sha1_md5),
1777 },
1778 };
1779
1780 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1781 .algs_info = omap_sham_algs_info_omap2,
1782 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1783 .flags = BIT(FLAGS_BE32_SHA1),
1784 .digest_size = SHA1_DIGEST_SIZE,
1785 .copy_hash = omap_sham_copy_hash_omap2,
1786 .write_ctrl = omap_sham_write_ctrl_omap2,
1787 .trigger = omap_sham_trigger_omap2,
1788 .poll_irq = omap_sham_poll_irq_omap2,
1789 .intr_hdlr = omap_sham_irq_omap2,
1790 .idigest_ofs = 0x00,
1791 .din_ofs = 0x1c,
1792 .digcnt_ofs = 0x14,
1793 .rev_ofs = 0x5c,
1794 .mask_ofs = 0x60,
1795 .sysstatus_ofs = 0x64,
1796 .major_mask = 0xf0,
1797 .major_shift = 4,
1798 .minor_mask = 0x0f,
1799 .minor_shift = 0,
1800 };
1801
1802 #ifdef CONFIG_OF
1803 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1804 {
1805 .algs_list = algs_sha1_md5,
1806 .size = ARRAY_SIZE(algs_sha1_md5),
1807 },
1808 {
1809 .algs_list = algs_sha224_sha256,
1810 .size = ARRAY_SIZE(algs_sha224_sha256),
1811 },
1812 };
1813
1814 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1815 .algs_info = omap_sham_algs_info_omap4,
1816 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1817 .flags = BIT(FLAGS_AUTO_XOR),
1818 .digest_size = SHA256_DIGEST_SIZE,
1819 .copy_hash = omap_sham_copy_hash_omap4,
1820 .write_ctrl = omap_sham_write_ctrl_omap4,
1821 .trigger = omap_sham_trigger_omap4,
1822 .poll_irq = omap_sham_poll_irq_omap4,
1823 .intr_hdlr = omap_sham_irq_omap4,
1824 .idigest_ofs = 0x020,
1825 .odigest_ofs = 0x0,
1826 .din_ofs = 0x080,
1827 .digcnt_ofs = 0x040,
1828 .rev_ofs = 0x100,
1829 .mask_ofs = 0x110,
1830 .sysstatus_ofs = 0x114,
1831 .mode_ofs = 0x44,
1832 .length_ofs = 0x48,
1833 .major_mask = 0x0700,
1834 .major_shift = 8,
1835 .minor_mask = 0x003f,
1836 .minor_shift = 0,
1837 };
1838
1839 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1840 {
1841 .algs_list = algs_sha1_md5,
1842 .size = ARRAY_SIZE(algs_sha1_md5),
1843 },
1844 {
1845 .algs_list = algs_sha224_sha256,
1846 .size = ARRAY_SIZE(algs_sha224_sha256),
1847 },
1848 {
1849 .algs_list = algs_sha384_sha512,
1850 .size = ARRAY_SIZE(algs_sha384_sha512),
1851 },
1852 };
1853
1854 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1855 .algs_info = omap_sham_algs_info_omap5,
1856 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1857 .flags = BIT(FLAGS_AUTO_XOR),
1858 .digest_size = SHA512_DIGEST_SIZE,
1859 .copy_hash = omap_sham_copy_hash_omap4,
1860 .write_ctrl = omap_sham_write_ctrl_omap4,
1861 .trigger = omap_sham_trigger_omap4,
1862 .poll_irq = omap_sham_poll_irq_omap4,
1863 .intr_hdlr = omap_sham_irq_omap4,
1864 .idigest_ofs = 0x240,
1865 .odigest_ofs = 0x200,
1866 .din_ofs = 0x080,
1867 .digcnt_ofs = 0x280,
1868 .rev_ofs = 0x100,
1869 .mask_ofs = 0x110,
1870 .sysstatus_ofs = 0x114,
1871 .mode_ofs = 0x284,
1872 .length_ofs = 0x288,
1873 .major_mask = 0x0700,
1874 .major_shift = 8,
1875 .minor_mask = 0x003f,
1876 .minor_shift = 0,
1877 };
1878
1879 static const struct of_device_id omap_sham_of_match[] = {
1880 {
1881 .compatible = "ti,omap2-sham",
1882 .data = &omap_sham_pdata_omap2,
1883 },
1884 {
1885 .compatible = "ti,omap3-sham",
1886 .data = &omap_sham_pdata_omap2,
1887 },
1888 {
1889 .compatible = "ti,omap4-sham",
1890 .data = &omap_sham_pdata_omap4,
1891 },
1892 {
1893 .compatible = "ti,omap5-sham",
1894 .data = &omap_sham_pdata_omap5,
1895 },
1896 {},
1897 };
1898 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1899
omap_sham_get_res_of(struct omap_sham_dev * dd,struct device * dev,struct resource * res)1900 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1901 struct device *dev, struct resource *res)
1902 {
1903 struct device_node *node = dev->of_node;
1904 int err = 0;
1905
1906 dd->pdata = of_device_get_match_data(dev);
1907 if (!dd->pdata) {
1908 dev_err(dev, "no compatible OF match\n");
1909 err = -EINVAL;
1910 goto err;
1911 }
1912
1913 err = of_address_to_resource(node, 0, res);
1914 if (err < 0) {
1915 dev_err(dev, "can't translate OF node address\n");
1916 err = -EINVAL;
1917 goto err;
1918 }
1919
1920 dd->irq = irq_of_parse_and_map(node, 0);
1921 if (!dd->irq) {
1922 dev_err(dev, "can't translate OF irq value\n");
1923 err = -EINVAL;
1924 goto err;
1925 }
1926
1927 err:
1928 return err;
1929 }
1930 #else
1931 static const struct of_device_id omap_sham_of_match[] = {
1932 {},
1933 };
1934
omap_sham_get_res_of(struct omap_sham_dev * dd,struct device * dev,struct resource * res)1935 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1936 struct device *dev, struct resource *res)
1937 {
1938 return -EINVAL;
1939 }
1940 #endif
1941
omap_sham_get_res_pdev(struct omap_sham_dev * dd,struct platform_device * pdev,struct resource * res)1942 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1943 struct platform_device *pdev, struct resource *res)
1944 {
1945 struct device *dev = &pdev->dev;
1946 struct resource *r;
1947 int err = 0;
1948
1949 /* Get the base address */
1950 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1951 if (!r) {
1952 dev_err(dev, "no MEM resource info\n");
1953 err = -ENODEV;
1954 goto err;
1955 }
1956 memcpy(res, r, sizeof(*res));
1957
1958 /* Get the IRQ */
1959 dd->irq = platform_get_irq(pdev, 0);
1960 if (dd->irq < 0) {
1961 err = dd->irq;
1962 goto err;
1963 }
1964
1965 /* Only OMAP2/3 can be non-DT */
1966 dd->pdata = &omap_sham_pdata_omap2;
1967
1968 err:
1969 return err;
1970 }
1971
fallback_show(struct device * dev,struct device_attribute * attr,char * buf)1972 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1973 char *buf)
1974 {
1975 struct omap_sham_dev *dd = dev_get_drvdata(dev);
1976
1977 return sysfs_emit(buf, "%d\n", dd->fallback_sz);
1978 }
1979
fallback_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)1980 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1981 const char *buf, size_t size)
1982 {
1983 struct omap_sham_dev *dd = dev_get_drvdata(dev);
1984 ssize_t status;
1985 long value;
1986
1987 status = kstrtol(buf, 0, &value);
1988 if (status)
1989 return status;
1990
1991 /* HW accelerator only works with buffers > 9 */
1992 if (value < 9) {
1993 dev_err(dev, "minimum fallback size 9\n");
1994 return -EINVAL;
1995 }
1996
1997 dd->fallback_sz = value;
1998
1999 return size;
2000 }
2001
queue_len_show(struct device * dev,struct device_attribute * attr,char * buf)2002 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2003 char *buf)
2004 {
2005 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2006
2007 return sysfs_emit(buf, "%d\n", dd->queue.max_qlen);
2008 }
2009
queue_len_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)2010 static ssize_t queue_len_store(struct device *dev,
2011 struct device_attribute *attr, const char *buf,
2012 size_t size)
2013 {
2014 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2015 ssize_t status;
2016 long value;
2017
2018 status = kstrtol(buf, 0, &value);
2019 if (status)
2020 return status;
2021
2022 if (value < 1)
2023 return -EINVAL;
2024
2025 /*
2026 * Changing the queue size in fly is safe, if size becomes smaller
2027 * than current size, it will just not accept new entries until
2028 * it has shrank enough.
2029 */
2030 dd->queue.max_qlen = value;
2031
2032 return size;
2033 }
2034
2035 static DEVICE_ATTR_RW(queue_len);
2036 static DEVICE_ATTR_RW(fallback);
2037
2038 static struct attribute *omap_sham_attrs[] = {
2039 &dev_attr_queue_len.attr,
2040 &dev_attr_fallback.attr,
2041 NULL,
2042 };
2043 ATTRIBUTE_GROUPS(omap_sham);
2044
omap_sham_probe(struct platform_device * pdev)2045 static int omap_sham_probe(struct platform_device *pdev)
2046 {
2047 struct omap_sham_dev *dd;
2048 struct device *dev = &pdev->dev;
2049 struct resource res;
2050 dma_cap_mask_t mask;
2051 int err, i, j;
2052 u32 rev;
2053
2054 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2055 if (dd == NULL) {
2056 dev_err(dev, "unable to alloc data struct.\n");
2057 err = -ENOMEM;
2058 goto data_err;
2059 }
2060 dd->dev = dev;
2061 platform_set_drvdata(pdev, dd);
2062
2063 INIT_LIST_HEAD(&dd->list);
2064 INIT_WORK(&dd->done_task, omap_sham_done_task);
2065 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2066
2067 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2068 omap_sham_get_res_pdev(dd, pdev, &res);
2069 if (err)
2070 goto data_err;
2071
2072 dd->io_base = devm_ioremap_resource(dev, &res);
2073 if (IS_ERR(dd->io_base)) {
2074 err = PTR_ERR(dd->io_base);
2075 goto data_err;
2076 }
2077 dd->phys_base = res.start;
2078
2079 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2080 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2081 if (err) {
2082 dev_err(dev, "unable to request irq %d, err = %d\n",
2083 dd->irq, err);
2084 goto data_err;
2085 }
2086
2087 dma_cap_zero(mask);
2088 dma_cap_set(DMA_SLAVE, mask);
2089
2090 dd->dma_lch = dma_request_chan(dev, "rx");
2091 if (IS_ERR(dd->dma_lch)) {
2092 err = PTR_ERR(dd->dma_lch);
2093 if (err == -EPROBE_DEFER)
2094 goto data_err;
2095
2096 dd->polling_mode = 1;
2097 dev_dbg(dev, "using polling mode instead of dma\n");
2098 }
2099
2100 dd->flags |= dd->pdata->flags;
2101 sham.flags |= dd->pdata->flags;
2102
2103 pm_runtime_use_autosuspend(dev);
2104 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2105
2106 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2107
2108 pm_runtime_enable(dev);
2109
2110 err = pm_runtime_resume_and_get(dev);
2111 if (err < 0) {
2112 dev_err(dev, "failed to get sync: %d\n", err);
2113 goto err_pm;
2114 }
2115
2116 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2117 pm_runtime_put_sync(&pdev->dev);
2118
2119 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2120 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2121 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2122
2123 spin_lock_bh(&sham.lock);
2124 list_add_tail(&dd->list, &sham.dev_list);
2125 spin_unlock_bh(&sham.lock);
2126
2127 dd->engine = crypto_engine_alloc_init(dev, 1);
2128 if (!dd->engine) {
2129 err = -ENOMEM;
2130 goto err_engine;
2131 }
2132
2133 err = crypto_engine_start(dd->engine);
2134 if (err)
2135 goto err_engine_start;
2136
2137 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2138 if (dd->pdata->algs_info[i].registered)
2139 break;
2140
2141 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2142 struct ahash_engine_alg *ealg;
2143 struct ahash_alg *alg;
2144
2145 ealg = &dd->pdata->algs_info[i].algs_list[j];
2146 alg = &ealg->base;
2147 alg->export = omap_sham_export;
2148 alg->import = omap_sham_import;
2149 alg->halg.statesize = sizeof(struct omap_sham_reqctx);
2150 err = crypto_engine_register_ahash(ealg);
2151 if (err)
2152 goto err_algs;
2153
2154 dd->pdata->algs_info[i].registered++;
2155 }
2156 }
2157
2158 return 0;
2159
2160 err_algs:
2161 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2162 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2163 crypto_engine_unregister_ahash(
2164 &dd->pdata->algs_info[i].algs_list[j]);
2165 err_engine_start:
2166 crypto_engine_exit(dd->engine);
2167 err_engine:
2168 spin_lock_bh(&sham.lock);
2169 list_del(&dd->list);
2170 spin_unlock_bh(&sham.lock);
2171 err_pm:
2172 pm_runtime_dont_use_autosuspend(dev);
2173 pm_runtime_disable(dev);
2174 if (!dd->polling_mode)
2175 dma_release_channel(dd->dma_lch);
2176 data_err:
2177 dev_err(dev, "initialization failed.\n");
2178
2179 return err;
2180 }
2181
omap_sham_remove(struct platform_device * pdev)2182 static void omap_sham_remove(struct platform_device *pdev)
2183 {
2184 struct omap_sham_dev *dd;
2185 int i, j;
2186
2187 dd = platform_get_drvdata(pdev);
2188
2189 spin_lock_bh(&sham.lock);
2190 list_del(&dd->list);
2191 spin_unlock_bh(&sham.lock);
2192 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2193 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2194 crypto_engine_unregister_ahash(
2195 &dd->pdata->algs_info[i].algs_list[j]);
2196 dd->pdata->algs_info[i].registered--;
2197 }
2198 cancel_work_sync(&dd->done_task);
2199 pm_runtime_dont_use_autosuspend(&pdev->dev);
2200 pm_runtime_disable(&pdev->dev);
2201
2202 if (!dd->polling_mode)
2203 dma_release_channel(dd->dma_lch);
2204 }
2205
2206 static struct platform_driver omap_sham_driver = {
2207 .probe = omap_sham_probe,
2208 .remove = omap_sham_remove,
2209 .driver = {
2210 .name = "omap-sham",
2211 .of_match_table = omap_sham_of_match,
2212 .dev_groups = omap_sham_groups,
2213 },
2214 };
2215
2216 module_platform_driver(omap_sham_driver);
2217
2218 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2219 MODULE_LICENSE("GPL v2");
2220 MODULE_AUTHOR("Dmitry Kasatkin");
2221 MODULE_ALIAS("platform:omap-sham");
2222