Searched refs:SEC_CONTROL_REG (Results 1 – 1 of 1) sorted by relevance
56 #define SEC_CONTROL_REG 0x301200 macro479 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()487 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()608 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()610 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()626 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()628 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()649 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()651 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()726 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()[all …]