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Searched refs:SDMA0_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v3_0.c581 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
1334 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1339 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1350 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1355 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
H A Dsdma_v2_4.c996 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1001 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1012 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1017 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
H A Dsdma_v5_0.c630 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_0_ctx_switch_enable()
794 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v5_0_gfx_resume_instance()
797 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); in sdma_v5_0_gfx_resume_instance()
1608 cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0); in sdma_v5_0_stop_queue()
1694 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_0_set_trap_irq_state()
H A Dsdma_v5_2.c489 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_2_ctx_switch_enable()
641 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v5_2_gfx_resume_instance()
644 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); in sdma_v5_2_gfx_resume_instance()
1523 cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0); in sdma_v5_2_stop_queue()
1606 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_2_set_trap_irq_state()
H A Dsdma_v4_0.c1012 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable()
1415 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v4_0_start()
2067 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
H A Dsdma_v6_0.c437 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v6_0_ctxempty_int_enable()
1610 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v6_0_set_trap_irq_state()
H A Dsdma_v7_0.c1535 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v7_0_set_trap_irq_state()
/linux/drivers/gpu/drm/radeon/
H A Dcik_reg.h204 #define SDMA0_CNTL 0xD010 macro
H A Dcik_sdma.c313 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
318 WREG32(SDMA0_CNTL + reg_offset, value); in cik_sdma_ctx_switch_enable()
H A Dcikd.h1960 #define SDMA0_CNTL 0xD010 macro