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Searched refs:R_P0_RXCK (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/net/wireless/realtek/rtw89/ !
H A Drtw8851b_rfk.c179 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0); in _txck_force()
184 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck); in _txck_force()
185 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1); in _txck_force()
195 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0); in _rxck_force()
199 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck); in _rxck_force()
200 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1); in _rxck_force()
218 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 8), B_P0_RXCK_ADJ, data[6]); in _rxck_force()
1964 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), B_P0_TXCK_ALL, 0x00); in _dpk_bb_afe_restore()
H A Drtw8852a_rfk.c1030 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _iqk_rxclk_setting()
1032 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _iqk_rxclk_setting()
1038 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _iqk_rxclk_setting()
1040 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _iqk_rxclk_setting()
1685 ori_val = rtw89_phy_read32_mask(rtwdev, R_P0_RXCK + (path << 13), MASKDWORD); in _set_rx_dck()
1689 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _set_rx_dck()
1690 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _set_rx_dck()
1718 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _set_rx_dck()
H A Drtw8851b.c1201 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); in rtw8851b_bw_setting()
1210 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); in rtw8851b_bw_setting()
1219 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); in rtw8851b_bw_setting()
1228 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); in rtw8851b_bw_setting()
1237 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92); in rtw8851b_bw_setting()
H A Drtw8852bt_rfk.c256 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0); in _txck_force()
261 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck); in _txck_force()
262 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1); in _txck_force()
271 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0); in _rxck_force()
276 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck); in _rxck_force()
277 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1); in _rxck_force()
353 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_TXCK_ALL, 0x00); in _rfk_bb_afe_restore()
1616 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_TXCK_ALL, 0x00); in _iqk_afebb_restore()
H A Drtw8852c_rfk.c446 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0); in rtw8852c_txck_force()
451 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck); in rtw8852c_txck_force()
452 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1); in rtw8852c_txck_force()
460 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0); in rtw8852c_rxck_force()
465 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck); in rtw8852c_rxck_force()
466 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1); in rtw8852c_rxck_force()
1973 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), B_P0_TXCK_ALL, 0x00); in _dpk_bb_afe_restore()
H A Drtw8852b_rfk.c991 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x2); in _iqk_rxclk_setting()
992 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1); in _iqk_rxclk_setting()
1007 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x1); in _iqk_rxclk_setting()
1008 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1); in _iqk_rxclk_setting()
H A Dreg.h8884 #define R_P0_RXCK 0x12A0 macro