1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2024 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "debug.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852b_common.h"
11 #include "sar.h"
12 #include "util.h"
13
14 static const struct rtw89_reg3_def rtw8852bx_pmac_ht20_mcs7_tbl[] = {
15 {0x4580, 0x0000ffff, 0x0},
16 {0x4580, 0xffff0000, 0x0},
17 {0x4584, 0x0000ffff, 0x0},
18 {0x4584, 0xffff0000, 0x0},
19 {0x4580, 0x0000ffff, 0x1},
20 {0x4578, 0x00ffffff, 0x2018b},
21 {0x4570, 0x03ffffff, 0x7},
22 {0x4574, 0x03ffffff, 0x32407},
23 {0x45b8, 0x00000010, 0x0},
24 {0x45b8, 0x00000100, 0x0},
25 {0x45b8, 0x00000080, 0x0},
26 {0x45b8, 0x00000008, 0x0},
27 {0x45a0, 0x0000ff00, 0x0},
28 {0x45a0, 0xff000000, 0x1},
29 {0x45a4, 0x0000ff00, 0x2},
30 {0x45a4, 0xff000000, 0x3},
31 {0x45b8, 0x00000020, 0x0},
32 {0x4568, 0xe0000000, 0x0},
33 {0x45b8, 0x00000002, 0x1},
34 {0x456c, 0xe0000000, 0x0},
35 {0x45b4, 0x00006000, 0x0},
36 {0x45b4, 0x00001800, 0x1},
37 {0x45b8, 0x00000040, 0x0},
38 {0x45b8, 0x00000004, 0x0},
39 {0x45b8, 0x00000200, 0x0},
40 {0x4598, 0xf8000000, 0x0},
41 {0x45b8, 0x00100000, 0x0},
42 {0x45a8, 0x00000fc0, 0x0},
43 {0x45b8, 0x00200000, 0x0},
44 {0x45b0, 0x00000038, 0x0},
45 {0x45b0, 0x000001c0, 0x0},
46 {0x45a0, 0x000000ff, 0x0},
47 {0x45b8, 0x00400000, 0x0},
48 {0x4590, 0x000007ff, 0x0},
49 {0x45b0, 0x00000e00, 0x0},
50 {0x45ac, 0x0000001f, 0x0},
51 {0x45b8, 0x00800000, 0x0},
52 {0x45a8, 0x0003f000, 0x0},
53 {0x45b8, 0x01000000, 0x0},
54 {0x45b0, 0x00007000, 0x0},
55 {0x45b0, 0x00038000, 0x0},
56 {0x45a0, 0x00ff0000, 0x0},
57 {0x45b8, 0x02000000, 0x0},
58 {0x4590, 0x003ff800, 0x0},
59 {0x45b0, 0x001c0000, 0x0},
60 {0x45ac, 0x000003e0, 0x0},
61 {0x45b8, 0x04000000, 0x0},
62 {0x45a8, 0x00fc0000, 0x0},
63 {0x45b8, 0x08000000, 0x0},
64 {0x45b0, 0x00e00000, 0x0},
65 {0x45b0, 0x07000000, 0x0},
66 {0x45a4, 0x000000ff, 0x0},
67 {0x45b8, 0x10000000, 0x0},
68 {0x4594, 0x000007ff, 0x0},
69 {0x45b0, 0x38000000, 0x0},
70 {0x45ac, 0x00007c00, 0x0},
71 {0x45b8, 0x20000000, 0x0},
72 {0x45a8, 0x3f000000, 0x0},
73 {0x45b8, 0x40000000, 0x0},
74 {0x45b4, 0x00000007, 0x0},
75 {0x45b4, 0x00000038, 0x0},
76 {0x45a4, 0x00ff0000, 0x0},
77 {0x45b8, 0x80000000, 0x0},
78 {0x4594, 0x003ff800, 0x0},
79 {0x45b4, 0x000001c0, 0x0},
80 {0x4598, 0xf8000000, 0x0},
81 {0x45b8, 0x00100000, 0x0},
82 {0x45a8, 0x00000fc0, 0x7},
83 {0x45b8, 0x00200000, 0x0},
84 {0x45b0, 0x00000038, 0x0},
85 {0x45b0, 0x000001c0, 0x0},
86 {0x45a0, 0x000000ff, 0x0},
87 {0x45b4, 0x06000000, 0x0},
88 {0x45b0, 0x00000007, 0x0},
89 {0x45b8, 0x00080000, 0x0},
90 {0x45a8, 0x0000003f, 0x0},
91 {0x457c, 0xffe00000, 0x1},
92 {0x4530, 0xffffffff, 0x0},
93 {0x4588, 0x00003fff, 0x0},
94 {0x4598, 0x000001ff, 0x0},
95 {0x4534, 0xffffffff, 0x0},
96 {0x4538, 0xffffffff, 0x0},
97 {0x453c, 0xffffffff, 0x0},
98 {0x4588, 0x0fffc000, 0x0},
99 {0x4598, 0x0003fe00, 0x0},
100 {0x4540, 0xffffffff, 0x0},
101 {0x4544, 0xffffffff, 0x0},
102 {0x4548, 0xffffffff, 0x0},
103 {0x458c, 0x00003fff, 0x0},
104 {0x4598, 0x07fc0000, 0x0},
105 {0x454c, 0xffffffff, 0x0},
106 {0x4550, 0xffffffff, 0x0},
107 {0x4554, 0xffffffff, 0x0},
108 {0x458c, 0x0fffc000, 0x0},
109 {0x459c, 0x000001ff, 0x0},
110 {0x4558, 0xffffffff, 0x0},
111 {0x455c, 0xffffffff, 0x0},
112 {0x4530, 0xffffffff, 0x4e790001},
113 {0x4588, 0x00003fff, 0x0},
114 {0x4598, 0x000001ff, 0x1},
115 {0x4534, 0xffffffff, 0x0},
116 {0x4538, 0xffffffff, 0x4b},
117 {0x45ac, 0x38000000, 0x7},
118 {0x4588, 0xf0000000, 0x0},
119 {0x459c, 0x7e000000, 0x0},
120 {0x45b8, 0x00040000, 0x0},
121 {0x45b8, 0x00020000, 0x0},
122 {0x4590, 0xffc00000, 0x0},
123 {0x45b8, 0x00004000, 0x0},
124 {0x4578, 0xff000000, 0x0},
125 {0x45b8, 0x00000400, 0x0},
126 {0x45b8, 0x00000800, 0x0},
127 {0x45b8, 0x00001000, 0x0},
128 {0x45b8, 0x00002000, 0x0},
129 {0x45b4, 0x00018000, 0x0},
130 {0x45ac, 0x07800000, 0x0},
131 {0x45b4, 0x00000600, 0x2},
132 {0x459c, 0x0001fe00, 0x80},
133 {0x45ac, 0x00078000, 0x3},
134 {0x459c, 0x01fe0000, 0x1},
135 };
136
137 static const struct rtw89_reg3_def rtw8852bx_btc_preagc_en_defs[] = {
138 {0x46D0, GENMASK(1, 0), 0x3},
139 {0x4790, GENMASK(1, 0), 0x3},
140 {0x4AD4, GENMASK(31, 0), 0xf},
141 {0x4AE0, GENMASK(31, 0), 0xf},
142 {0x4688, GENMASK(31, 24), 0x80},
143 {0x476C, GENMASK(31, 24), 0x80},
144 {0x4694, GENMASK(7, 0), 0x80},
145 {0x4694, GENMASK(15, 8), 0x80},
146 {0x4778, GENMASK(7, 0), 0x80},
147 {0x4778, GENMASK(15, 8), 0x80},
148 {0x4AE4, GENMASK(23, 0), 0x780D1E},
149 {0x4AEC, GENMASK(23, 0), 0x780D1E},
150 {0x469C, GENMASK(31, 26), 0x34},
151 {0x49F0, GENMASK(31, 26), 0x34},
152 };
153
154 static DECLARE_PHY_REG3_TBL(rtw8852bx_btc_preagc_en_defs);
155
156 static const struct rtw89_reg3_def rtw8852bx_btc_preagc_dis_defs[] = {
157 {0x46D0, GENMASK(1, 0), 0x0},
158 {0x4790, GENMASK(1, 0), 0x0},
159 {0x4AD4, GENMASK(31, 0), 0x60},
160 {0x4AE0, GENMASK(31, 0), 0x60},
161 {0x4688, GENMASK(31, 24), 0x1a},
162 {0x476C, GENMASK(31, 24), 0x1a},
163 {0x4694, GENMASK(7, 0), 0x2a},
164 {0x4694, GENMASK(15, 8), 0x2a},
165 {0x4778, GENMASK(7, 0), 0x2a},
166 {0x4778, GENMASK(15, 8), 0x2a},
167 {0x4AE4, GENMASK(23, 0), 0x79E99E},
168 {0x4AEC, GENMASK(23, 0), 0x79E99E},
169 {0x469C, GENMASK(31, 26), 0x26},
170 {0x49F0, GENMASK(31, 26), 0x26},
171 };
172
173 static DECLARE_PHY_REG3_TBL(rtw8852bx_btc_preagc_dis_defs);
174
rtw8852bx_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8852bx_efuse * map)175 static void rtw8852bx_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
176 struct rtw8852bx_efuse *map)
177 {
178 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
179 struct rtw8852bx_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
180 u8 i, j;
181
182 tssi->thermal[RF_PATH_A] = map->path_a_therm;
183 tssi->thermal[RF_PATH_B] = map->path_b_therm;
184
185 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
186 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
187 sizeof(ofst[i]->cck_tssi));
188
189 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
190 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
191 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
192 i, j, tssi->tssi_cck[i][j]);
193
194 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
195 sizeof(ofst[i]->bw40_tssi));
196 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
197 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
198
199 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
200 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
201 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
202 i, j, tssi->tssi_mcs[i][j]);
203 }
204 }
205
_decode_efuse_gain(u8 data,s8 * high,s8 * low)206 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
207 {
208 if (high)
209 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);
210 if (low)
211 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);
212
213 return data != 0xff;
214 }
215
rtw8852bx_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8852bx_efuse * map)216 static void rtw8852bx_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
217 struct rtw8852bx_efuse *map)
218 {
219 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
220 bool valid = false;
221
222 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
223 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
224 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
225 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
226 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
227 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
228 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
229 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
230 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
231 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
232 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
233 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
234 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
235 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
236 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
237
238 gain->offset_valid = valid;
239 }
240
__rtw8852bx_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)241 static int __rtw8852bx_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
242 enum rtw89_efuse_block block)
243 {
244 struct rtw89_efuse *efuse = &rtwdev->efuse;
245 struct rtw8852bx_efuse *map;
246
247 map = (struct rtw8852bx_efuse *)log_map;
248
249 efuse->country_code[0] = map->country_code[0];
250 efuse->country_code[1] = map->country_code[1];
251 rtw8852bx_efuse_parsing_tssi(rtwdev, map);
252 rtw8852bx_efuse_parsing_gain_offset(rtwdev, map);
253
254 switch (rtwdev->hci.type) {
255 case RTW89_HCI_TYPE_PCIE:
256 ether_addr_copy(efuse->addr, map->e.mac_addr);
257 break;
258 case RTW89_HCI_TYPE_USB:
259 ether_addr_copy(efuse->addr, map->u.mac_addr);
260 break;
261 default:
262 return -EOPNOTSUPP;
263 }
264
265 efuse->rfe_type = map->rfe_type;
266 efuse->xtal_cap = map->xtal_k;
267
268 return 0;
269 }
270
rtw8852bx_phycap_parsing_power_cal(struct rtw89_dev * rtwdev,u8 * phycap_map)271 static void rtw8852bx_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map)
272 {
273 #define PWR_K_CHK_OFFSET 0x5E9
274 #define PWR_K_CHK_VALUE 0xAA
275 u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr;
276
277 if (phycap_map[offset] == PWR_K_CHK_VALUE)
278 rtwdev->efuse.power_k_valid = true;
279 }
280
rtw8852bx_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)281 static void rtw8852bx_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
282 {
283 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
284 static const u32 tssi_trim_addr[RF_PATH_NUM_8852BX] = {0x5D6, 0x5AB};
285 u32 addr = rtwdev->chip->phycap_addr;
286 bool pg = false;
287 u32 ofst;
288 u8 i, j;
289
290 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
291 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
292 /* addrs are in decreasing order */
293 ofst = tssi_trim_addr[i] - addr - j;
294 tssi->tssi_trim[i][j] = phycap_map[ofst];
295
296 if (phycap_map[ofst] != 0xff)
297 pg = true;
298 }
299 }
300
301 if (!pg) {
302 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
303 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
304 "[TSSI][TRIM] no PG, set all trim info to 0\n");
305 }
306
307 for (i = 0; i < RF_PATH_NUM_8852BX; i++)
308 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
309 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
310 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
311 i, j, tssi->tssi_trim[i][j],
312 tssi_trim_addr[i] - j);
313 }
314
rtw8852bx_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)315 static void rtw8852bx_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
316 u8 *phycap_map)
317 {
318 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
319 static const u32 thm_trim_addr[RF_PATH_NUM_8852BX] = {0x5DF, 0x5DC};
320 u32 addr = rtwdev->chip->phycap_addr;
321 u8 i;
322
323 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
324 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
325
326 rtw89_debug(rtwdev, RTW89_DBG_RFK,
327 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
328 i, info->thermal_trim[i]);
329
330 if (info->thermal_trim[i] != 0xff)
331 info->pg_thermal_trim = true;
332 }
333 }
334
rtw8852bx_thermal_trim(struct rtw89_dev * rtwdev)335 static void rtw8852bx_thermal_trim(struct rtw89_dev *rtwdev)
336 {
337 #define __thm_setting(raw) \
338 ({ \
339 u8 __v = (raw); \
340 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
341 })
342 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
343 u8 i, val;
344
345 if (!info->pg_thermal_trim) {
346 rtw89_debug(rtwdev, RTW89_DBG_RFK,
347 "[THERMAL][TRIM] no PG, do nothing\n");
348
349 return;
350 }
351
352 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
353 val = __thm_setting(info->thermal_trim[i]);
354 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
355
356 rtw89_debug(rtwdev, RTW89_DBG_RFK,
357 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
358 i, val);
359 }
360 #undef __thm_setting
361 }
362
rtw8852bx_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)363 static void rtw8852bx_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
364 u8 *phycap_map)
365 {
366 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
367 static const u32 pabias_trim_addr[RF_PATH_NUM_8852BX] = {0x5DE, 0x5DB};
368 u32 addr = rtwdev->chip->phycap_addr;
369 u8 i;
370
371 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
372 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
373
374 rtw89_debug(rtwdev, RTW89_DBG_RFK,
375 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
376 i, info->pa_bias_trim[i]);
377
378 if (info->pa_bias_trim[i] != 0xff)
379 info->pg_pa_bias_trim = true;
380 }
381 }
382
rtw8852bx_pa_bias_trim(struct rtw89_dev * rtwdev)383 static void rtw8852bx_pa_bias_trim(struct rtw89_dev *rtwdev)
384 {
385 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
386 u8 pabias_2g, pabias_5g;
387 u8 i;
388
389 if (!info->pg_pa_bias_trim) {
390 rtw89_debug(rtwdev, RTW89_DBG_RFK,
391 "[PA_BIAS][TRIM] no PG, do nothing\n");
392
393 return;
394 }
395
396 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
397 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
398 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
399
400 rtw89_debug(rtwdev, RTW89_DBG_RFK,
401 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
402 i, pabias_2g, pabias_5g);
403
404 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
405 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
406 }
407 }
408
rtw8852bx_phycap_parsing_gain_comp(struct rtw89_dev * rtwdev,u8 * phycap_map)409 static void rtw8852bx_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
410 {
411 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
412 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
413 {0x590, 0x58F, 0, 0x58E, 0x58D},
414 };
415 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
416 u32 phycap_addr = rtwdev->chip->phycap_addr;
417 bool valid = false;
418 int path, i;
419 u8 data;
420
421 for (path = 0; path < 2; path++)
422 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
423 if (comp_addrs[path][i] == 0)
424 continue;
425
426 data = phycap_map[comp_addrs[path][i] - phycap_addr];
427 valid |= _decode_efuse_gain(data, NULL,
428 &gain->comp[path][i]);
429 }
430
431 gain->comp_valid = valid;
432 }
433
__rtw8852bx_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)434 static int __rtw8852bx_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
435 {
436 rtw8852bx_phycap_parsing_power_cal(rtwdev, phycap_map);
437 rtw8852bx_phycap_parsing_tssi(rtwdev, phycap_map);
438 rtw8852bx_phycap_parsing_thermal_trim(rtwdev, phycap_map);
439 rtw8852bx_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
440 rtw8852bx_phycap_parsing_gain_comp(rtwdev, phycap_map);
441
442 return 0;
443 }
444
__rtw8852bx_power_trim(struct rtw89_dev * rtwdev)445 static void __rtw8852bx_power_trim(struct rtw89_dev *rtwdev)
446 {
447 rtw8852bx_thermal_trim(rtwdev);
448 rtw8852bx_pa_bias_trim(rtwdev);
449 }
450
__rtw8852bx_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)451 static void __rtw8852bx_set_channel_mac(struct rtw89_dev *rtwdev,
452 const struct rtw89_chan *chan,
453 u8 mac_idx)
454 {
455 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
456 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
457 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
458 u8 txsc20 = 0, txsc40 = 0;
459
460 switch (chan->band_width) {
461 case RTW89_CHANNEL_WIDTH_80:
462 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
463 fallthrough;
464 case RTW89_CHANNEL_WIDTH_40:
465 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
466 break;
467 default:
468 break;
469 }
470
471 switch (chan->band_width) {
472 case RTW89_CHANNEL_WIDTH_80:
473 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
474 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
475 break;
476 case RTW89_CHANNEL_WIDTH_40:
477 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
478 rtw89_write32(rtwdev, sub_carr, txsc20);
479 break;
480 case RTW89_CHANNEL_WIDTH_20:
481 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
482 rtw89_write32(rtwdev, sub_carr, 0);
483 break;
484 default:
485 break;
486 }
487
488 if (chan->channel > 14) {
489 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
490 rtw89_write8_set(rtwdev, chk_rate,
491 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
492 } else {
493 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
494 rtw89_write8_clr(rtwdev, chk_rate,
495 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
496 }
497 }
498
499 static const u32 rtw8852bx_sco_barker_threshold[14] = {
500 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
501 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
502 };
503
504 static const u32 rtw8852bx_sco_cck_threshold[14] = {
505 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
506 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
507 };
508
rtw8852bx_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch)509 static void rtw8852bx_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
510 {
511 u8 ch_element = primary_ch - 1;
512
513 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
514 rtw8852bx_sco_barker_threshold[ch_element]);
515 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
516 rtw8852bx_sco_cck_threshold[ch_element]);
517 }
518
rtw8852bx_sco_mapping(u8 central_ch)519 static u8 rtw8852bx_sco_mapping(u8 central_ch)
520 {
521 if (central_ch == 1)
522 return 109;
523 else if (central_ch >= 2 && central_ch <= 6)
524 return 108;
525 else if (central_ch >= 7 && central_ch <= 10)
526 return 107;
527 else if (central_ch >= 11 && central_ch <= 14)
528 return 106;
529 else if (central_ch == 36 || central_ch == 38)
530 return 51;
531 else if (central_ch >= 40 && central_ch <= 58)
532 return 50;
533 else if (central_ch >= 60 && central_ch <= 64)
534 return 49;
535 else if (central_ch == 100 || central_ch == 102)
536 return 48;
537 else if (central_ch >= 104 && central_ch <= 126)
538 return 47;
539 else if (central_ch >= 128 && central_ch <= 151)
540 return 46;
541 else if (central_ch >= 153 && central_ch <= 177)
542 return 45;
543 else
544 return 0;
545 }
546
547 struct rtw8852bx_bb_gain {
548 u32 gain_g[BB_PATH_NUM_8852BX];
549 u32 gain_a[BB_PATH_NUM_8852BX];
550 u32 gain_mask;
551 };
552
553 static const struct rtw8852bx_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
554 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
555 .gain_mask = 0x00ff0000 },
556 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
557 .gain_mask = 0xff000000 },
558 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
559 .gain_mask = 0x000000ff },
560 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
561 .gain_mask = 0x0000ff00 },
562 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
563 .gain_mask = 0x00ff0000 },
564 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
565 .gain_mask = 0xff000000 },
566 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
567 .gain_mask = 0x000000ff },
568 };
569
570 static const struct rtw8852bx_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
571 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
572 .gain_mask = 0x00ff0000 },
573 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
574 .gain_mask = 0xff000000 },
575 };
576
rtw8852bx_set_gain_error(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_rf_path path)577 static void rtw8852bx_set_gain_error(struct rtw89_dev *rtwdev,
578 enum rtw89_subband subband,
579 enum rtw89_rf_path path)
580 {
581 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
582 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
583 s32 val;
584 u32 reg;
585 u32 mask;
586 int i;
587
588 for (i = 0; i < LNA_GAIN_NUM; i++) {
589 if (subband == RTW89_CH_2G)
590 reg = bb_gain_lna[i].gain_g[path];
591 else
592 reg = bb_gain_lna[i].gain_a[path];
593
594 mask = bb_gain_lna[i].gain_mask;
595 val = gain->lna_gain[gain_band][path][i];
596 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
597 }
598
599 for (i = 0; i < TIA_GAIN_NUM; i++) {
600 if (subband == RTW89_CH_2G)
601 reg = bb_gain_tia[i].gain_g[path];
602 else
603 reg = bb_gain_tia[i].gain_a[path];
604
605 mask = bb_gain_tia[i].gain_mask;
606 val = gain->tia_gain[gain_band][path][i];
607 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
608 }
609 }
610
rtw8852bt_ext_loss_avg_update(struct rtw89_dev * rtwdev,s8 ext_loss_a,s8 ext_loss_b)611 static void rtw8852bt_ext_loss_avg_update(struct rtw89_dev *rtwdev,
612 s8 ext_loss_a, s8 ext_loss_b)
613 {
614 s8 ext_loss_avg;
615 u64 linear;
616 u8 pwrofst;
617
618 if (ext_loss_a == ext_loss_b) {
619 ext_loss_avg = ext_loss_a;
620 } else {
621 linear = rtw89_db_to_linear(abs(ext_loss_a - ext_loss_b)) + 1;
622 linear /= 2;
623 ext_loss_avg = rtw89_linear_to_db(linear);
624 ext_loss_avg += min(ext_loss_a, ext_loss_b);
625 }
626
627 pwrofst = max(DIV_ROUND_CLOSEST(ext_loss_avg, 4) + 16, EDCCA_PWROFST_DEFAULT);
628
629 rtw89_phy_write32_mask(rtwdev, R_PWOFST, B_PWOFST, pwrofst);
630 }
631
rtw8852bx_set_gain_offset(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_phy_idx phy_idx)632 static void rtw8852bx_set_gain_offset(struct rtw89_dev *rtwdev,
633 enum rtw89_subband subband,
634 enum rtw89_phy_idx phy_idx)
635 {
636 static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD};
637 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1,
638 R_PATH1_G_TIA1_LNA6_OP1DB_V1};
639 struct rtw89_hal *hal = &rtwdev->hal;
640 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
641 enum rtw89_gain_offset gain_ofdm_band;
642 s8 ext_loss_a = 0, ext_loss_b = 0;
643 s32 offset_a, offset_b;
644 s32 offset_ofdm, offset_cck;
645 s32 tmp;
646 u8 path;
647
648 if (!efuse_gain->comp_valid)
649 goto next;
650
651 for (path = RF_PATH_A; path < BB_PATH_NUM_8852BX; path++) {
652 tmp = efuse_gain->comp[path][subband];
653 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
654 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
655 }
656
657 next:
658 if (!efuse_gain->offset_valid)
659 goto ext_loss;
660
661 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
662
663 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
664 offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
665
666 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
667 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
668 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
669
670 tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
671 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
672 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp);
673
674 if (hal->antenna_rx == RF_B) {
675 offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
676 offset_cck = -efuse_gain->offset[RF_PATH_B][0];
677 } else {
678 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
679 offset_cck = -efuse_gain->offset[RF_PATH_A][0];
680 }
681
682 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
683 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
684 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
685
686 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
687 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
688 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
689
690 if (subband == RTW89_CH_2G) {
691 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
692 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
693 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
694 B_RX_RPL_OFST_CCK_MASK, tmp);
695 }
696
697 ext_loss_a = (offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2);
698 ext_loss_b = (offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2);
699
700 ext_loss:
701 if (rtwdev->chip->chip_id == RTL8852BT)
702 rtw8852bt_ext_loss_avg_update(rtwdev, ext_loss_a, ext_loss_b);
703 }
704
705 static
rtw8852bx_set_rxsc_rpl_comp(struct rtw89_dev * rtwdev,enum rtw89_subband subband)706 void rtw8852bx_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
707 {
708 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
709 u8 band = rtw89_subband_to_bb_gain_band(subband);
710 u32 val;
711
712 val = u32_encode_bits((gain->rpl_ofst_20[band][RF_PATH_A] +
713 gain->rpl_ofst_20[band][RF_PATH_B]) >> 1, B_P0_RPL1_20_MASK) |
714 u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][0] +
715 gain->rpl_ofst_40[band][RF_PATH_B][0]) >> 1, B_P0_RPL1_40_MASK) |
716 u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][1] +
717 gain->rpl_ofst_40[band][RF_PATH_B][1]) >> 1, B_P0_RPL1_41_MASK);
718 val >>= B_P0_RPL1_SHIFT;
719 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
720 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
721
722 val = u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][2] +
723 gain->rpl_ofst_40[band][RF_PATH_B][2]) >> 1, B_P0_RTL2_42_MASK) |
724 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][0] +
725 gain->rpl_ofst_80[band][RF_PATH_B][0]) >> 1, B_P0_RTL2_80_MASK) |
726 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][1] +
727 gain->rpl_ofst_80[band][RF_PATH_B][1]) >> 1, B_P0_RTL2_81_MASK) |
728 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][10] +
729 gain->rpl_ofst_80[band][RF_PATH_B][10]) >> 1, B_P0_RTL2_8A_MASK);
730 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
731 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
732
733 val = u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][2] +
734 gain->rpl_ofst_80[band][RF_PATH_B][2]) >> 1, B_P0_RTL3_82_MASK) |
735 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][3] +
736 gain->rpl_ofst_80[band][RF_PATH_B][3]) >> 1, B_P0_RTL3_83_MASK) |
737 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][4] +
738 gain->rpl_ofst_80[band][RF_PATH_B][4]) >> 1, B_P0_RTL3_84_MASK) |
739 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][9] +
740 gain->rpl_ofst_80[band][RF_PATH_B][9]) >> 1, B_P0_RTL3_89_MASK);
741 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
742 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
743 }
744
rtw8852bx_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)745 static void rtw8852bx_ctrl_ch(struct rtw89_dev *rtwdev,
746 const struct rtw89_chan *chan,
747 enum rtw89_phy_idx phy_idx)
748 {
749 u8 central_ch = chan->channel;
750 u8 subband = chan->subband_type;
751 u8 sco_comp;
752 bool is_2g = central_ch <= 14;
753
754 /* Path A */
755 if (is_2g)
756 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
757 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
758 else
759 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
760 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
761
762 /* Path B */
763 if (is_2g)
764 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
765 B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx);
766 else
767 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
768 B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx);
769
770 /* SCO compensate FC setting */
771 sco_comp = rtw8852bx_sco_mapping(central_ch);
772 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
773
774 if (chan->band_type == RTW89_BAND_6G)
775 return;
776
777 /* CCK parameters */
778 if (central_ch == 14) {
779 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
780 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
781 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
782 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
783 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
784 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
785 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
786 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
787 } else {
788 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
789 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
790 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
791 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
792 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
793 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
794 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
795 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
796 }
797
798 rtw8852bx_set_gain_error(rtwdev, subband, RF_PATH_A);
799 rtw8852bx_set_gain_error(rtwdev, subband, RF_PATH_B);
800 rtw8852bx_set_gain_offset(rtwdev, subband, phy_idx);
801 rtw8852bx_set_rxsc_rpl_comp(rtwdev, subband);
802 }
803
rtw8852b_bw_setting(struct rtw89_dev * rtwdev,u8 bw,u8 path)804 static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
805 {
806 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
807 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
808
809 switch (bw) {
810 case RTW89_CHANNEL_WIDTH_5:
811 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
812 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
813 break;
814 case RTW89_CHANNEL_WIDTH_10:
815 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
816 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
817 break;
818 case RTW89_CHANNEL_WIDTH_20:
819 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
820 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
821 break;
822 case RTW89_CHANNEL_WIDTH_40:
823 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
824 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
825 break;
826 case RTW89_CHANNEL_WIDTH_80:
827 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
828 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
829 break;
830 default:
831 rtw89_warn(rtwdev, "Fail to set ADC\n");
832 }
833 }
834
835 static
rtw8852bt_adc_cfg(struct rtw89_dev * rtwdev,u8 bw,u8 path)836 void rtw8852bt_adc_cfg(struct rtw89_dev *rtwdev, u8 bw, u8 path)
837 {
838 static const u32 rck_reset_count[2] = {0xC0E8, 0xC1E8};
839 static const u32 adc_op5_bw_sel[2] = {0xC0D8, 0xC1D8};
840 static const u32 adc_sample_td[2] = {0xC0D4, 0xC1D4};
841 static const u32 adc_rst_cycle[2] = {0xC0EC, 0xC1EC};
842 static const u32 decim_filter[2] = {0xC0EC, 0xC1EC};
843 static const u32 rck_offset[2] = {0xC0C4, 0xC1C4};
844 static const u32 rx_adc_clk[2] = {0x12A0, 0x32A0};
845 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
846 static const u32 idac2_1[2] = {0xC0D4, 0xC1D4};
847 static const u32 idac2[2] = {0xC0D4, 0xC1D4};
848 static const u32 upd_clk_adc = {0x704};
849
850 if (rtwdev->chip->chip_id != RTL8852BT)
851 return;
852
853 rtw89_phy_write32_mask(rtwdev, idac2[path], B_P0_CFCH_CTL, 0x8);
854 rtw89_phy_write32_mask(rtwdev, rck_reset_count[path], B_ADCMOD_LP, 0x9);
855 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], B_WDADC_SEL, 0x2);
856 rtw89_phy_write32_mask(rtwdev, rx_adc_clk[path], B_P0_RXCK_ADJ, 0x49);
857 rtw89_phy_write32_mask(rtwdev, decim_filter[path], B_DCIM_FR, 0x0);
858
859 switch (bw) {
860 case RTW89_CHANNEL_WIDTH_5:
861 case RTW89_CHANNEL_WIDTH_10:
862 case RTW89_CHANNEL_WIDTH_20:
863 case RTW89_CHANNEL_WIDTH_40:
864 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2);
865 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x3);
866 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0xf);
867 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0);
868 /* Tx TSSI ADC update */
869 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 0);
870
871 if (rtwdev->efuse.rfe_type >= 51)
872 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x2);
873 else
874 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
875 break;
876 case RTW89_CHANNEL_WIDTH_80:
877 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2);
878 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2);
879 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x8);
880 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0);
881 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
882 /* Tx TSSI ADC update */
883 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 1);
884 break;
885 case RTW89_CHANNEL_WIDTH_160:
886 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x0);
887 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2);
888 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x4);
889 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x6);
890 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
891 /* Tx TSSI ADC update */
892 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 2);
893 break;
894 default:
895 rtw89_warn(rtwdev, "Fail to set ADC\n");
896 break;
897 }
898 }
899
rtw8852bx_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)900 static void rtw8852bx_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
901 enum rtw89_phy_idx phy_idx)
902 {
903 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
904 u32 rx_path_0;
905
906 rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, phy_idx);
907
908 switch (bw) {
909 case RTW89_CHANNEL_WIDTH_5:
910 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
911 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
912 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
913
914 /*Set RF mode at 3 */
915 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
916 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
917 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
918 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
919 if (chip_id == RTL8852BT) {
920 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
921 B_PATH0_BAND_NRBW_EN_V1, 0x0, phy_idx);
922 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
923 B_PATH1_BAND_NRBW_EN_V1, 0x0, phy_idx);
924 }
925 break;
926 case RTW89_CHANNEL_WIDTH_10:
927 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
928 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
929 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
930
931 /*Set RF mode at 3 */
932 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
933 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
934 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
935 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
936 if (chip_id == RTL8852BT) {
937 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
938 B_PATH0_BAND_NRBW_EN_V1, 0x0, phy_idx);
939 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
940 B_PATH1_BAND_NRBW_EN_V1, 0x0, phy_idx);
941 }
942 break;
943 case RTW89_CHANNEL_WIDTH_20:
944 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
945 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
946 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
947
948 /*Set RF mode at 3 */
949 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
950 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
951 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
952 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
953 if (chip_id == RTL8852BT) {
954 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
955 B_PATH0_BAND_NRBW_EN_V1, 0x1, phy_idx);
956 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
957 B_PATH1_BAND_NRBW_EN_V1, 0x1, phy_idx);
958 }
959 break;
960 case RTW89_CHANNEL_WIDTH_40:
961 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
962 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
963 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
964 pri_ch, phy_idx);
965
966 /*Set RF mode at 3 */
967 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
968 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
969 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
970 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
971 /*CCK primary channel */
972 if (pri_ch == RTW89_SC_20_UPPER)
973 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
974 else
975 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
976
977 break;
978 case RTW89_CHANNEL_WIDTH_80:
979 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
980 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
981 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
982 pri_ch, phy_idx);
983
984 /*Set RF mode at 3 */
985 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
986 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
987 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
988 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
989 break;
990 default:
991 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
992 pri_ch);
993 }
994
995 if (chip_id == RTL8852B) {
996 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A);
997 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B);
998 } else if (chip_id == RTL8852BT) {
999 rtw8852bt_adc_cfg(rtwdev, bw, RF_PATH_A);
1000 rtw8852bt_adc_cfg(rtwdev, bw, RF_PATH_B);
1001 }
1002
1003 if (rx_path_0 == 0x1)
1004 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
1005 B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
1006 else if (rx_path_0 == 0x2)
1007 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
1008 B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
1009 }
1010
rtw8852bx_ctrl_cck_en(struct rtw89_dev * rtwdev,bool cck_en)1011 static void rtw8852bx_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1012 {
1013 if (cck_en) {
1014 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1015 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1016 } else {
1017 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1018 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1019 }
1020 }
1021
rtw8852bx_5m_mask(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1022 static void rtw8852bx_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1023 enum rtw89_phy_idx phy_idx)
1024 {
1025 u8 pri_ch = chan->pri_ch_idx;
1026 bool mask_5m_low;
1027 bool mask_5m_en;
1028
1029 switch (chan->band_width) {
1030 case RTW89_CHANNEL_WIDTH_40:
1031 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
1032 mask_5m_en = true;
1033 mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1034 break;
1035 case RTW89_CHANNEL_WIDTH_80:
1036 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
1037 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1038 pri_ch == RTW89_SC_20_LOWEST;
1039 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1040 break;
1041 default:
1042 mask_5m_en = false;
1043 break;
1044 }
1045
1046 if (!mask_5m_en) {
1047 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1048 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0);
1049 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1050 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1051 return;
1052 }
1053
1054 if (mask_5m_low) {
1055 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
1056 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1057 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1058 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1059 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
1060 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
1061 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0);
1062 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1);
1063 } else {
1064 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
1065 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1066 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1067 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1068 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
1069 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
1070 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1);
1071 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0);
1072 }
1073 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1074 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1075 }
1076
__rtw8852bx_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1077 static void __rtw8852bx_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1078 {
1079 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1080 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1081 fsleep(1);
1082 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1083 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1084 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1085 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1086 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1087 }
1088
rtw8852bx_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1089 static void rtw8852bx_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1090 enum rtw89_phy_idx phy_idx)
1091 {
1092 u32 addr;
1093
1094 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1095 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1096 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1097 }
1098
__rtw8852bx_bb_sethw(struct rtw89_dev * rtwdev)1099 static void __rtw8852bx_bb_sethw(struct rtw89_dev *rtwdev)
1100 {
1101 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1102
1103 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1104 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1105
1106 rtw8852bx_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1107
1108 /* read these registers after loading BB parameters */
1109 gain->offset_base[RTW89_PHY_0] =
1110 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1111 gain->rssi_base[RTW89_PHY_0] =
1112 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1113 }
1114
rtw8852bx_bb_set_pop(struct rtw89_dev * rtwdev)1115 static void rtw8852bx_bb_set_pop(struct rtw89_dev *rtwdev)
1116 {
1117 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)
1118 rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN);
1119 }
1120
rtw8852bt_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1121 static u32 rtw8852bt_spur_freq(struct rtw89_dev *rtwdev,
1122 const struct rtw89_chan *chan)
1123 {
1124 u8 center_chan = chan->channel;
1125
1126 switch (chan->band_type) {
1127 case RTW89_BAND_5G:
1128 if (center_chan == 151 || center_chan == 153 ||
1129 center_chan == 155 || center_chan == 163)
1130 return 5760;
1131 break;
1132 default:
1133 break;
1134 }
1135
1136 return 0;
1137 }
1138
1139 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1140 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1141 #define MAX_TONE_NUM 2048
1142
rtw8852bt_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1143 static void rtw8852bt_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1144 const struct rtw89_chan *chan,
1145 enum rtw89_phy_idx phy_idx)
1146 {
1147 s32 freq_diff, csi_idx, csi_tone_idx;
1148 u32 spur_freq;
1149
1150 spur_freq = rtw8852bt_spur_freq(rtwdev, chan);
1151 if (spur_freq == 0) {
1152 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1153 0, phy_idx);
1154 return;
1155 }
1156
1157 freq_diff = (spur_freq - chan->freq) * 1000000;
1158 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1159 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1160
1161 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1162 csi_tone_idx, phy_idx);
1163 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1164 }
1165
1166 static
__rtw8852bx_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1167 void __rtw8852bx_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1168 enum rtw89_phy_idx phy_idx)
1169 {
1170 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1171 bool cck_en = chan->channel <= 14;
1172 u8 pri_ch_idx = chan->pri_ch_idx;
1173 u8 band = chan->band_type, chan_idx;
1174
1175 if (cck_en)
1176 rtw8852bx_ctrl_sco_cck(rtwdev, chan->primary_channel);
1177
1178 rtw8852bx_ctrl_ch(rtwdev, chan, phy_idx);
1179 rtw8852bx_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1180 rtw8852bx_ctrl_cck_en(rtwdev, cck_en);
1181 if (chip_id == RTL8852BT)
1182 rtw8852bt_set_csi_tone_idx(rtwdev, chan, phy_idx);
1183 if (chip_id == RTL8852B && chan->band_type == RTW89_BAND_5G) {
1184 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1185 B_PATH0_BT_SHARE_V1, 0x0);
1186 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1187 B_PATH0_BTG_PATH_V1, 0x0);
1188 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1189 B_PATH1_BT_SHARE_V1, 0x0);
1190 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1191 B_PATH1_BTG_PATH_V1, 0x0);
1192 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1193 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1194 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1195 B_BT_DYN_DC_EST_EN_MSK, 0x0);
1196 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1197 }
1198 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1199 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1200 rtw8852bx_5m_mask(rtwdev, chan, phy_idx);
1201 rtw8852bx_bb_set_pop(rtwdev);
1202 __rtw8852bx_bb_reset_all(rtwdev, phy_idx);
1203 }
1204
rtw8852bx_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref,u16 pwr_ofst_decrease)1205 static u32 rtw8852bx_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1206 enum rtw89_phy_idx phy_idx,
1207 s16 ref, u16 pwr_ofst_decrease)
1208 {
1209 const u16 tssi_16dbm_cw = 0x12c;
1210 const u8 base_cw_0db = 0x27;
1211 s16 pwr_s10_3;
1212 s16 rf_pwr_cw;
1213 u16 bb_pwr_cw;
1214 u32 pwr_cw;
1215 u32 tssi_ofst_cw;
1216
1217 pwr_s10_3 = (ref << 1) + (s16)(base_cw_0db << 3) - pwr_ofst_decrease;
1218 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
1219 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
1220 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1221 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1222
1223 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)) -
1224 pwr_ofst_decrease;
1225 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1226 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1227 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1228
1229 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
1230 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
1231 u32_encode_bits(ref, B_DPD_REF);
1232 }
1233
1234 /* @pwr_ofst (unit: 1/8 dBm): power of path A minus power of path B */
rtw8852bx_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 pwr_ofst)1235 static void rtw8852bx_set_txpwr_ref(struct rtw89_dev *rtwdev,
1236 enum rtw89_phy_idx phy_idx, s16 pwr_ofst)
1237 {
1238 static const u32 addr[RF_PATH_NUM_8852BX] = {0x5800, 0x7800};
1239 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
1240 u16 ofst_dec[RF_PATH_NUM_8852BX];
1241 const u8 ofst_ofdm = 0x4;
1242 const u8 ofst_cck = 0x8;
1243 const s16 ref_ofdm = 0;
1244 const s16 ref_cck = 0;
1245 u32 val;
1246 u8 i;
1247
1248 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1249
1250 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1251 B_AX_PWR_REF, 0x0);
1252
1253 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? 0 : abs(pwr_ofst);
1254 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ofst : 0;
1255
1256 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1257 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
1258 val = rtw8852bx_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm, ofst_dec[i]);
1259 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, phy_idx);
1260 }
1261
1262 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1263 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
1264 val = rtw8852bx_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck, ofst_dec[i]);
1265 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, phy_idx);
1266 }
1267 }
1268
rtw8852bx_bb_set_tx_shape_dfir(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 tx_shape_idx,enum rtw89_phy_idx phy_idx)1269 static void rtw8852bx_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1270 const struct rtw89_chan *chan,
1271 u8 tx_shape_idx,
1272 enum rtw89_phy_idx phy_idx)
1273 {
1274 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
1275 #define __DFIR_CFG_MASK 0xffffffff
1276 #define __DFIR_CFG_NR 8
1277 #define __DECL_DFIR_PARAM(_name, _val...) \
1278 static const u32 param_ ## _name[] = {_val}; \
1279 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
1280
1281 __DECL_DFIR_PARAM(flat,
1282 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1283 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1284 __DECL_DFIR_PARAM(sharp,
1285 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1286 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
1287 __DECL_DFIR_PARAM(sharp_14,
1288 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1289 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
1290 u8 ch = chan->channel;
1291 const u32 *param;
1292 u32 addr;
1293 int i;
1294
1295 if (ch > 14) {
1296 rtw89_warn(rtwdev,
1297 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
1298 return;
1299 }
1300
1301 if (ch == 14)
1302 param = param_sharp_14;
1303 else
1304 param = tx_shape_idx == 0 ? param_flat : param_sharp;
1305
1306 for (i = 0; i < __DFIR_CFG_NR; i++) {
1307 addr = __DFIR_CFG_ADDR(i);
1308 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1309 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
1310 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1311 phy_idx);
1312 }
1313
1314 #undef __DECL_DFIR_PARAM
1315 #undef __DFIR_CFG_NR
1316 #undef __DFIR_CFG_MASK
1317 #undef __DECL_CFG_ADDR
1318 }
1319
rtw8852bx_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1320 static void rtw8852bx_set_tx_shape(struct rtw89_dev *rtwdev,
1321 const struct rtw89_chan *chan,
1322 enum rtw89_phy_idx phy_idx)
1323 {
1324 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1325 u8 band = chan->band_type;
1326 u8 regd = rtw89_regd_get(rtwdev, band);
1327 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd];
1328 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd];
1329
1330 if (band == RTW89_BAND_2G)
1331 rtw8852bx_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1332
1333 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1334 tx_shape_ofdm);
1335 }
1336
rtw8852bx_get_txpwr_sar_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1337 static s16 rtw8852bx_get_txpwr_sar_diff(struct rtw89_dev *rtwdev,
1338 const struct rtw89_chan *chan)
1339 {
1340 struct rtw89_sar_parm sar_parm = {
1341 .center_freq = chan->freq,
1342 .force_path = true,
1343 };
1344 s16 sar_bb_a, sar_bb_b;
1345 s8 sar_mac;
1346
1347 sar_parm.path = RF_PATH_A;
1348 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
1349 sar_bb_a = rtw89_phy_txpwr_mac_to_bb(rtwdev, sar_mac);
1350
1351 sar_parm.path = RF_PATH_B;
1352 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
1353 sar_bb_b = rtw89_phy_txpwr_mac_to_bb(rtwdev, sar_mac);
1354
1355 return sar_bb_a - sar_bb_b;
1356 }
1357
rtw8852bx_set_txpwr_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1358 static void rtw8852bx_set_txpwr_diff(struct rtw89_dev *rtwdev,
1359 const struct rtw89_chan *chan,
1360 enum rtw89_phy_idx phy_idx)
1361 {
1362 s16 pwr_ofst;
1363
1364 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan);
1365 pwr_ofst += rtw8852bx_get_txpwr_sar_diff(rtwdev, chan);
1366 rtw8852bx_set_txpwr_ref(rtwdev, phy_idx, pwr_ofst);
1367 }
1368
__rtw8852bx_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1369 static void __rtw8852bx_set_txpwr(struct rtw89_dev *rtwdev,
1370 const struct rtw89_chan *chan,
1371 enum rtw89_phy_idx phy_idx)
1372 {
1373 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1374 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1375 rtw8852bx_set_tx_shape(rtwdev, chan, phy_idx);
1376 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1377 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1378 rtw8852bx_set_txpwr_diff(rtwdev, chan, phy_idx);
1379 }
1380
__rtw8852bx_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1381 static void __rtw8852bx_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1382 enum rtw89_phy_idx phy_idx)
1383 {
1384 rtw8852bx_set_txpwr_ref(rtwdev, phy_idx, 0);
1385 }
1386
1387 static
__rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1388 void __rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1389 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1390 {
1391 u32 reg;
1392
1393 if (pw_ofst < -16 || pw_ofst > 15) {
1394 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1395 return;
1396 }
1397
1398 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1399 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1400
1401 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1402 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1403
1404 pw_ofst = max_t(s8, pw_ofst - 3, -16);
1405 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1406 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1407 }
1408
1409 static int
__rtw8852bx_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1410 __rtw8852bx_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1411 {
1412 int ret;
1413
1414 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1415 if (ret)
1416 return ret;
1417
1418 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1419 if (ret)
1420 return ret;
1421
1422 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1423 if (ret)
1424 return ret;
1425
1426 rtw8852bx_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1427 RTW89_MAC_1 : RTW89_MAC_0);
1428
1429 return 0;
1430 }
1431
1432 static
__rtw8852bx_bb_set_plcp_tx(struct rtw89_dev * rtwdev)1433 void __rtw8852bx_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1434 {
1435 const struct rtw89_reg3_def *def = rtw8852bx_pmac_ht20_mcs7_tbl;
1436 u8 i;
1437
1438 for (i = 0; i < ARRAY_SIZE(rtw8852bx_pmac_ht20_mcs7_tbl); i++, def++)
1439 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
1440 }
1441
rtw8852bx_stop_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852bx_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1442 static void rtw8852bx_stop_pmac_tx(struct rtw89_dev *rtwdev,
1443 struct rtw8852bx_bb_pmac_info *tx_info,
1444 enum rtw89_phy_idx idx)
1445 {
1446 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1447 if (tx_info->mode == CONT_TX)
1448 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx);
1449 else if (tx_info->mode == PKTS_TX)
1450 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx);
1451 }
1452
rtw8852bx_start_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852bx_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1453 static void rtw8852bx_start_pmac_tx(struct rtw89_dev *rtwdev,
1454 struct rtw8852bx_bb_pmac_info *tx_info,
1455 enum rtw89_phy_idx idx)
1456 {
1457 enum rtw8852bx_pmac_mode mode = tx_info->mode;
1458 u32 pkt_cnt = tx_info->tx_cnt;
1459 u16 period = tx_info->period;
1460
1461 if (mode == CONT_TX && !tx_info->is_cck) {
1462 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx);
1463 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1464 } else if (mode == PKTS_TX) {
1465 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx);
1466 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1467 B_PMAC_TX_PRD_MSK, period, idx);
1468 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1469 pkt_cnt, idx);
1470 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1471 }
1472
1473 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1474 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1475 }
1476
1477 static
rtw8852bx_bb_set_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852bx_bb_pmac_info * tx_info,enum rtw89_phy_idx idx,const struct rtw89_chan * chan)1478 void rtw8852bx_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1479 struct rtw8852bx_bb_pmac_info *tx_info,
1480 enum rtw89_phy_idx idx, const struct rtw89_chan *chan)
1481 {
1482 if (!tx_info->en_pmac_tx) {
1483 rtw8852bx_stop_pmac_tx(rtwdev, tx_info, idx);
1484 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1485 if (chan->band_type == RTW89_BAND_2G)
1486 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1487 return;
1488 }
1489
1490 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1491
1492 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1493 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1494 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx);
1495 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1496 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1497 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1498 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1499
1500 rtw8852bx_start_pmac_tx(rtwdev, tx_info, idx);
1501 }
1502
1503 static
__rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev * rtwdev,u8 enable,u16 tx_cnt,u16 period,u16 tx_time,enum rtw89_phy_idx idx,const struct rtw89_chan * chan)1504 void __rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1505 u16 tx_cnt, u16 period, u16 tx_time,
1506 enum rtw89_phy_idx idx, const struct rtw89_chan *chan)
1507 {
1508 struct rtw8852bx_bb_pmac_info tx_info = {0};
1509
1510 tx_info.en_pmac_tx = enable;
1511 tx_info.is_cck = 0;
1512 tx_info.mode = PKTS_TX;
1513 tx_info.tx_cnt = tx_cnt;
1514 tx_info.period = period;
1515 tx_info.tx_time = tx_time;
1516
1517 rtw8852bx_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan);
1518 }
1519
1520 static
__rtw8852bx_bb_set_power(struct rtw89_dev * rtwdev,s16 pwr_dbm,enum rtw89_phy_idx idx)1521 void __rtw8852bx_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1522 enum rtw89_phy_idx idx)
1523 {
1524 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1525
1526 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1527 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1528 }
1529
1530 static
__rtw8852bx_bb_cfg_tx_path(struct rtw89_dev * rtwdev,u8 tx_path)1531 void __rtw8852bx_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1532 {
1533 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1534
1535 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1536
1537 if (tx_path == RF_PATH_A) {
1538 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1);
1539 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
1540 } else if (tx_path == RF_PATH_B) {
1541 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2);
1542 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
1543 } else if (tx_path == RF_PATH_AB) {
1544 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3);
1545 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4);
1546 } else {
1547 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1548 }
1549 }
1550
1551 static
__rtw8852bx_bb_tx_mode_switch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,u8 mode)1552 void __rtw8852bx_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1553 enum rtw89_phy_idx idx, u8 mode)
1554 {
1555 if (mode != 0)
1556 return;
1557
1558 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1559
1560 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1561 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1562 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1563 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1564 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1565 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1566 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1567 }
1568
1569 static
__rtw8852bx_bb_backup_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,struct rtw8852bx_bb_tssi_bak * bak)1570 void __rtw8852bx_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
1571 struct rtw8852bx_bb_tssi_bak *bak)
1572 {
1573 s32 tmp;
1574
1575 bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx);
1576 bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx);
1577 bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx);
1578 bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx);
1579 bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx);
1580 bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx);
1581 tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx);
1582 bak->tx_pwr = sign_extend32(tmp, 8);
1583 }
1584
1585 static
__rtw8852bx_bb_restore_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,const struct rtw8852bx_bb_tssi_bak * bak)1586 void __rtw8852bx_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
1587 const struct rtw8852bx_bb_tssi_bak *bak)
1588 {
1589 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx);
1590 if (bak->tx_path == RF_AB)
1591 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4);
1592 else
1593 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0);
1594 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx);
1595 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1596 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx);
1597 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx);
1598 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx);
1599 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx);
1600 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx);
1601 }
1602
__rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1603 static void __rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1604 enum rtw89_phy_idx phy_idx)
1605 {
1606 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852bx_btc_preagc_en_defs_tbl :
1607 &rtw8852bx_btc_preagc_dis_defs_tbl);
1608 }
1609
__rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1610 static void __rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1611 enum rtw89_phy_idx phy_idx)
1612 {
1613 if (en) {
1614 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1615 B_PATH0_BT_SHARE_V1, 0x1);
1616 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1617 B_PATH0_BTG_PATH_V1, 0x0);
1618 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
1619 B_PATH1_G_LNA6_OP1DB_V1, 0x20);
1620 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
1621 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
1622 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1623 B_PATH1_BT_SHARE_V1, 0x1);
1624 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1625 B_PATH1_BTG_PATH_V1, 0x1);
1626 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1627 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1628 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2);
1629 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1630 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1631 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1632 } else {
1633 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1634 B_PATH0_BT_SHARE_V1, 0x0);
1635 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1636 B_PATH0_BTG_PATH_V1, 0x0);
1637 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
1638 B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
1639 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
1640 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1641 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1642 B_PATH1_BT_SHARE_V1, 0x0);
1643 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1644 B_PATH1_BTG_PATH_V1, 0x0);
1645 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1646 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1647 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1648 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1649 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1650 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1651 }
1652 }
1653
1654 static
__rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path,const struct rtw89_chan * chan)1655 void __rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1656 enum rtw89_rf_path_bit rx_path,
1657 const struct rtw89_chan *chan)
1658 {
1659 u32 rst_mask0;
1660 u32 rst_mask1;
1661
1662 if (rx_path == RF_A) {
1663 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1664 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1665 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1666 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1667 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1668 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1669 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1670 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1671 } else if (rx_path == RF_B) {
1672 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2);
1673 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2);
1674 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2);
1675 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1676 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1677 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1678 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1679 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1680 } else if (rx_path == RF_AB) {
1681 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3);
1682 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3);
1683 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3);
1684 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
1685 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
1686 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1687 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
1688 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
1689 }
1690
1691 rtw8852bx_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1692
1693 if (chan->band_type == RTW89_BAND_2G &&
1694 (rx_path == RF_B || rx_path == RF_AB))
1695 rtw8852bx_ctrl_btg_bt_rx(rtwdev, true, RTW89_PHY_0);
1696 else
1697 rtw8852bx_ctrl_btg_bt_rx(rtwdev, false, RTW89_PHY_0);
1698
1699 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1700 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
1701 if (rx_path == RF_A) {
1702 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1703 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1704 } else {
1705 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1706 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1707 }
1708 }
1709
rtw8852bx_bb_ctrl_rf_mode_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path)1710 static void rtw8852bx_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev,
1711 enum rtw89_rf_path_bit rx_path)
1712 {
1713 if (rx_path == RF_A) {
1714 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
1715 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
1716 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
1717 B_P0_RFMODE_FTM_RX, 0x333);
1718 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
1719 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
1720 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
1721 B_P1_RFMODE_FTM_RX, 0x111);
1722 } else if (rx_path == RF_B) {
1723 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
1724 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
1725 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
1726 B_P0_RFMODE_FTM_RX, 0x111);
1727 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
1728 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
1729 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
1730 B_P1_RFMODE_FTM_RX, 0x333);
1731 } else if (rx_path == RF_AB) {
1732 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
1733 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
1734 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
1735 B_P0_RFMODE_FTM_RX, 0x333);
1736 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
1737 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
1738 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
1739 B_P1_RFMODE_FTM_RX, 0x333);
1740 }
1741 }
1742
__rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)1743 static void __rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1744 {
1745 struct rtw89_hal *hal = &rtwdev->hal;
1746 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1747 enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB;
1748 u8 rx_nss = rtwdev->hal.rx_nss;
1749
1750 if (rx_path != RF_AB)
1751 rx_nss = 1;
1752
1753 rtw8852bx_bb_ctrl_rx_path(rtwdev, rx_path, chan);
1754 rtw8852bx_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path);
1755
1756 if (rx_nss == 1) {
1757 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1758 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1759 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1760 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1761 } else {
1762 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
1763 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
1764 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
1765 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
1766 }
1767
1768 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1769 }
1770
__rtw8852bx_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1771 static u8 __rtw8852bx_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1772 {
1773 if (rtwdev->is_tssi_mode[rf_path]) {
1774 u32 addr = 0x1c10 + (rf_path << 13);
1775
1776 return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1777 }
1778
1779 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1780 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1781 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1782
1783 fsleep(200);
1784
1785 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1786 }
1787
1788 static
rtw8852bx_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)1789 void rtw8852bx_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1790 {
1791 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
1792 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
1793 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
1794 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
1795 }
1796
__rtw8852bx_btc_init_cfg(struct rtw89_dev * rtwdev)1797 static void __rtw8852bx_btc_init_cfg(struct rtw89_dev *rtwdev)
1798 {
1799 struct rtw89_btc *btc = &rtwdev->btc;
1800 const struct rtw89_chip_info *chip = rtwdev->chip;
1801 const struct rtw89_mac_ax_coex coex_params = {
1802 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1803 .direction = RTW89_MAC_AX_COEX_INNER,
1804 };
1805
1806 /* PTA init */
1807 rtw89_mac_coex_init(rtwdev, &coex_params);
1808
1809 /* set WL Tx response = Hi-Pri */
1810 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1811 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1812
1813 /* set rf gnt debug off */
1814 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
1815 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
1816
1817 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
1818 if (btc->ant_type == BTC_ANT_SHARED) {
1819 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
1820 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
1821 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
1822 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
1823 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f);
1824 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
1825 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
1826 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
1827 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
1828 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff);
1829 }
1830
1831 if (rtwdev->chip->chip_id == RTL8852BT) {
1832 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_RX_GROUP, 0x5df);
1833 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_RX_GROUP, 0x5df);
1834 }
1835
1836 /* set PTA break table */
1837 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1838
1839 /* enable BT counter 0xda40[16,2] = 2b'11 */
1840 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
1841 btc->cx.wl.status.map.init_ok = true;
1842 }
1843
1844 static
__rtw8852bx_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)1845 void __rtw8852bx_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1846 {
1847 u32 bitmap;
1848 u32 reg;
1849
1850 switch (map) {
1851 case BTC_PRI_MASK_TX_RESP:
1852 reg = R_BTC_BT_COEX_MSK_TABLE;
1853 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
1854 break;
1855 case BTC_PRI_MASK_BEACON:
1856 reg = R_AX_WL_PRI_MSK;
1857 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
1858 break;
1859 case BTC_PRI_MASK_RX_CCK:
1860 reg = R_BTC_BT_COEX_MSK_TABLE;
1861 bitmap = B_BTC_PRI_MASK_RXCCK_V1;
1862 break;
1863 default:
1864 return;
1865 }
1866
1867 if (state)
1868 rtw89_write32_set(rtwdev, reg, bitmap);
1869 else
1870 rtw89_write32_clr(rtwdev, reg, bitmap);
1871 }
1872
1873 static
__rtw8852bx_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)1874 s8 __rtw8852bx_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1875 {
1876 /* +6 for compensate offset */
1877 return clamp_t(s8, val + 6, -100, 0) + 100;
1878 }
1879
1880 static
__rtw8852bx_btc_update_bt_cnt(struct rtw89_dev * rtwdev)1881 void __rtw8852bx_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1882 {
1883 /* Feature move to firmware */
1884 }
1885
__rtw8852bx_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)1886 static void __rtw8852bx_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1887 {
1888 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
1889 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1890 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31);
1891
1892 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
1893 if (state)
1894 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x179);
1895 else
1896 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20);
1897
1898 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1899 }
1900
rtw8852bx_btc_set_wl_lna2(struct rtw89_dev * rtwdev,u8 level)1901 static void rtw8852bx_btc_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
1902 {
1903 switch (level) {
1904 case 0: /* default */
1905 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1906 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
1907 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1908 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1909 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
1910 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1911 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1912 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1913 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
1914 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1915 break;
1916 case 1: /* Fix LNA2=5 */
1917 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1918 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
1919 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1920 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1921 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
1922 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1923 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1924 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1925 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
1926 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1927 break;
1928 }
1929 }
1930
__rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)1931 static void __rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
1932 {
1933 struct rtw89_btc *btc = &rtwdev->btc;
1934
1935 switch (level) {
1936 case 0: /* original */
1937 default:
1938 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
1939 btc->dm.wl_lna2 = 0;
1940 break;
1941 case 1: /* for FDD free-run */
1942 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0);
1943 btc->dm.wl_lna2 = 0;
1944 break;
1945 case 2: /* for BTG Co-Rx*/
1946 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
1947 btc->dm.wl_lna2 = 1;
1948 break;
1949 }
1950
1951 rtw8852bx_btc_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
1952 }
1953
rtw8852bx_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)1954 static void rtw8852bx_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
1955 struct rtw89_rx_phy_ppdu *phy_ppdu,
1956 struct ieee80211_rx_status *status)
1957 {
1958 u16 chan = phy_ppdu->chan_idx;
1959 enum nl80211_band band;
1960 u8 ch;
1961
1962 if (chan == 0)
1963 return;
1964
1965 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
1966 status->freq = ieee80211_channel_to_frequency(ch, band);
1967 status->band = band;
1968 }
1969
__rtw8852bx_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)1970 static void __rtw8852bx_query_ppdu(struct rtw89_dev *rtwdev,
1971 struct rtw89_rx_phy_ppdu *phy_ppdu,
1972 struct ieee80211_rx_status *status)
1973 {
1974 u8 path;
1975 u8 *rx_power = phy_ppdu->rssi;
1976
1977 if (!status->signal)
1978 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A],
1979 rx_power[RF_PATH_B]));
1980 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
1981 status->chains |= BIT(path);
1982 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
1983 }
1984 if (phy_ppdu->valid)
1985 rtw8852bx_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
1986 }
1987
__rtw8852bx_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1988 static void __rtw8852bx_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
1989 struct rtw89_rx_phy_ppdu *phy_ppdu)
1990 {
1991 u8 delta = phy_ppdu->rpl_avg - phy_ppdu->rssi_avg;
1992 u8 *rssi = phy_ppdu->rssi;
1993 u8 i;
1994
1995 for (i = 0; i < RF_PATH_NUM_8852BX; i++)
1996 rssi[i] += delta;
1997
1998 phy_ppdu->rssi_avg = phy_ppdu->rpl_avg;
1999 }
2000
__rtw8852bx_mac_enable_bb_rf(struct rtw89_dev * rtwdev)2001 static int __rtw8852bx_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2002 {
2003 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2004 u32 val32;
2005 int ret;
2006
2007 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2008 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2009 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1);
2010 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2011 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2012 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2013
2014 if (chip_id == RTL8852BT) {
2015 val32 = rtw89_read32(rtwdev, R_AX_AFE_OFF_CTRL1);
2016 val32 = u32_replace_bits(val32, 0x1, B_AX_S0_LDO_VSEL_F_MASK);
2017 val32 = u32_replace_bits(val32, 0x1, B_AX_S1_LDO_VSEL_F_MASK);
2018 rtw89_write32(rtwdev, R_AX_AFE_OFF_CTRL1, val32);
2019 }
2020
2021 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2022 FULL_BIT_MASK);
2023 if (ret)
2024 return ret;
2025
2026 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2027 FULL_BIT_MASK);
2028 if (ret)
2029 return ret;
2030
2031 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2032
2033 return 0;
2034 }
2035
__rtw8852bx_mac_disable_bb_rf(struct rtw89_dev * rtwdev)2036 static int __rtw8852bx_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2037 {
2038 u8 wl_rfc_s0;
2039 u8 wl_rfc_s1;
2040 int ret;
2041
2042 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2043 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2044 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2045
2046 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2047 if (ret)
2048 return ret;
2049 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
2050 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2051 FULL_BIT_MASK);
2052 if (ret)
2053 return ret;
2054
2055 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2056 if (ret)
2057 return ret;
2058 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
2059 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
2060 FULL_BIT_MASK);
2061 return ret;
2062 }
2063
2064 const struct rtw8852bx_info rtw8852bx_info = {
2065 .mac_enable_bb_rf = __rtw8852bx_mac_enable_bb_rf,
2066 .mac_disable_bb_rf = __rtw8852bx_mac_disable_bb_rf,
2067 .bb_sethw = __rtw8852bx_bb_sethw,
2068 .bb_reset_all = __rtw8852bx_bb_reset_all,
2069 .bb_cfg_txrx_path = __rtw8852bx_bb_cfg_txrx_path,
2070 .bb_cfg_tx_path = __rtw8852bx_bb_cfg_tx_path,
2071 .bb_ctrl_rx_path = __rtw8852bx_bb_ctrl_rx_path,
2072 .bb_set_plcp_tx = __rtw8852bx_bb_set_plcp_tx,
2073 .bb_set_power = __rtw8852bx_bb_set_power,
2074 .bb_set_pmac_pkt_tx = __rtw8852bx_bb_set_pmac_pkt_tx,
2075 .bb_backup_tssi = __rtw8852bx_bb_backup_tssi,
2076 .bb_restore_tssi = __rtw8852bx_bb_restore_tssi,
2077 .bb_tx_mode_switch = __rtw8852bx_bb_tx_mode_switch,
2078 .set_channel_mac = __rtw8852bx_set_channel_mac,
2079 .set_channel_bb = __rtw8852bx_set_channel_bb,
2080 .ctrl_nbtg_bt_tx = __rtw8852bx_ctrl_nbtg_bt_tx,
2081 .ctrl_btg_bt_rx = __rtw8852bx_ctrl_btg_bt_rx,
2082 .query_ppdu = __rtw8852bx_query_ppdu,
2083 .convert_rpl_to_rssi = __rtw8852bx_convert_rpl_to_rssi,
2084 .read_efuse = __rtw8852bx_read_efuse,
2085 .read_phycap = __rtw8852bx_read_phycap,
2086 .power_trim = __rtw8852bx_power_trim,
2087 .set_txpwr = __rtw8852bx_set_txpwr,
2088 .set_txpwr_ctrl = __rtw8852bx_set_txpwr_ctrl,
2089 .init_txpwr_unit = __rtw8852bx_init_txpwr_unit,
2090 .set_txpwr_ul_tb_offset = __rtw8852bx_set_txpwr_ul_tb_offset,
2091 .get_thermal = __rtw8852bx_get_thermal,
2092 .adc_cfg = rtw8852bt_adc_cfg,
2093 .btc_init_cfg = __rtw8852bx_btc_init_cfg,
2094 .btc_set_wl_pri = __rtw8852bx_btc_set_wl_pri,
2095 .btc_get_bt_rssi = __rtw8852bx_btc_get_bt_rssi,
2096 .btc_update_bt_cnt = __rtw8852bx_btc_update_bt_cnt,
2097 .btc_wl_s1_standby = __rtw8852bx_btc_wl_s1_standby,
2098 .btc_set_wl_rx_gain = __rtw8852bx_btc_set_wl_rx_gain,
2099 };
2100 EXPORT_SYMBOL(rtw8852bx_info);
2101
2102 MODULE_AUTHOR("Realtek Corporation");
2103 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B common routines");
2104 MODULE_LICENSE("Dual BSD/GPL");
2105