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Searched refs:RREG32_PLL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c45 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_engine_clock()
51 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; in radeon_legacy_get_engine_clock()
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
75 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_memory_clock()
81 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; in radeon_legacy_get_memory_clock()
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
122 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_read_clocks_OF()
152 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & in radeon_read_clocks_OF()
200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info()
216 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & in radeon_get_clock_info()
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H A Drs600.c259 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); in rs600_pm_misc()
276 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); in rs600_pm_misc()
288 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); in rs600_pm_misc()
296 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); in rs600_pm_misc()
303 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); in rs600_pm_misc()
H A Dradeon_combios.c1131 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); in radeon_legacy_get_lvds_info_from_regs()
1136 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_legacy_get_lvds_info_from_regs()
2971 val = RREG32_PLL(reg); in radeon_combios_external_tmds_setup()
3050 (RREG32_PLL in combios_parse_mmio_table()
3100 tmp = RREG32_PLL(addr); in combios_parse_pll_table()
3118 (RREG32_PLL in combios_parse_pll_table()
3126 if (RREG32_PLL in combios_parse_pll_table()
3134 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); in combios_parse_pll_table()
3138 RREG32_PLL in combios_parse_pll_table()
H A Drv515.c480 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); in rv515_clock_startup()
482 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); in rv515_clock_startup()
484 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); in rv515_clock_startup()
H A Dr420.c200 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); in r420_clock_resume()
H A Dradeon_legacy_encoders.c120 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_lvds_update()
653 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_primary_dac_detect()
1576 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_tv_dac_detect()
H A Dr100.c391 sclk_cntl = RREG32_PLL(SCLK_CNTL); in r100_pm_misc()
392 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); in r100_pm_misc()
394 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); in r100_pm_misc()
2719 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); in r100_set_common_regs()
3893 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); in r100_clock_startup()
H A Dradeon_legacy_tv.c285 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
H A Dr300.c1364 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); in r300_clock_startup()
H A Dradeon.h2513 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) macro
2546 uint32_t tmp_ = RREG32_PLL(reg); \
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu.h1408 uint32_t tmp_ = RREG32_PLL(reg); \