xref: /linux/drivers/clk/clk-rp1.c (revision 0f46f50845ce75bfaba62df0421084d23bb6a72f)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2023 Raspberry Pi Ltd.
4  *
5  * Clock driver for RP1 PCIe multifunction chip.
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/clk-provider.h>
10 #include <linux/regmap.h>
11 #include <linux/math64.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/units.h>
15 
16 #include <dt-bindings/clock/raspberrypi,rp1-clocks.h>
17 
18 #define PLL_SYS_OFFSET			0x08000
19 #define PLL_SYS_CS			(PLL_SYS_OFFSET + 0x00)
20 #define PLL_SYS_PWR			(PLL_SYS_OFFSET + 0x04)
21 #define PLL_SYS_FBDIV_INT		(PLL_SYS_OFFSET + 0x08)
22 #define PLL_SYS_FBDIV_FRAC		(PLL_SYS_OFFSET + 0x0c)
23 #define PLL_SYS_PRIM			(PLL_SYS_OFFSET + 0x10)
24 #define PLL_SYS_SEC			(PLL_SYS_OFFSET + 0x14)
25 
26 #define PLL_AUDIO_OFFSET		0x0c000
27 #define PLL_AUDIO_CS			(PLL_AUDIO_OFFSET + 0x00)
28 #define PLL_AUDIO_PWR			(PLL_AUDIO_OFFSET + 0x04)
29 #define PLL_AUDIO_FBDIV_INT		(PLL_AUDIO_OFFSET + 0x08)
30 #define PLL_AUDIO_FBDIV_FRAC		(PLL_AUDIO_OFFSET + 0x0c)
31 #define PLL_AUDIO_PRIM			(PLL_AUDIO_OFFSET + 0x10)
32 #define PLL_AUDIO_SEC			(PLL_AUDIO_OFFSET + 0x14)
33 #define PLL_AUDIO_TERN			(PLL_AUDIO_OFFSET + 0x18)
34 
35 #define PLL_VIDEO_OFFSET		0x10000
36 #define PLL_VIDEO_CS			(PLL_VIDEO_OFFSET + 0x00)
37 #define PLL_VIDEO_PWR			(PLL_VIDEO_OFFSET + 0x04)
38 #define PLL_VIDEO_FBDIV_INT		(PLL_VIDEO_OFFSET + 0x08)
39 #define PLL_VIDEO_FBDIV_FRAC		(PLL_VIDEO_OFFSET + 0x0c)
40 #define PLL_VIDEO_PRIM			(PLL_VIDEO_OFFSET + 0x10)
41 #define PLL_VIDEO_SEC			(PLL_VIDEO_OFFSET + 0x14)
42 
43 #define GPCLK_OE_CTRL			0x00000
44 
45 #define CLK_SYS_OFFSET			0x00014
46 #define CLK_SYS_CTRL			(CLK_SYS_OFFSET + 0x00)
47 #define CLK_SYS_DIV_INT			(CLK_SYS_OFFSET + 0x04)
48 #define CLK_SYS_SEL			(CLK_SYS_OFFSET + 0x0c)
49 
50 #define CLK_SLOW_OFFSET			0x00024
51 #define CLK_SLOW_SYS_CTRL		(CLK_SLOW_OFFSET + 0x00)
52 #define CLK_SLOW_SYS_DIV_INT		(CLK_SLOW_OFFSET + 0x04)
53 #define CLK_SLOW_SYS_SEL		(CLK_SLOW_OFFSET + 0x0c)
54 
55 #define CLK_DMA_OFFSET			0x00044
56 #define CLK_DMA_CTRL			(CLK_DMA_OFFSET + 0x00)
57 #define CLK_DMA_DIV_INT			(CLK_DMA_OFFSET + 0x04)
58 #define CLK_DMA_SEL			(CLK_DMA_OFFSET + 0x0c)
59 
60 #define CLK_UART_OFFSET			0x00054
61 #define CLK_UART_CTRL			(CLK_UART_OFFSET + 0x00)
62 #define CLK_UART_DIV_INT		(CLK_UART_OFFSET + 0x04)
63 #define CLK_UART_SEL			(CLK_UART_OFFSET + 0x0c)
64 
65 #define CLK_ETH_OFFSET			0x00064
66 #define CLK_ETH_CTRL			(CLK_ETH_OFFSET + 0x00)
67 #define CLK_ETH_DIV_INT			(CLK_ETH_OFFSET + 0x04)
68 #define CLK_ETH_SEL			(CLK_ETH_OFFSET + 0x0c)
69 
70 #define CLK_PWM0_OFFSET			0x00074
71 #define CLK_PWM0_CTRL			(CLK_PWM0_OFFSET + 0x00)
72 #define CLK_PWM0_DIV_INT		(CLK_PWM0_OFFSET + 0x04)
73 #define CLK_PWM0_DIV_FRAC		(CLK_PWM0_OFFSET + 0x08)
74 #define CLK_PWM0_SEL			(CLK_PWM0_OFFSET + 0x0c)
75 
76 #define CLK_PWM1_OFFSET			0x00084
77 #define CLK_PWM1_CTRL			(CLK_PWM1_OFFSET + 0x00)
78 #define CLK_PWM1_DIV_INT		(CLK_PWM1_OFFSET + 0x04)
79 #define CLK_PWM1_DIV_FRAC		(CLK_PWM1_OFFSET + 0x08)
80 #define CLK_PWM1_SEL			(CLK_PWM1_OFFSET + 0x0c)
81 
82 #define CLK_AUDIO_IN_OFFSET		0x00094
83 #define CLK_AUDIO_IN_CTRL		(CLK_AUDIO_IN_OFFSET + 0x00)
84 #define CLK_AUDIO_IN_DIV_INT		(CLK_AUDIO_IN_OFFSET + 0x04)
85 #define CLK_AUDIO_IN_SEL		(CLK_AUDIO_IN_OFFSET + 0x0c)
86 
87 #define CLK_AUDIO_OUT_OFFSET		0x000a4
88 #define CLK_AUDIO_OUT_CTRL		(CLK_AUDIO_OUT_OFFSET + 0x00)
89 #define CLK_AUDIO_OUT_DIV_INT		(CLK_AUDIO_OUT_OFFSET + 0x04)
90 #define CLK_AUDIO_OUT_SEL		(CLK_AUDIO_OUT_OFFSET + 0x0c)
91 
92 #define CLK_I2S_OFFSET			0x000b4
93 #define CLK_I2S_CTRL			(CLK_I2S_OFFSET + 0x00)
94 #define CLK_I2S_DIV_INT			(CLK_I2S_OFFSET + 0x04)
95 #define CLK_I2S_SEL			(CLK_I2S_OFFSET + 0x0c)
96 
97 #define CLK_MIPI0_CFG_OFFSET		0x000c4
98 #define CLK_MIPI0_CFG_CTRL		(CLK_MIPI0_CFG_OFFSET + 0x00)
99 #define CLK_MIPI0_CFG_DIV_INT		(CLK_MIPI0_CFG_OFFSET + 0x04)
100 #define CLK_MIPI0_CFG_SEL		(CLK_MIPI0_CFG_OFFSET + 0x0c)
101 
102 #define CLK_MIPI1_CFG_OFFSET		0x000d4
103 #define CLK_MIPI1_CFG_CTRL		(CLK_MIPI1_CFG_OFFSET + 0x00)
104 #define CLK_MIPI1_CFG_DIV_INT		(CLK_MIPI1_CFG_OFFSET + 0x04)
105 #define CLK_MIPI1_CFG_SEL		(CLK_MIPI1_CFG_OFFSET + 0x0c)
106 
107 #define CLK_PCIE_AUX_OFFSET		0x000e4
108 #define CLK_PCIE_AUX_CTRL		(CLK_PCIE_AUX_OFFSET + 0x00)
109 #define CLK_PCIE_AUX_DIV_INT		(CLK_PCIE_AUX_OFFSET + 0x04)
110 #define CLK_PCIE_AUX_SEL		(CLK_PCIE_AUX_OFFSET + 0x0c)
111 
112 #define CLK_USBH0_MICROFRAME_OFFSET	0x000f4
113 #define CLK_USBH0_MICROFRAME_CTRL	(CLK_USBH0_MICROFRAME_OFFSET + 0x00)
114 #define CLK_USBH0_MICROFRAME_DIV_INT	(CLK_USBH0_MICROFRAME_OFFSET + 0x04)
115 #define CLK_USBH0_MICROFRAME_SEL	(CLK_USBH0_MICROFRAME_OFFSET + 0x0c)
116 
117 #define CLK_USBH1_MICROFRAME_OFFSET	0x00104
118 #define CLK_USBH1_MICROFRAME_CTRL	(CLK_USBH1_MICROFRAME_OFFSET + 0x00)
119 #define CLK_USBH1_MICROFRAME_DIV_INT	(CLK_USBH1_MICROFRAME_OFFSET + 0x04)
120 #define CLK_USBH1_MICROFRAME_SEL	(CLK_USBH1_MICROFRAME_OFFSET + 0x0c)
121 
122 #define CLK_USBH0_SUSPEND_OFFSET	0x00114
123 #define CLK_USBH0_SUSPEND_CTRL		(CLK_USBH0_SUSPEND_OFFSET + 0x00)
124 #define CLK_USBH0_SUSPEND_DIV_INT	(CLK_USBH0_SUSPEND_OFFSET + 0x04)
125 #define CLK_USBH0_SUSPEND_SEL		(CLK_USBH0_SUSPEND_OFFSET + 0x0c)
126 
127 #define CLK_USBH1_SUSPEND_OFFSET	0x00124
128 #define CLK_USBH1_SUSPEND_CTRL		(CLK_USBH1_SUSPEND_OFFSET + 0x00)
129 #define CLK_USBH1_SUSPEND_DIV_INT	(CLK_USBH1_SUSPEND_OFFSET + 0x04)
130 #define CLK_USBH1_SUSPEND_SEL		(CLK_USBH1_SUSPEND_OFFSET + 0x0c)
131 
132 #define CLK_ETH_TSU_OFFSET		0x00134
133 #define CLK_ETH_TSU_CTRL		(CLK_ETH_TSU_OFFSET + 0x00)
134 #define CLK_ETH_TSU_DIV_INT		(CLK_ETH_TSU_OFFSET + 0x04)
135 #define CLK_ETH_TSU_SEL			(CLK_ETH_TSU_OFFSET + 0x0c)
136 
137 #define CLK_ADC_OFFSET			0x00144
138 #define CLK_ADC_CTRL			(CLK_ADC_OFFSET + 0x00)
139 #define CLK_ADC_DIV_INT			(CLK_ADC_OFFSET + 0x04)
140 #define CLK_ADC_SEL			(CLK_ADC_OFFSET + 0x0c)
141 
142 #define CLK_SDIO_TIMER_OFFSET		0x00154
143 #define CLK_SDIO_TIMER_CTRL		(CLK_SDIO_TIMER_OFFSET + 0x00)
144 #define CLK_SDIO_TIMER_DIV_INT		(CLK_SDIO_TIMER_OFFSET + 0x04)
145 #define CLK_SDIO_TIMER_SEL		(CLK_SDIO_TIMER_OFFSET + 0x0c)
146 
147 #define CLK_SDIO_ALT_SRC_OFFSET		0x00164
148 #define CLK_SDIO_ALT_SRC_CTRL		(CLK_SDIO_ALT_SRC_OFFSET + 0x00)
149 #define CLK_SDIO_ALT_SRC_DIV_INT	(CLK_SDIO_ALT_SRC_OFFSET + 0x04)
150 #define CLK_SDIO_ALT_SRC_SEL		(CLK_SDIO_ALT_SRC_OFFSET + 0x0c)
151 
152 #define CLK_GP0_OFFSET			0x00174
153 #define CLK_GP0_CTRL			(CLK_GP0_OFFSET + 0x00)
154 #define CLK_GP0_DIV_INT			(CLK_GP0_OFFSET + 0x04)
155 #define CLK_GP0_DIV_FRAC		(CLK_GP0_OFFSET + 0x08)
156 #define CLK_GP0_SEL			(CLK_GP0_OFFSET + 0x0c)
157 
158 #define CLK_GP1_OFFSET			0x00184
159 #define CLK_GP1_CTRL			(CLK_GP1_OFFSET + 0x00)
160 #define CLK_GP1_DIV_INT			(CLK_GP1_OFFSET + 0x04)
161 #define CLK_GP1_DIV_FRAC		(CLK_GP1_OFFSET + 0x08)
162 #define CLK_GP1_SEL			(CLK_GP1_OFFSET + 0x0c)
163 
164 #define CLK_GP2_OFFSET			0x00194
165 #define CLK_GP2_CTRL			(CLK_GP2_OFFSET + 0x00)
166 #define CLK_GP2_DIV_INT			(CLK_GP2_OFFSET + 0x04)
167 #define CLK_GP2_DIV_FRAC		(CLK_GP2_OFFSET + 0x08)
168 #define CLK_GP2_SEL			(CLK_GP2_OFFSET + 0x0c)
169 
170 #define CLK_GP3_OFFSET			0x001a4
171 #define CLK_GP3_CTRL			(CLK_GP3_OFFSET + 0x00)
172 #define CLK_GP3_DIV_INT			(CLK_GP3_OFFSET + 0x04)
173 #define CLK_GP3_DIV_FRAC		(CLK_GP3_OFFSET + 0x08)
174 #define CLK_GP3_SEL			(CLK_GP3_OFFSET + 0x0c)
175 
176 #define CLK_GP4_OFFSET			0x001b4
177 #define CLK_GP4_CTRL			(CLK_GP4_OFFSET + 0x00)
178 #define CLK_GP4_DIV_INT			(CLK_GP4_OFFSET + 0x04)
179 #define CLK_GP4_DIV_FRAC		(CLK_GP4_OFFSET + 0x08)
180 #define CLK_GP4_SEL			(CLK_GP4_OFFSET + 0x0c)
181 
182 #define CLK_GP5_OFFSET			0x001c4
183 #define CLK_GP5_CTRL			(CLK_GP5_OFFSET + 0x00)
184 #define CLK_GP5_DIV_INT			(CLK_GP5_OFFSET + 0x04)
185 #define CLK_GP5_DIV_FRAC		(CLK_GP5_OFFSET + 0x08)
186 #define CLK_GP5_SEL			(CLK_GP5_OFFSET + 0x0c)
187 
188 #define CLK_SYS_RESUS_CTRL		0x0020c
189 
190 #define CLK_SLOW_SYS_RESUS_CTRL		0x00214
191 
192 #define FC0_OFFSET			0x0021c
193 #define FC0_REF_KHZ			(FC0_OFFSET + 0x00)
194 #define FC0_MIN_KHZ			(FC0_OFFSET + 0x04)
195 #define FC0_MAX_KHZ			(FC0_OFFSET + 0x08)
196 #define FC0_DELAY			(FC0_OFFSET + 0x0c)
197 #define FC0_INTERVAL			(FC0_OFFSET + 0x10)
198 #define FC0_SRC				(FC0_OFFSET + 0x14)
199 #define FC0_STATUS			(FC0_OFFSET + 0x18)
200 #define FC0_RESULT			(FC0_OFFSET + 0x1c)
201 #define FC_SIZE				0x20
202 #define FC_COUNT			8
203 #define FC_NUM(idx, off)		((idx) * 32 + (off))
204 
205 #define AUX_SEL				1
206 
207 #define VIDEO_CLOCKS_OFFSET		0x4000
208 #define VIDEO_CLK_VEC_CTRL		(VIDEO_CLOCKS_OFFSET + 0x0000)
209 #define VIDEO_CLK_VEC_DIV_INT		(VIDEO_CLOCKS_OFFSET + 0x0004)
210 #define VIDEO_CLK_VEC_SEL		(VIDEO_CLOCKS_OFFSET + 0x000c)
211 #define VIDEO_CLK_DPI_CTRL		(VIDEO_CLOCKS_OFFSET + 0x0010)
212 #define VIDEO_CLK_DPI_DIV_INT		(VIDEO_CLOCKS_OFFSET + 0x0014)
213 #define VIDEO_CLK_DPI_SEL		(VIDEO_CLOCKS_OFFSET + 0x001c)
214 #define VIDEO_CLK_MIPI0_DPI_CTRL	(VIDEO_CLOCKS_OFFSET + 0x0020)
215 #define VIDEO_CLK_MIPI0_DPI_DIV_INT	(VIDEO_CLOCKS_OFFSET + 0x0024)
216 #define VIDEO_CLK_MIPI0_DPI_DIV_FRAC	(VIDEO_CLOCKS_OFFSET + 0x0028)
217 #define VIDEO_CLK_MIPI0_DPI_SEL		(VIDEO_CLOCKS_OFFSET + 0x002c)
218 #define VIDEO_CLK_MIPI1_DPI_CTRL	(VIDEO_CLOCKS_OFFSET + 0x0030)
219 #define VIDEO_CLK_MIPI1_DPI_DIV_INT	(VIDEO_CLOCKS_OFFSET + 0x0034)
220 #define VIDEO_CLK_MIPI1_DPI_DIV_FRAC	(VIDEO_CLOCKS_OFFSET + 0x0038)
221 #define VIDEO_CLK_MIPI1_DPI_SEL		(VIDEO_CLOCKS_OFFSET + 0x003c)
222 
223 #define DIV_INT_8BIT_MAX		GENMASK(7, 0)	/* max divide for most clocks */
224 #define DIV_INT_16BIT_MAX		GENMASK(15, 0)	/* max divide for GPx, PWM */
225 #define DIV_INT_24BIT_MAX               GENMASK(23, 0)	/* max divide for CLK_SYS */
226 
227 #define FC0_STATUS_DONE			BIT(4)
228 #define FC0_STATUS_RUNNING		BIT(8)
229 #define FC0_RESULT_FRAC_SHIFT		5
230 
231 #define PLL_PRIM_DIV1_MASK		GENMASK(18, 16)
232 #define PLL_PRIM_DIV2_MASK		GENMASK(14, 12)
233 
234 #define PLL_SEC_DIV_MASK		GENMASK(12, 8)
235 
236 #define PLL_CS_LOCK			BIT(31)
237 #define PLL_CS_REFDIV_MASK		BIT(1)
238 
239 #define PLL_PWR_PD			BIT(0)
240 #define PLL_PWR_DACPD			BIT(1)
241 #define PLL_PWR_DSMPD			BIT(2)
242 #define PLL_PWR_POSTDIVPD		BIT(3)
243 #define PLL_PWR_4PHASEPD		BIT(4)
244 #define PLL_PWR_VCOPD			BIT(5)
245 #define PLL_PWR_MASK			GENMASK(5, 0)
246 
247 #define PLL_SEC_RST			BIT(16)
248 #define PLL_SEC_IMPL			BIT(31)
249 
250 /* PLL phase output for both PRI and SEC */
251 #define PLL_PH_EN			BIT(4)
252 #define PLL_PH_PHASE_SHIFT		0
253 
254 #define RP1_PLL_PHASE_0			0
255 #define RP1_PLL_PHASE_90		1
256 #define RP1_PLL_PHASE_180		2
257 #define RP1_PLL_PHASE_270		3
258 
259 /* Clock fields for all clocks */
260 #define CLK_CTRL_ENABLE			BIT(11)
261 #define CLK_CTRL_AUXSRC_MASK		GENMASK(9, 5)
262 #define CLK_CTRL_SRC_SHIFT		0
263 #define CLK_DIV_FRAC_BITS		16
264 
265 #define LOCK_TIMEOUT_US			100000
266 #define LOCK_POLL_DELAY_US		5
267 
268 #define MAX_CLK_PARENTS			16
269 
270 #define PLL_DIV_INVALID			19
271 /*
272  * Secondary PLL channel output divider table.
273  * Divider values range from 8 to 19, where
274  * 19 means invalid.
275  */
276 static const struct clk_div_table pll_sec_div_table[] = {
277 	{ 0x00, PLL_DIV_INVALID },
278 	{ 0x01, PLL_DIV_INVALID },
279 	{ 0x02, PLL_DIV_INVALID },
280 	{ 0x03, PLL_DIV_INVALID },
281 	{ 0x04, PLL_DIV_INVALID },
282 	{ 0x05, PLL_DIV_INVALID },
283 	{ 0x06, PLL_DIV_INVALID },
284 	{ 0x07, PLL_DIV_INVALID },
285 	{ 0x08,  8 },
286 	{ 0x09,  9 },
287 	{ 0x0a, 10 },
288 	{ 0x0b, 11 },
289 	{ 0x0c, 12 },
290 	{ 0x0d, 13 },
291 	{ 0x0e, 14 },
292 	{ 0x0f, 15 },
293 	{ 0x10, 16 },
294 	{ 0x11, 17 },
295 	{ 0x12, 18 },
296 	{ 0x13, PLL_DIV_INVALID },
297 	{ 0x14, PLL_DIV_INVALID },
298 	{ 0x15, PLL_DIV_INVALID },
299 	{ 0x16, PLL_DIV_INVALID },
300 	{ 0x17, PLL_DIV_INVALID },
301 	{ 0x18, PLL_DIV_INVALID },
302 	{ 0x19, PLL_DIV_INVALID },
303 	{ 0x1a, PLL_DIV_INVALID },
304 	{ 0x1b, PLL_DIV_INVALID },
305 	{ 0x1c, PLL_DIV_INVALID },
306 	{ 0x1d, PLL_DIV_INVALID },
307 	{ 0x1e, PLL_DIV_INVALID },
308 	{ 0x1f, PLL_DIV_INVALID },
309 	{ 0 }
310 };
311 
312 struct rp1_clockman {
313 	struct device *dev;
314 	void __iomem *regs;
315 	struct regmap *regmap;
316 	spinlock_t regs_lock; /* spinlock for all clocks */
317 
318 	/* Must be last */
319 	struct clk_hw_onecell_data onecell;
320 };
321 
322 struct rp1_pll_core_data {
323 	u32 cs_reg;
324 	u32 pwr_reg;
325 	u32 fbdiv_int_reg;
326 	u32 fbdiv_frac_reg;
327 	u32 fc0_src;
328 };
329 
330 struct rp1_pll_data {
331 	u32 ctrl_reg;
332 	u32 fc0_src;
333 };
334 
335 struct rp1_pll_ph_data {
336 	unsigned int phase;
337 	unsigned int fixed_divider;
338 	u32 ph_reg;
339 	u32 fc0_src;
340 };
341 
342 struct rp1_pll_divider_data {
343 	u32 sec_reg;
344 	u32 fc0_src;
345 };
346 
347 struct rp1_clock_data {
348 	int num_std_parents;
349 	int num_aux_parents;
350 	u32 oe_mask;
351 	u32 clk_src_mask;
352 	u32 ctrl_reg;
353 	u32 div_int_reg;
354 	u32 div_frac_reg;
355 	u32 sel_reg;
356 	u32 div_int_max;
357 	unsigned long max_freq;
358 	u32 fc0_src;
359 };
360 
361 struct rp1_clk_desc {
362 	struct clk_hw *(*clk_register)(struct rp1_clockman *clockman,
363 				       struct rp1_clk_desc *desc);
364 	const void *data;
365 	struct clk_hw hw;
366 	struct rp1_clockman *clockman;
367 	unsigned long cached_rate;
368 	struct clk_divider div;
369 };
370 
371 static inline
clockman_write(struct rp1_clockman * clockman,u32 reg,u32 val)372 void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val)
373 {
374 	regmap_write(clockman->regmap, reg, val);
375 }
376 
clockman_read(struct rp1_clockman * clockman,u32 reg)377 static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg)
378 {
379 	u32 val;
380 
381 	regmap_read(clockman->regmap, reg, &val);
382 
383 	return val;
384 }
385 
rp1_pll_core_is_on(struct clk_hw * hw)386 static int rp1_pll_core_is_on(struct clk_hw *hw)
387 {
388 	struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw);
389 	struct rp1_clockman *clockman = pll_core->clockman;
390 	const struct rp1_pll_core_data *data = pll_core->data;
391 	u32 pwr = clockman_read(clockman, data->pwr_reg);
392 
393 	return (pwr & PLL_PWR_PD) || (pwr & PLL_PWR_POSTDIVPD);
394 }
395 
rp1_pll_core_on(struct clk_hw * hw)396 static int rp1_pll_core_on(struct clk_hw *hw)
397 {
398 	struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw);
399 	struct rp1_clockman *clockman = pll_core->clockman;
400 	const struct rp1_pll_core_data *data = pll_core->data;
401 	u32 fbdiv_frac, val;
402 	int ret;
403 
404 	spin_lock(&clockman->regs_lock);
405 
406 	if (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) {
407 		/* Reset to a known state. */
408 		clockman_write(clockman, data->pwr_reg, PLL_PWR_MASK);
409 		clockman_write(clockman, data->fbdiv_int_reg, 20);
410 		clockman_write(clockman, data->fbdiv_frac_reg, 0);
411 		clockman_write(clockman, data->cs_reg, PLL_CS_REFDIV_MASK);
412 	}
413 
414 	/* Come out of reset. */
415 	fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg);
416 	clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD);
417 	spin_unlock(&clockman->regs_lock);
418 
419 	/* Wait for the PLL to lock. */
420 	ret = regmap_read_poll_timeout(clockman->regmap, data->cs_reg, val,
421 				       val & PLL_CS_LOCK,
422 				       LOCK_POLL_DELAY_US, LOCK_TIMEOUT_US);
423 	if (ret)
424 		dev_err(clockman->dev, "%s: can't lock PLL\n",
425 			clk_hw_get_name(hw));
426 
427 	return ret;
428 }
429 
rp1_pll_core_off(struct clk_hw * hw)430 static void rp1_pll_core_off(struct clk_hw *hw)
431 {
432 	struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw);
433 	struct rp1_clockman *clockman = pll_core->clockman;
434 	const struct rp1_pll_core_data *data = pll_core->data;
435 
436 	spin_lock(&clockman->regs_lock);
437 	clockman_write(clockman, data->pwr_reg, 0);
438 	spin_unlock(&clockman->regs_lock);
439 }
440 
get_pll_core_divider(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,u32 * div_int,u32 * div_frac)441 static inline unsigned long get_pll_core_divider(struct clk_hw *hw,
442 						 unsigned long rate,
443 						 unsigned long parent_rate,
444 						 u32 *div_int, u32 *div_frac)
445 {
446 	u32 fbdiv_int, fbdiv_frac;
447 	unsigned long calc_rate;
448 	u64 shifted_fbdiv_int;
449 	u64 div_fp64; /* 32.32 fixed point fraction. */
450 
451 	/* Factor of reference clock to VCO frequency. */
452 	div_fp64 = (u64)(rate) << 32;
453 	div_fp64 = DIV_ROUND_CLOSEST_ULL(div_fp64, parent_rate);
454 
455 	/* Round the fractional component at 24 bits. */
456 	div_fp64 += 1 << (32 - 24 - 1);
457 
458 	fbdiv_int = div_fp64 >> 32;
459 	fbdiv_frac = (div_fp64 >> (32 - 24)) & 0xffffff;
460 
461 	shifted_fbdiv_int = (u64)fbdiv_int << 24;
462 	calc_rate = (u64)parent_rate * (shifted_fbdiv_int + fbdiv_frac);
463 	calc_rate += BIT(23);
464 	calc_rate >>= 24;
465 
466 	*div_int = fbdiv_int;
467 	*div_frac = fbdiv_frac;
468 
469 	return calc_rate;
470 }
471 
rp1_pll_core_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)472 static int rp1_pll_core_set_rate(struct clk_hw *hw,
473 				 unsigned long rate, unsigned long parent_rate)
474 {
475 	struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw);
476 	struct rp1_clockman *clockman = pll_core->clockman;
477 	const struct rp1_pll_core_data *data = pll_core->data;
478 	unsigned long calc_rate;
479 	u32 fbdiv_int, fbdiv_frac;
480 
481 	/* Disable dividers to start with. */
482 	spin_lock(&clockman->regs_lock);
483 	clockman_write(clockman, data->fbdiv_int_reg, 0);
484 	clockman_write(clockman, data->fbdiv_frac_reg, 0);
485 	spin_unlock(&clockman->regs_lock);
486 
487 	calc_rate = get_pll_core_divider(hw, rate, parent_rate,
488 					 &fbdiv_int, &fbdiv_frac);
489 
490 	spin_lock(&clockman->regs_lock);
491 	clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD);
492 	clockman_write(clockman, data->fbdiv_int_reg, fbdiv_int);
493 	clockman_write(clockman, data->fbdiv_frac_reg, fbdiv_frac);
494 	spin_unlock(&clockman->regs_lock);
495 
496 	/* Check that reference frequency is no greater than VCO / 16. */
497 	if (WARN_ON_ONCE(parent_rate > (rate / 16)))
498 		return -ERANGE;
499 
500 	pll_core->cached_rate = calc_rate;
501 
502 	spin_lock(&clockman->regs_lock);
503 	/* Don't need to divide ref unless parent_rate > (output freq / 16) */
504 	clockman_write(clockman, data->cs_reg,
505 		       clockman_read(clockman, data->cs_reg) |
506 				     PLL_CS_REFDIV_MASK);
507 	spin_unlock(&clockman->regs_lock);
508 
509 	return 0;
510 }
511 
rp1_pll_core_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)512 static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw,
513 					      unsigned long parent_rate)
514 {
515 	struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw);
516 	struct rp1_clockman *clockman = pll_core->clockman;
517 	const struct rp1_pll_core_data *data = pll_core->data;
518 	u32 fbdiv_int, fbdiv_frac;
519 	unsigned long calc_rate;
520 	u64 shifted_fbdiv_int;
521 
522 	fbdiv_int = clockman_read(clockman, data->fbdiv_int_reg);
523 	fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg);
524 
525 	shifted_fbdiv_int = (u64)fbdiv_int << 24;
526 	calc_rate = (u64)parent_rate * (shifted_fbdiv_int + fbdiv_frac);
527 	calc_rate += BIT(23);
528 	calc_rate >>= 24;
529 
530 	return calc_rate;
531 }
532 
rp1_pll_core_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)533 static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate,
534 				    unsigned long *parent_rate)
535 {
536 	u32 fbdiv_int, fbdiv_frac;
537 
538 	return get_pll_core_divider(hw, rate, *parent_rate,
539 				    &fbdiv_int, &fbdiv_frac);
540 }
541 
get_pll_prim_dividers(unsigned long rate,unsigned long parent_rate,u32 * divider1,u32 * divider2)542 static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate,
543 				  u32 *divider1, u32 *divider2)
544 {
545 	unsigned int div1, div2;
546 	unsigned int best_div1 = 7, best_div2 = 7;
547 	unsigned long best_rate_diff =
548 		abs_diff(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate);
549 	unsigned long rate_diff, calc_rate;
550 
551 	for (div1 = 1; div1 <= 7; div1++) {
552 		for (div2 = 1; div2 <= div1; div2++) {
553 			calc_rate = DIV_ROUND_CLOSEST(parent_rate, div1 * div2);
554 			rate_diff = abs_diff(calc_rate, rate);
555 
556 			if (calc_rate == rate) {
557 				best_div1 = div1;
558 				best_div2 = div2;
559 				goto done;
560 			} else if (rate_diff < best_rate_diff) {
561 				best_div1 = div1;
562 				best_div2 = div2;
563 				best_rate_diff = rate_diff;
564 			}
565 		}
566 	}
567 
568 done:
569 	*divider1 = best_div1;
570 	*divider2 = best_div2;
571 }
572 
rp1_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)573 static int rp1_pll_set_rate(struct clk_hw *hw,
574 			    unsigned long rate, unsigned long parent_rate)
575 {
576 	struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw);
577 	struct rp1_clockman *clockman = pll->clockman;
578 	const struct rp1_pll_data *data = pll->data;
579 
580 	u32 prim, prim_div1, prim_div2;
581 
582 	get_pll_prim_dividers(rate, parent_rate, &prim_div1, &prim_div2);
583 
584 	spin_lock(&clockman->regs_lock);
585 	prim = clockman_read(clockman, data->ctrl_reg);
586 	prim &= ~PLL_PRIM_DIV1_MASK;
587 	prim |= FIELD_PREP(PLL_PRIM_DIV1_MASK, prim_div1);
588 	prim &= ~PLL_PRIM_DIV2_MASK;
589 	prim |= FIELD_PREP(PLL_PRIM_DIV2_MASK, prim_div2);
590 	clockman_write(clockman, data->ctrl_reg, prim);
591 	spin_unlock(&clockman->regs_lock);
592 
593 	return 0;
594 }
595 
rp1_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)596 static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw,
597 					 unsigned long parent_rate)
598 {
599 	struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw);
600 	struct rp1_clockman *clockman = pll->clockman;
601 	const struct rp1_pll_data *data = pll->data;
602 	u32 prim, prim_div1, prim_div2;
603 
604 	prim = clockman_read(clockman, data->ctrl_reg);
605 	prim_div1 = FIELD_GET(PLL_PRIM_DIV1_MASK, prim);
606 	prim_div2 = FIELD_GET(PLL_PRIM_DIV2_MASK, prim);
607 
608 	if (!prim_div1 || !prim_div2) {
609 		dev_err(clockman->dev, "%s: (%s) zero divider value\n",
610 			__func__, clk_hw_get_name(hw));
611 		return 0;
612 	}
613 
614 	return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2);
615 }
616 
rp1_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)617 static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate,
618 			       unsigned long *parent_rate)
619 {
620 	u32 div1, div2;
621 
622 	get_pll_prim_dividers(rate, *parent_rate, &div1, &div2);
623 
624 	return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2);
625 }
626 
rp1_pll_ph_is_on(struct clk_hw * hw)627 static int rp1_pll_ph_is_on(struct clk_hw *hw)
628 {
629 	struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw);
630 	struct rp1_clockman *clockman = pll_ph->clockman;
631 	const struct rp1_pll_ph_data *data = pll_ph->data;
632 
633 	return !!(clockman_read(clockman, data->ph_reg) & PLL_PH_EN);
634 }
635 
rp1_pll_ph_on(struct clk_hw * hw)636 static int rp1_pll_ph_on(struct clk_hw *hw)
637 {
638 	struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw);
639 	struct rp1_clockman *clockman = pll_ph->clockman;
640 	const struct rp1_pll_ph_data *data = pll_ph->data;
641 	u32 ph_reg;
642 
643 	spin_lock(&clockman->regs_lock);
644 	ph_reg = clockman_read(clockman, data->ph_reg);
645 	ph_reg |= data->phase << PLL_PH_PHASE_SHIFT;
646 	ph_reg |= PLL_PH_EN;
647 	clockman_write(clockman, data->ph_reg, ph_reg);
648 	spin_unlock(&clockman->regs_lock);
649 
650 	return 0;
651 }
652 
rp1_pll_ph_off(struct clk_hw * hw)653 static void rp1_pll_ph_off(struct clk_hw *hw)
654 {
655 	struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw);
656 	struct rp1_clockman *clockman = pll_ph->clockman;
657 	const struct rp1_pll_ph_data *data = pll_ph->data;
658 
659 	spin_lock(&clockman->regs_lock);
660 	clockman_write(clockman, data->ph_reg,
661 		       clockman_read(clockman, data->ph_reg) & ~PLL_PH_EN);
662 	spin_unlock(&clockman->regs_lock);
663 }
664 
rp1_pll_ph_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)665 static unsigned long rp1_pll_ph_recalc_rate(struct clk_hw *hw,
666 					    unsigned long parent_rate)
667 {
668 	struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw);
669 	const struct rp1_pll_ph_data *data = pll_ph->data;
670 
671 	return parent_rate / data->fixed_divider;
672 }
673 
rp1_pll_ph_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)674 static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate,
675 				  unsigned long *parent_rate)
676 {
677 	struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw);
678 	const struct rp1_pll_ph_data *data = pll_ph->data;
679 
680 	return *parent_rate / data->fixed_divider;
681 }
682 
rp1_pll_divider_is_on(struct clk_hw * hw)683 static int rp1_pll_divider_is_on(struct clk_hw *hw)
684 {
685 	struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw);
686 	struct rp1_clockman *clockman = divider->clockman;
687 	const struct rp1_pll_data *data = divider->data;
688 
689 	return !(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_RST);
690 }
691 
rp1_pll_divider_on(struct clk_hw * hw)692 static int rp1_pll_divider_on(struct clk_hw *hw)
693 {
694 	struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw);
695 	struct rp1_clockman *clockman = divider->clockman;
696 	const struct rp1_pll_data *data = divider->data;
697 
698 	spin_lock(&clockman->regs_lock);
699 	/* Check the implementation bit is set! */
700 	WARN_ON(!(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_IMPL));
701 	clockman_write(clockman, data->ctrl_reg,
702 		       clockman_read(clockman, data->ctrl_reg) & ~PLL_SEC_RST);
703 	spin_unlock(&clockman->regs_lock);
704 
705 	return 0;
706 }
707 
rp1_pll_divider_off(struct clk_hw * hw)708 static void rp1_pll_divider_off(struct clk_hw *hw)
709 {
710 	struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw);
711 	struct rp1_clockman *clockman = divider->clockman;
712 	const struct rp1_pll_data *data = divider->data;
713 
714 	spin_lock(&clockman->regs_lock);
715 	clockman_write(clockman, data->ctrl_reg,
716 		       clockman_read(clockman, data->ctrl_reg) | PLL_SEC_RST);
717 	spin_unlock(&clockman->regs_lock);
718 }
719 
rp1_pll_divider_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)720 static int rp1_pll_divider_set_rate(struct clk_hw *hw,
721 				    unsigned long rate,
722 				    unsigned long parent_rate)
723 {
724 	struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw);
725 	struct rp1_clockman *clockman = divider->clockman;
726 	const struct rp1_pll_data *data = divider->data;
727 	u32 div, sec;
728 
729 	div = DIV_ROUND_UP_ULL(parent_rate, rate);
730 	div = clamp(div, 8u, 19u);
731 
732 	spin_lock(&clockman->regs_lock);
733 	sec = clockman_read(clockman, data->ctrl_reg);
734 	sec &= ~PLL_SEC_DIV_MASK;
735 	sec |= FIELD_PREP(PLL_SEC_DIV_MASK, div);
736 
737 	/* Must keep the divider in reset to change the value. */
738 	sec |= PLL_SEC_RST;
739 	clockman_write(clockman, data->ctrl_reg, sec);
740 
741 	/* must sleep 10 pll vco cycles */
742 	ndelay(div64_ul(10ULL * div * NSEC_PER_SEC, parent_rate));
743 
744 	sec &= ~PLL_SEC_RST;
745 	clockman_write(clockman, data->ctrl_reg, sec);
746 	spin_unlock(&clockman->regs_lock);
747 
748 	return 0;
749 }
750 
rp1_pll_divider_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)751 static unsigned long rp1_pll_divider_recalc_rate(struct clk_hw *hw,
752 						 unsigned long parent_rate)
753 {
754 	return clk_divider_ops.recalc_rate(hw, parent_rate);
755 }
756 
rp1_pll_divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)757 static long rp1_pll_divider_round_rate(struct clk_hw *hw,
758 				       unsigned long rate,
759 				       unsigned long *parent_rate)
760 {
761 	return clk_divider_ops.round_rate(hw, rate, parent_rate);
762 }
763 
rp1_clock_is_on(struct clk_hw * hw)764 static int rp1_clock_is_on(struct clk_hw *hw)
765 {
766 	struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
767 	struct rp1_clockman *clockman = clock->clockman;
768 	const struct rp1_clock_data *data = clock->data;
769 
770 	return !!(clockman_read(clockman, data->ctrl_reg) & CLK_CTRL_ENABLE);
771 }
772 
rp1_clock_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)773 static unsigned long rp1_clock_recalc_rate(struct clk_hw *hw,
774 					   unsigned long parent_rate)
775 {
776 	struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
777 	struct rp1_clockman *clockman = clock->clockman;
778 	const struct rp1_clock_data *data = clock->data;
779 	u64 calc_rate;
780 	u64 div;
781 	u32 frac;
782 
783 	div = clockman_read(clockman, data->div_int_reg);
784 	frac = (data->div_frac_reg != 0) ?
785 		clockman_read(clockman, data->div_frac_reg) : 0;
786 
787 	/* If the integer portion of the divider is 0, treat it as 2^16 */
788 	if (!div)
789 		div = 1 << 16;
790 
791 	div = (div << CLK_DIV_FRAC_BITS) | (frac >> (32 - CLK_DIV_FRAC_BITS));
792 
793 	calc_rate = (u64)parent_rate << CLK_DIV_FRAC_BITS;
794 	calc_rate = div64_u64(calc_rate, div);
795 
796 	return calc_rate;
797 }
798 
rp1_clock_on(struct clk_hw * hw)799 static int rp1_clock_on(struct clk_hw *hw)
800 {
801 	struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
802 	struct rp1_clockman *clockman = clock->clockman;
803 	const struct rp1_clock_data *data = clock->data;
804 
805 	spin_lock(&clockman->regs_lock);
806 	clockman_write(clockman, data->ctrl_reg,
807 		       clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE);
808 	/* If this is a GPCLK, turn on the output-enable */
809 	if (data->oe_mask)
810 		clockman_write(clockman, GPCLK_OE_CTRL,
811 			       clockman_read(clockman, GPCLK_OE_CTRL) | data->oe_mask);
812 	spin_unlock(&clockman->regs_lock);
813 
814 	return 0;
815 }
816 
rp1_clock_off(struct clk_hw * hw)817 static void rp1_clock_off(struct clk_hw *hw)
818 {
819 	struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
820 	struct rp1_clockman *clockman = clock->clockman;
821 	const struct rp1_clock_data *data = clock->data;
822 
823 	spin_lock(&clockman->regs_lock);
824 	clockman_write(clockman, data->ctrl_reg,
825 		       clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE);
826 	/* If this is a GPCLK, turn off the output-enable */
827 	if (data->oe_mask)
828 		clockman_write(clockman, GPCLK_OE_CTRL,
829 			       clockman_read(clockman, GPCLK_OE_CTRL) & ~data->oe_mask);
830 	spin_unlock(&clockman->regs_lock);
831 }
832 
rp1_clock_choose_div(unsigned long rate,unsigned long parent_rate,const struct rp1_clock_data * data)833 static u32 rp1_clock_choose_div(unsigned long rate, unsigned long parent_rate,
834 				const struct rp1_clock_data *data)
835 {
836 	u64 div;
837 
838 	/*
839 	 * Due to earlier rounding, calculated parent_rate may differ from
840 	 * expected value. Don't fail on a small discrepancy near unity divide.
841 	 */
842 	if (!rate || rate > parent_rate + (parent_rate >> CLK_DIV_FRAC_BITS))
843 		return 0;
844 
845 	/*
846 	 * Always express div in fixed-point format for fractional division;
847 	 * If no fractional divider is present, the fraction part will be zero.
848 	 */
849 	if (data->div_frac_reg) {
850 		div = (u64)parent_rate << CLK_DIV_FRAC_BITS;
851 		div = DIV_ROUND_CLOSEST_ULL(div, rate);
852 	} else {
853 		div = DIV_ROUND_CLOSEST_ULL(parent_rate, rate);
854 		div <<= CLK_DIV_FRAC_BITS;
855 	}
856 
857 	div = clamp(div,
858 		    1ull << CLK_DIV_FRAC_BITS,
859 		    (u64)data->div_int_max << CLK_DIV_FRAC_BITS);
860 
861 	return div;
862 }
863 
rp1_clock_get_parent(struct clk_hw * hw)864 static u8 rp1_clock_get_parent(struct clk_hw *hw)
865 {
866 	struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
867 	struct rp1_clockman *clockman = clock->clockman;
868 	const struct rp1_clock_data *data = clock->data;
869 	u32 sel, ctrl;
870 	u8 parent;
871 
872 	/* Sel is one-hot, so find the first bit set */
873 	sel = clockman_read(clockman, data->sel_reg);
874 	parent = ffs(sel) - 1;
875 
876 	/* sel == 0 implies the parent clock is not enabled yet. */
877 	if (!sel) {
878 		/* Read the clock src from the CTRL register instead */
879 		ctrl = clockman_read(clockman, data->ctrl_reg);
880 		parent = (ctrl & data->clk_src_mask) >> CLK_CTRL_SRC_SHIFT;
881 	}
882 
883 	if (parent >= data->num_std_parents)
884 		parent = AUX_SEL;
885 
886 	if (parent == AUX_SEL) {
887 		/*
888 		 * Clock parent is an auxiliary source, so get the parent from
889 		 * the AUXSRC register field.
890 		 */
891 		ctrl = clockman_read(clockman, data->ctrl_reg);
892 		parent = FIELD_GET(CLK_CTRL_AUXSRC_MASK, ctrl);
893 		parent += data->num_std_parents;
894 	}
895 
896 	return parent;
897 }
898 
rp1_clock_set_parent(struct clk_hw * hw,u8 index)899 static int rp1_clock_set_parent(struct clk_hw *hw, u8 index)
900 {
901 	struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
902 	struct rp1_clockman *clockman = clock->clockman;
903 	const struct rp1_clock_data *data = clock->data;
904 	u32 ctrl, sel;
905 
906 	spin_lock(&clockman->regs_lock);
907 	ctrl = clockman_read(clockman, data->ctrl_reg);
908 
909 	if (index >= data->num_std_parents) {
910 		/* This is an aux source request */
911 		if (index >= data->num_std_parents + data->num_aux_parents) {
912 			spin_unlock(&clockman->regs_lock);
913 			return -EINVAL;
914 		}
915 
916 		/* Select parent from aux list */
917 		ctrl &= ~CLK_CTRL_AUXSRC_MASK;
918 		ctrl |= FIELD_PREP(CLK_CTRL_AUXSRC_MASK, index - data->num_std_parents);
919 		/* Set src to aux list */
920 		ctrl &= ~data->clk_src_mask;
921 		ctrl |= (AUX_SEL << CLK_CTRL_SRC_SHIFT) & data->clk_src_mask;
922 	} else {
923 		ctrl &= ~data->clk_src_mask;
924 		ctrl |= (index << CLK_CTRL_SRC_SHIFT) & data->clk_src_mask;
925 	}
926 
927 	clockman_write(clockman, data->ctrl_reg, ctrl);
928 	spin_unlock(&clockman->regs_lock);
929 
930 	sel = rp1_clock_get_parent(hw);
931 	if (sel != index)
932 		return -EINVAL;
933 
934 	return 0;
935 }
936 
rp1_clock_set_rate_and_parent(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,u8 parent)937 static int rp1_clock_set_rate_and_parent(struct clk_hw *hw,
938 					 unsigned long rate,
939 					 unsigned long parent_rate,
940 					 u8 parent)
941 {
942 	struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
943 	struct rp1_clockman *clockman = clock->clockman;
944 	const struct rp1_clock_data *data = clock->data;
945 	u32 div = rp1_clock_choose_div(rate, parent_rate, data);
946 
947 	spin_lock(&clockman->regs_lock);
948 
949 	clockman_write(clockman, data->div_int_reg, div >> CLK_DIV_FRAC_BITS);
950 	if (data->div_frac_reg)
951 		clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS));
952 
953 	spin_unlock(&clockman->regs_lock);
954 
955 	if (parent != 0xff)
956 		return rp1_clock_set_parent(hw, parent);
957 
958 	return 0;
959 }
960 
rp1_clock_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)961 static int rp1_clock_set_rate(struct clk_hw *hw, unsigned long rate,
962 			      unsigned long parent_rate)
963 {
964 	return rp1_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff);
965 }
966 
rp1_clock_choose_div_and_prate(struct clk_hw * hw,int parent_idx,unsigned long rate,unsigned long * prate,unsigned long * calc_rate)967 static void rp1_clock_choose_div_and_prate(struct clk_hw *hw,
968 					   int parent_idx,
969 					   unsigned long rate,
970 					   unsigned long *prate,
971 					   unsigned long *calc_rate)
972 {
973 	struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw);
974 	const struct rp1_clock_data *data = clock->data;
975 	struct clk_hw *parent;
976 	u32 div;
977 	u64 tmp;
978 
979 	parent = clk_hw_get_parent_by_index(hw, parent_idx);
980 
981 	*prate = clk_hw_get_rate(parent);
982 	div = rp1_clock_choose_div(rate, *prate, data);
983 
984 	if (!div) {
985 		*calc_rate = 0;
986 		return;
987 	}
988 
989 	/* Recalculate to account for rounding errors */
990 	tmp = (u64)*prate << CLK_DIV_FRAC_BITS;
991 	tmp = div_u64(tmp, div);
992 
993 	/*
994 	 * Prevent overclocks - if all parent choices result in
995 	 * a downstream clock in excess of the maximum, then the
996 	 * call to set the clock will fail.
997 	 */
998 	if (tmp > data->max_freq)
999 		*calc_rate = 0;
1000 	else
1001 		*calc_rate = tmp;
1002 }
1003 
rp1_clock_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)1004 static int rp1_clock_determine_rate(struct clk_hw *hw,
1005 				    struct clk_rate_request *req)
1006 {
1007 	struct clk_hw *parent, *best_parent = NULL;
1008 	unsigned long best_rate = 0;
1009 	unsigned long best_prate = 0;
1010 	unsigned long best_rate_diff = ULONG_MAX;
1011 	unsigned long prate, calc_rate;
1012 	size_t i;
1013 
1014 	/*
1015 	 * If the NO_REPARENT flag is set, try to use existing parent.
1016 	 */
1017 	if ((clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT)) {
1018 		i = rp1_clock_get_parent(hw);
1019 		parent = clk_hw_get_parent_by_index(hw, i);
1020 		if (parent) {
1021 			rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate,
1022 						       &calc_rate);
1023 			if (calc_rate > 0) {
1024 				req->best_parent_hw = parent;
1025 				req->best_parent_rate = prate;
1026 				req->rate = calc_rate;
1027 				return 0;
1028 			}
1029 		}
1030 	}
1031 
1032 	/*
1033 	 * Select parent clock that results in the closest rate (lower or
1034 	 * higher)
1035 	 */
1036 	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
1037 		parent = clk_hw_get_parent_by_index(hw, i);
1038 		if (!parent)
1039 			continue;
1040 
1041 		rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate,
1042 					       &calc_rate);
1043 
1044 		if (abs_diff(calc_rate, req->rate) < best_rate_diff) {
1045 			best_parent = parent;
1046 			best_prate = prate;
1047 			best_rate = calc_rate;
1048 			best_rate_diff = abs_diff(calc_rate, req->rate);
1049 
1050 			if (best_rate_diff == 0)
1051 				break;
1052 		}
1053 	}
1054 
1055 	if (best_rate == 0)
1056 		return -EINVAL;
1057 
1058 	req->best_parent_hw = best_parent;
1059 	req->best_parent_rate = best_prate;
1060 	req->rate = best_rate;
1061 
1062 	return 0;
1063 }
1064 
1065 static const struct clk_ops rp1_pll_core_ops = {
1066 	.is_prepared = rp1_pll_core_is_on,
1067 	.prepare = rp1_pll_core_on,
1068 	.unprepare = rp1_pll_core_off,
1069 	.set_rate = rp1_pll_core_set_rate,
1070 	.recalc_rate = rp1_pll_core_recalc_rate,
1071 	.round_rate = rp1_pll_core_round_rate,
1072 };
1073 
1074 static const struct clk_ops rp1_pll_ops = {
1075 	.set_rate = rp1_pll_set_rate,
1076 	.recalc_rate = rp1_pll_recalc_rate,
1077 	.round_rate = rp1_pll_round_rate,
1078 };
1079 
1080 static const struct clk_ops rp1_pll_ph_ops = {
1081 	.is_prepared = rp1_pll_ph_is_on,
1082 	.prepare = rp1_pll_ph_on,
1083 	.unprepare = rp1_pll_ph_off,
1084 	.recalc_rate = rp1_pll_ph_recalc_rate,
1085 	.round_rate = rp1_pll_ph_round_rate,
1086 };
1087 
1088 static const struct clk_ops rp1_pll_divider_ops = {
1089 	.is_prepared = rp1_pll_divider_is_on,
1090 	.prepare = rp1_pll_divider_on,
1091 	.unprepare = rp1_pll_divider_off,
1092 	.set_rate = rp1_pll_divider_set_rate,
1093 	.recalc_rate = rp1_pll_divider_recalc_rate,
1094 	.round_rate = rp1_pll_divider_round_rate,
1095 };
1096 
1097 static const struct clk_ops rp1_clk_ops = {
1098 	.is_prepared = rp1_clock_is_on,
1099 	.prepare = rp1_clock_on,
1100 	.unprepare = rp1_clock_off,
1101 	.recalc_rate = rp1_clock_recalc_rate,
1102 	.get_parent = rp1_clock_get_parent,
1103 	.set_parent = rp1_clock_set_parent,
1104 	.set_rate_and_parent = rp1_clock_set_rate_and_parent,
1105 	.set_rate = rp1_clock_set_rate,
1106 	.determine_rate = rp1_clock_determine_rate,
1107 };
1108 
rp1_register_pll(struct rp1_clockman * clockman,struct rp1_clk_desc * desc)1109 static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman,
1110 				       struct rp1_clk_desc *desc)
1111 {
1112 	int ret;
1113 
1114 	desc->clockman = clockman;
1115 
1116 	ret = devm_clk_hw_register(clockman->dev, &desc->hw);
1117 	if (ret)
1118 		return ERR_PTR(ret);
1119 
1120 	return &desc->hw;
1121 }
1122 
rp1_register_pll_divider(struct rp1_clockman * clockman,struct rp1_clk_desc * desc)1123 static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman,
1124 					       struct rp1_clk_desc *desc)
1125 {
1126 	const struct rp1_pll_data *divider_data = desc->data;
1127 	int ret;
1128 
1129 	desc->div.reg = clockman->regs + divider_data->ctrl_reg;
1130 	desc->div.shift = __ffs(PLL_SEC_DIV_MASK);
1131 	desc->div.width = __ffs(~(PLL_SEC_DIV_MASK >> desc->div.shift));
1132 	desc->div.flags = CLK_DIVIDER_ROUND_CLOSEST;
1133 	desc->div.lock = &clockman->regs_lock;
1134 	desc->div.hw.init = desc->hw.init;
1135 	desc->div.table = pll_sec_div_table;
1136 
1137 	desc->clockman = clockman;
1138 
1139 	ret = devm_clk_hw_register(clockman->dev, &desc->div.hw);
1140 	if (ret)
1141 		return ERR_PTR(ret);
1142 
1143 	return &desc->div.hw;
1144 }
1145 
rp1_register_clock(struct rp1_clockman * clockman,struct rp1_clk_desc * desc)1146 static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman,
1147 					 struct rp1_clk_desc *desc)
1148 {
1149 	const struct rp1_clock_data *clock_data = desc->data;
1150 	int ret;
1151 
1152 	if (WARN_ON_ONCE(MAX_CLK_PARENTS <
1153 	       clock_data->num_std_parents + clock_data->num_aux_parents))
1154 		return ERR_PTR(-EINVAL);
1155 
1156 	/* There must be a gap for the AUX selector */
1157 	if (WARN_ON_ONCE(clock_data->num_std_parents > AUX_SEL &&
1158 			 desc->hw.init->parent_data[AUX_SEL].index != -1))
1159 		return ERR_PTR(-EINVAL);
1160 
1161 	desc->clockman = clockman;
1162 
1163 	ret = devm_clk_hw_register(clockman->dev, &desc->hw);
1164 	if (ret)
1165 		return ERR_PTR(ret);
1166 
1167 	return &desc->hw;
1168 }
1169 
1170 /* Assignment helper macros for different clock types. */
1171 #define _REGISTER(f, ...)	{ .clk_register = f, __VA_ARGS__ }
1172 
1173 #define CLK_DATA(type, ...)	.data = &(struct type) { __VA_ARGS__ }
1174 
1175 #define REGISTER_PLL(...)	_REGISTER(&rp1_register_pll,		\
1176 					  __VA_ARGS__)
1177 
1178 #define REGISTER_PLL_DIV(...)	_REGISTER(&rp1_register_pll_divider,	\
1179 					  __VA_ARGS__)
1180 
1181 #define REGISTER_CLK(...)	_REGISTER(&rp1_register_clock,		\
1182 					  __VA_ARGS__)
1183 
1184 static struct rp1_clk_desc pll_sys_core_desc = REGISTER_PLL(
1185 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1186 		"pll_sys_core",
1187 		(const struct clk_parent_data[]) { { .index = 0 } },
1188 		&rp1_pll_core_ops,
1189 		CLK_IS_CRITICAL
1190 	),
1191 	CLK_DATA(rp1_pll_core_data,
1192 		 .cs_reg = PLL_SYS_CS,
1193 		 .pwr_reg = PLL_SYS_PWR,
1194 		 .fbdiv_int_reg = PLL_SYS_FBDIV_INT,
1195 		 .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC,
1196 	)
1197 );
1198 
1199 static struct rp1_clk_desc pll_audio_core_desc = REGISTER_PLL(
1200 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1201 		"pll_audio_core",
1202 		(const struct clk_parent_data[]) { { .index = 0 } },
1203 		&rp1_pll_core_ops,
1204 		CLK_IS_CRITICAL
1205 	),
1206 	CLK_DATA(rp1_pll_core_data,
1207 		 .cs_reg = PLL_AUDIO_CS,
1208 		 .pwr_reg = PLL_AUDIO_PWR,
1209 		 .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT,
1210 		 .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC,
1211 	)
1212 );
1213 
1214 static struct rp1_clk_desc pll_video_core_desc = REGISTER_PLL(
1215 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1216 		"pll_video_core",
1217 		(const struct clk_parent_data[]) { { .index = 0 } },
1218 		&rp1_pll_core_ops,
1219 		CLK_IS_CRITICAL
1220 	),
1221 	CLK_DATA(rp1_pll_core_data,
1222 		 .cs_reg = PLL_VIDEO_CS,
1223 		 .pwr_reg = PLL_VIDEO_PWR,
1224 		 .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT,
1225 		 .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC,
1226 	)
1227 );
1228 
1229 static struct rp1_clk_desc pll_sys_desc = REGISTER_PLL(
1230 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1231 		"pll_sys",
1232 		(const struct clk_parent_data[]) {
1233 			{ .hw = &pll_sys_core_desc.hw }
1234 		},
1235 		&rp1_pll_ops,
1236 		0
1237 	),
1238 	CLK_DATA(rp1_pll_data,
1239 		 .ctrl_reg = PLL_SYS_PRIM,
1240 		 .fc0_src = FC_NUM(0, 2),
1241 	)
1242 );
1243 
1244 static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV(
1245 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1246 		"pll_sys_sec",
1247 		(const struct clk_parent_data[]) {
1248 			{ .hw = &pll_sys_core_desc.hw }
1249 		},
1250 		&rp1_pll_divider_ops,
1251 		0
1252 	),
1253 	CLK_DATA(rp1_pll_data,
1254 		 .ctrl_reg = PLL_SYS_SEC,
1255 		 .fc0_src = FC_NUM(2, 2),
1256 	)
1257 );
1258 
1259 static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK(
1260 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1261 		"clk_eth_tsu",
1262 		(const struct clk_parent_data[]) { { .index = 0 } },
1263 		&rp1_clk_ops,
1264 		0
1265 	),
1266 	CLK_DATA(rp1_clock_data,
1267 		 .num_std_parents = 0,
1268 		 .num_aux_parents = 1,
1269 		 .ctrl_reg = CLK_ETH_TSU_CTRL,
1270 		 .div_int_reg = CLK_ETH_TSU_DIV_INT,
1271 		 .sel_reg = CLK_ETH_TSU_SEL,
1272 		 .div_int_max = DIV_INT_8BIT_MAX,
1273 		 .max_freq = 50 * HZ_PER_MHZ,
1274 		 .fc0_src = FC_NUM(5, 7),
1275 	)
1276 );
1277 
1278 static const struct clk_parent_data clk_eth_parents[] = {
1279 	{ .hw = &pll_sys_sec_desc.div.hw },
1280 	{ .hw = &pll_sys_desc.hw },
1281 };
1282 
1283 static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK(
1284 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1285 		"clk_eth",
1286 		clk_eth_parents,
1287 		&rp1_clk_ops,
1288 		0
1289 	),
1290 	CLK_DATA(rp1_clock_data,
1291 		 .num_std_parents = 0,
1292 		 .num_aux_parents = 2,
1293 		 .ctrl_reg = CLK_ETH_CTRL,
1294 		 .div_int_reg = CLK_ETH_DIV_INT,
1295 		 .sel_reg = CLK_ETH_SEL,
1296 		 .div_int_max = DIV_INT_8BIT_MAX,
1297 		 .max_freq = 125 * HZ_PER_MHZ,
1298 		 .fc0_src = FC_NUM(4, 6),
1299 	)
1300 );
1301 
1302 static const struct clk_parent_data clk_sys_parents[] = {
1303 	{ .index = 0 },
1304 	{ .index = -1 },
1305 	{ .hw = &pll_sys_desc.hw },
1306 };
1307 
1308 static struct rp1_clk_desc clk_sys_desc = REGISTER_CLK(
1309 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1310 		"clk_sys",
1311 		clk_sys_parents,
1312 		&rp1_clk_ops,
1313 		CLK_IS_CRITICAL
1314 	),
1315 	CLK_DATA(rp1_clock_data,
1316 		 .num_std_parents = 3,
1317 		 .num_aux_parents = 0,
1318 		 .ctrl_reg = CLK_SYS_CTRL,
1319 		 .div_int_reg = CLK_SYS_DIV_INT,
1320 		 .sel_reg = CLK_SYS_SEL,
1321 		 .div_int_max = DIV_INT_24BIT_MAX,
1322 		 .max_freq = 200 * HZ_PER_MHZ,
1323 		 .fc0_src = FC_NUM(0, 4),
1324 		 .clk_src_mask = 0x3,
1325 	)
1326 );
1327 
1328 static struct rp1_clk_desc pll_sys_pri_ph_desc = REGISTER_PLL(
1329 	.hw.init = CLK_HW_INIT_PARENTS_DATA(
1330 		"pll_sys_pri_ph",
1331 		(const struct clk_parent_data[]) {
1332 			{ .hw = &pll_sys_desc.hw }
1333 		},
1334 		&rp1_pll_ph_ops,
1335 		0
1336 	),
1337 	CLK_DATA(rp1_pll_ph_data,
1338 		 .ph_reg = PLL_SYS_PRIM,
1339 		 .fixed_divider = 2,
1340 		 .phase = RP1_PLL_PHASE_0,
1341 		 .fc0_src = FC_NUM(1, 2),
1342 	)
1343 );
1344 
1345 static struct rp1_clk_desc *const clk_desc_array[] = {
1346 	[RP1_PLL_SYS_CORE] = &pll_sys_core_desc,
1347 	[RP1_PLL_AUDIO_CORE] = &pll_audio_core_desc,
1348 	[RP1_PLL_VIDEO_CORE] = &pll_video_core_desc,
1349 	[RP1_PLL_SYS] = &pll_sys_desc,
1350 	[RP1_CLK_ETH_TSU] = &clk_eth_tsu_desc,
1351 	[RP1_CLK_ETH] = &clk_eth_desc,
1352 	[RP1_CLK_SYS] = &clk_sys_desc,
1353 	[RP1_PLL_SYS_PRI_PH] = &pll_sys_pri_ph_desc,
1354 	[RP1_PLL_SYS_SEC] = &pll_sys_sec_desc,
1355 };
1356 
1357 static const struct regmap_range rp1_reg_ranges[] = {
1358 	regmap_reg_range(PLL_SYS_CS, PLL_SYS_SEC),
1359 	regmap_reg_range(PLL_AUDIO_CS, PLL_AUDIO_TERN),
1360 	regmap_reg_range(PLL_VIDEO_CS, PLL_VIDEO_SEC),
1361 	regmap_reg_range(GPCLK_OE_CTRL, GPCLK_OE_CTRL),
1362 	regmap_reg_range(CLK_SYS_CTRL, CLK_SYS_DIV_INT),
1363 	regmap_reg_range(CLK_SYS_SEL, CLK_SYS_SEL),
1364 	regmap_reg_range(CLK_SLOW_SYS_CTRL, CLK_SLOW_SYS_DIV_INT),
1365 	regmap_reg_range(CLK_SLOW_SYS_SEL, CLK_SLOW_SYS_SEL),
1366 	regmap_reg_range(CLK_DMA_CTRL, CLK_DMA_DIV_INT),
1367 	regmap_reg_range(CLK_DMA_SEL, CLK_DMA_SEL),
1368 	regmap_reg_range(CLK_UART_CTRL, CLK_UART_DIV_INT),
1369 	regmap_reg_range(CLK_UART_SEL, CLK_UART_SEL),
1370 	regmap_reg_range(CLK_ETH_CTRL, CLK_ETH_DIV_INT),
1371 	regmap_reg_range(CLK_ETH_SEL, CLK_ETH_SEL),
1372 	regmap_reg_range(CLK_PWM0_CTRL, CLK_PWM0_SEL),
1373 	regmap_reg_range(CLK_PWM1_CTRL, CLK_PWM1_SEL),
1374 	regmap_reg_range(CLK_AUDIO_IN_CTRL, CLK_AUDIO_IN_DIV_INT),
1375 	regmap_reg_range(CLK_AUDIO_IN_SEL, CLK_AUDIO_IN_SEL),
1376 	regmap_reg_range(CLK_AUDIO_OUT_CTRL, CLK_AUDIO_OUT_DIV_INT),
1377 	regmap_reg_range(CLK_AUDIO_OUT_SEL, CLK_AUDIO_OUT_SEL),
1378 	regmap_reg_range(CLK_I2S_CTRL, CLK_I2S_DIV_INT),
1379 	regmap_reg_range(CLK_I2S_SEL, CLK_I2S_SEL),
1380 	regmap_reg_range(CLK_MIPI0_CFG_CTRL, CLK_MIPI0_CFG_DIV_INT),
1381 	regmap_reg_range(CLK_MIPI0_CFG_SEL, CLK_MIPI0_CFG_SEL),
1382 	regmap_reg_range(CLK_MIPI1_CFG_CTRL, CLK_MIPI1_CFG_DIV_INT),
1383 	regmap_reg_range(CLK_MIPI1_CFG_SEL, CLK_MIPI1_CFG_SEL),
1384 	regmap_reg_range(CLK_PCIE_AUX_CTRL, CLK_PCIE_AUX_DIV_INT),
1385 	regmap_reg_range(CLK_PCIE_AUX_SEL, CLK_PCIE_AUX_SEL),
1386 	regmap_reg_range(CLK_USBH0_MICROFRAME_CTRL, CLK_USBH0_MICROFRAME_DIV_INT),
1387 	regmap_reg_range(CLK_USBH0_MICROFRAME_SEL, CLK_USBH0_MICROFRAME_SEL),
1388 	regmap_reg_range(CLK_USBH1_MICROFRAME_CTRL, CLK_USBH1_MICROFRAME_DIV_INT),
1389 	regmap_reg_range(CLK_USBH1_MICROFRAME_SEL, CLK_USBH1_MICROFRAME_SEL),
1390 	regmap_reg_range(CLK_USBH0_SUSPEND_CTRL, CLK_USBH0_SUSPEND_DIV_INT),
1391 	regmap_reg_range(CLK_USBH0_SUSPEND_SEL, CLK_USBH0_SUSPEND_SEL),
1392 	regmap_reg_range(CLK_USBH1_SUSPEND_CTRL, CLK_USBH1_SUSPEND_DIV_INT),
1393 	regmap_reg_range(CLK_USBH1_SUSPEND_SEL, CLK_USBH1_SUSPEND_SEL),
1394 	regmap_reg_range(CLK_ETH_TSU_CTRL, CLK_ETH_TSU_DIV_INT),
1395 	regmap_reg_range(CLK_ETH_TSU_SEL, CLK_ETH_TSU_SEL),
1396 	regmap_reg_range(CLK_ADC_CTRL, CLK_ADC_DIV_INT),
1397 	regmap_reg_range(CLK_ADC_SEL, CLK_ADC_SEL),
1398 	regmap_reg_range(CLK_SDIO_TIMER_CTRL, CLK_SDIO_TIMER_DIV_INT),
1399 	regmap_reg_range(CLK_SDIO_TIMER_SEL, CLK_SDIO_TIMER_SEL),
1400 	regmap_reg_range(CLK_SDIO_ALT_SRC_CTRL, CLK_SDIO_ALT_SRC_DIV_INT),
1401 	regmap_reg_range(CLK_SDIO_ALT_SRC_SEL, CLK_SDIO_ALT_SRC_SEL),
1402 	regmap_reg_range(CLK_GP0_CTRL, CLK_GP0_SEL),
1403 	regmap_reg_range(CLK_GP1_CTRL, CLK_GP1_SEL),
1404 	regmap_reg_range(CLK_GP2_CTRL, CLK_GP2_SEL),
1405 	regmap_reg_range(CLK_GP3_CTRL, CLK_GP3_SEL),
1406 	regmap_reg_range(CLK_GP4_CTRL, CLK_GP4_SEL),
1407 	regmap_reg_range(CLK_GP5_CTRL, CLK_GP5_SEL),
1408 	regmap_reg_range(CLK_SYS_RESUS_CTRL, CLK_SYS_RESUS_CTRL),
1409 	regmap_reg_range(CLK_SLOW_SYS_RESUS_CTRL, CLK_SLOW_SYS_RESUS_CTRL),
1410 	regmap_reg_range(FC0_REF_KHZ, FC0_RESULT),
1411 	regmap_reg_range(VIDEO_CLK_VEC_CTRL, VIDEO_CLK_VEC_DIV_INT),
1412 	regmap_reg_range(VIDEO_CLK_VEC_SEL, VIDEO_CLK_DPI_DIV_INT),
1413 	regmap_reg_range(VIDEO_CLK_DPI_SEL, VIDEO_CLK_MIPI1_DPI_SEL),
1414 };
1415 
1416 static const struct regmap_access_table rp1_reg_table = {
1417 	.yes_ranges = rp1_reg_ranges,
1418 	.n_yes_ranges = ARRAY_SIZE(rp1_reg_ranges),
1419 };
1420 
1421 static const struct regmap_config rp1_clk_regmap_cfg = {
1422 	.reg_bits = 32,
1423 	.val_bits = 32,
1424 	.reg_stride = 4,
1425 	.max_register = PLL_VIDEO_SEC,
1426 	.name = "rp1-clk",
1427 	.rd_table = &rp1_reg_table,
1428 	.disable_locking = true,
1429 };
1430 
rp1_clk_probe(struct platform_device * pdev)1431 static int rp1_clk_probe(struct platform_device *pdev)
1432 {
1433 	const size_t asize = ARRAY_SIZE(clk_desc_array);
1434 	struct rp1_clk_desc *desc;
1435 	struct device *dev = &pdev->dev;
1436 	struct rp1_clockman *clockman;
1437 	struct clk_hw **hws;
1438 	unsigned int i;
1439 
1440 	clockman = devm_kzalloc(dev, struct_size(clockman, onecell.hws, asize),
1441 				GFP_KERNEL);
1442 	if (!clockman)
1443 		return -ENOMEM;
1444 
1445 	spin_lock_init(&clockman->regs_lock);
1446 	clockman->dev = dev;
1447 
1448 	clockman->regs = devm_platform_ioremap_resource(pdev, 0);
1449 	if (IS_ERR(clockman->regs))
1450 		return PTR_ERR(clockman->regs);
1451 
1452 	clockman->regmap = devm_regmap_init_mmio(dev, clockman->regs,
1453 						 &rp1_clk_regmap_cfg);
1454 	if (IS_ERR(clockman->regmap)) {
1455 		dev_err_probe(dev, PTR_ERR(clockman->regmap),
1456 			      "could not init clock regmap\n");
1457 		return PTR_ERR(clockman->regmap);
1458 	}
1459 
1460 	clockman->onecell.num = asize;
1461 	hws = clockman->onecell.hws;
1462 
1463 	for (i = 0; i < asize; i++) {
1464 		desc = clk_desc_array[i];
1465 		if (desc && desc->clk_register && desc->data)
1466 			hws[i] = desc->clk_register(clockman, desc);
1467 	}
1468 
1469 	platform_set_drvdata(pdev, clockman);
1470 
1471 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1472 					   &clockman->onecell);
1473 }
1474 
1475 static const struct of_device_id rp1_clk_of_match[] = {
1476 	{ .compatible = "raspberrypi,rp1-clocks" },
1477 	{}
1478 };
1479 MODULE_DEVICE_TABLE(of, rp1_clk_of_match);
1480 
1481 static struct platform_driver rp1_clk_driver = {
1482 	.driver = {
1483 		.name = "rp1-clk",
1484 		.of_match_table = rp1_clk_of_match,
1485 	},
1486 	.probe = rp1_clk_probe,
1487 };
1488 
1489 module_platform_driver(rp1_clk_driver);
1490 
1491 MODULE_AUTHOR("Naushir Patuck <naush@raspberrypi.com>");
1492 MODULE_AUTHOR("Andrea della Porta <andrea.porta@suse.com>");
1493 MODULE_DESCRIPTION("RP1 clock driver");
1494 MODULE_LICENSE("GPL");
1495