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Searched refs:RGMII (Results 1 – 25 of 68) sorted by relevance

123

/linux/drivers/net/dsa/lantiq/
H A DKconfig22 GSW120 4 port, 2 PHYs, RGMII & SGMII/2500Base-X
23 GSW125 4 port, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
24 GSW140 6 port, 4 PHYs, RGMII & SGMII/2500Base-X
25 GSW141 6 port, 4 PHYs, RGMII & SGMII
26 GSW145 6 port, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
27 GSW150 7 port, 5 PHYs, 1x GMII/RGMII, 1x RGMII
/linux/include/dt-bindings/phy/
H A Dphy-lan966x-serdes.h10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro
11 #define RGMII_MAX RGMII(2)
/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt5 special McMAL DMA controller, and sometimes an RGMII or ZMII
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
195 iv) RGMII node
203 - revision : as provided by the RGMII new version register if
H A Dcavium-pip.txt40 - rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
43 - tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
/linux/drivers/pinctrl/
H A Dpinctrl-ocelot.c1360 LAN9645X_P(4, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_…
1361 LAN9645X_P(5, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_…
1362 LAN9645X_P(6, GPIO, RGMII, TWI_SCL_M, NONE, NONE, NONE, SI_Sa, PHY_…
1363 LAN9645X_P(7, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, SI_Sa, PHY_…
1364 LAN9645X_P(8, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, NONE, PHY_…
1365 LAN9645X_P(9, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ1, UART, PHY_…
1366 LAN9645X_P(10, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ2, UART, PHY_…
1367 LAN9645X_P(11, GPIO, RGMII, TWI_SCL_M, MIIM, NONE, IRQ3, NONE, PHY_…
1368 LAN9645X_P(12, GPIO, RGMII, TWI_SCL_M, MIIM, PTP0, NONE, NONE, PHY_…
1369 LAN9645X_P(13, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP1, MACLED, NONE, PHY_…
[all …]
/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
457 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
464 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
H A Dfsp2.dts538 rgmii-device = <&RGMII>;
564 rgmii-device = <&RGMII>;
568 RGMII: rgmii@b0000600 { label
/linux/drivers/phy/microchip/
H A Dlan966x_serdes.c101 SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG |
107 SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG |
113 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
119 SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG |
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3-rev-a.dts15 /* The RGMII PHYs have a different MDIO address */
H A Ds32g274a-evb.dts57 /* KSZ 9031 on RGMII */
H A Dfsl-ls1028a-kontron-sl28-var4.dts6 * extends the base and provides one more port connected via RGMII.
H A Ds32g399a-rdb3.dts107 /* KSZ 9031 on RGMII */
H A Dfsl-ls1028a-kontron-sl28-var1.dts7 * port is connected via RGMII. This port is not TSN aware.
H A Ds32g274a-rdb2.dts91 /* KSZ 9031 on RGMII */
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxm-vega-s96.dts28 /* External PHY is in RGMII */
H A Dmeson-gxm-ugoos-am3.dts50 /* External PHY is in RGMII */
H A Dmeson-gxm-q200.dts53 /* External PHY is in RGMII */
H A Dmeson-gxl-s905d-p230.dts71 /* External PHY is in RGMII */
H A Dmeson-gxbb-odroidc2.dts293 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
295 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d3_eds.dts211 /* Reserved for reset signal to the RGMII connector. */
217 /* Reserved for an interrupt line from the RMII and RGMII connectors. */
/linux/arch/riscv/boot/dts/starfive/
H A Djh7100-starfive-visionfive-v1.dts26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
/linux/Documentation/networking/
H A Dphy.rst72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
95 Whenever possible, use the PHY side RGMII delay for these reasons:
119 required delays, as defined per the RGMII standard, several options may be
124 option to insert the expected 2ns RGMII delay.
129 Common problems with RGMII delay mismatch
132 When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, this
205 RGMII, and SGMII. See "PHY interface mode" below. For a full
540 RGMII v1.3:
543 RGMII v2.0:
/linux/drivers/net/pcs/
H A DKconfig36 RMII/RGMII, or can be set in pass-through mode for MII.
/linux/arch/mips/ralink/
H A DKconfig58 dual-core CPU, a 5-port 10/100/1000 switch/PHY and one RGMII.
/linux/Documentation/networking/dsa/
H A Dbcm_sf2.rst19 - several external MII/RevMII/GMII/RGMII interfaces
105 - turning off RGMII data processing logic when the link goes down

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