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Searched refs:RESET_DATA (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/reset/spacemit/
H A Dreset-spacemit-k3.c13 [RESET_MPMU_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
14 [RESET_MPMU_RIPC] = RESET_DATA(MPMU_RIPCCR, BIT(2), 0),
23 [RESET_APBC_UART0] = RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0),
24 [RESET_APBC_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
25 [RESET_APBC_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
26 [RESET_APBC_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
27 [RESET_APBC_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
28 [RESET_APBC_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
29 [RESET_APBC_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
30 [RESET_APBC_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
[all …]
H A Dreset-spacemit-k1.c13 [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
22 [RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0),
23 [RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
24 [RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
25 [RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)),
26 [RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)),
27 [RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)),
28 [RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)),
29 [RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)),
30 [RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)),
[all …]
H A Dreset-spacemit-common.h31 #define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ macro
/linux/arch/arm/mach-tegra/
H A Dreset-handler.S97 RESET_DATA(TF_PRESENT)
147 ldr r5, [r12, #RESET_DATA(TF_PRESENT)]
188 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
194 ldr r8, [r12, #RESET_DATA(MASK_LP1)]
199 ldr lr, [r12, #RESET_DATA(STARTUP_LP1)]
207 ldr r9, [r12, #RESET_DATA(MASK_LP2)]
210 ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
227 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
H A Dreset.h22 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) macro