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Searched refs:REG_SET_2 (Results 1 – 25 of 59) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.c367 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
375 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
380 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
385 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
391 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
396 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, in dce110_opp_set_clamping()
400 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, in dce110_opp_set_clamping()
404 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, in dce110_opp_set_clamping()
427 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping()
435 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping()
[all …]
H A Ddce_transform.c131 REG_SET_2(SCL_TAP_CONTROL, 0, in setup_scaling_configuration()
167 REG_SET_2(SCL_TAP_CONTROL, 0, in dce60_setup_scaling_configuration()
202 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, in program_overscan()
205 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, in program_overscan()
269 REG_SET_2(VIEWPORT_START, 0, in program_viewport()
273 REG_SET_2(VIEWPORT_SIZE, 0, in program_viewport()
353 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in program_scl_ratios_inits()
357 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in program_scl_ratios_inits()
377 REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0, in dce60_program_scl_ratios_inits()
382 REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0, in dce60_program_scl_ratios_inits()
[all …]
H A Ddce_ipp.c55 REG_SET_2(CUR_POSITION, 0, in dce_ipp_cursor_set_position()
59 REG_SET_2(CUR_HOT_SPOT, 0, in dce_ipp_cursor_set_position()
117 REG_SET_2(CUR_SIZE, 0, in dce_ipp_cursor_set_attributes()
147 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, in dce_ipp_program_prescale()
151 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, in dce_ipp_program_prescale()
155 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, in dce_ipp_program_prescale()
242 REG_SET_2(DEGAMMA_CONTROL, 0, in dce60_ipp_set_degamma()
H A Ddce_mem_input.c172 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in program_urgency_watermark()
187 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce60_program_urgency_watermark()
202 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce120_program_urgency_watermark()
206 REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0, in dce120_program_urgency_watermark()
575 REG_SET_2(GRPH_SWAP_CNTL, 0, in program_grph_pixel_format()
823 REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0, in program_sec_addr()
/linux/drivers/gpu/drm/amd/display/dc/opp/dcn20/
H A Ddcn20_opp.c93 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator()
98 REG_SET_2(DPG_OFFSET_SEGMENT, 0, in opp2_set_disp_pattern_generator()
172 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_set_disp_pattern_generator()
175 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_set_disp_pattern_generator()
178 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_set_disp_pattern_generator()
283 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator()
300 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_program_dpg_dimensions()
313 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_dpg_set_blank_color()
316 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_dpg_set_blank_color()
319 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_dpg_set_blank_color()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_dscl.c202 REG_SET_2(LB_DATA_FORMAT, 0, in dpp1_dscl_set_lb()
210 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb()
368 REG_SET_2(SCL_MODE, scl_mode, in dpp1_dscl_set_scl_filter()
533 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
539 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, in dpp1_dscl_set_manual_ratio_init()
545 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
554 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, in dpp1_dscl_set_manual_ratio_init()
561 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, in dpp1_dscl_set_manual_ratio_init()
570 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, in dpp1_dscl_set_manual_ratio_init()
590 REG_SET_2(RECOUT_START, 0, in dpp1_dscl_set_recout()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c615 REG_SET_2(BLANK_OFFSET_0, 0, in hubp1_program_deadline()
625 REG_SET_2(DST_AFTER_SCALER, 0, in hubp1_program_deadline()
650 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp1_program_deadline()
672 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp1_program_deadline()
717 REG_SET_2(PREFETCH_SETTINS, 0, in hubp1_setup_interdependent()
724 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp1_setup_interdependent()
734 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp1_setup_interdependent()
747 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp1_setup_interdependent()
795 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_system_aperture_settings()
835 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_context0_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c259 REG_SET_2(BLANK_OFFSET_0, 0, in hubp401_program_deadline()
269 REG_SET_2(DST_AFTER_SCALER, 0, in hubp401_program_deadline()
294 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp401_program_deadline()
316 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp401_program_deadline()
366 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp401_setup_interdependent()
373 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp401_setup_interdependent()
377 REG_SET_2(FLIP_PARAMETERS_0, 0, in hubp401_setup_interdependent()
390 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp401_setup_interdependent()
403 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp401_setup_interdependent()
655 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, in hubp401_set_viewport()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/
H A Ddcn21_hubbub.c157 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub21_program_urgent_watermarks()
202 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub21_program_urgent_watermarks()
247 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub21_program_urgent_watermarks()
292 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub21_program_urgent_watermarks()
353 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks()
370 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks()
388 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks()
405 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks()
423 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks()
440 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c215 REG_SET_2(PRE_DEGAM, 0, in dpp3_set_pre_degam()
241 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
360 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp3_cnv_setup()
365 REG_SET_2(PRE_DEALPHA, 0, in dpp3_cnv_setup()
368 REG_SET_2(PRE_REALPHA, 0, in dpp3_cnv_setup()
919 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp3_program_shaper_luta_settings()
922 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp3_program_shaper_luta_settings()
925 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp3_program_shaper_luta_settings()
929 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp3_program_shaper_luta_settings()
933 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp3_program_shaper_luta_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.c351 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
354 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
357 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
361 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
364 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
367 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
503 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
506 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
509 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
513 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0, in mpc32_program_shaper_lutb_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c637 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
640 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
643 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
647 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
651 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
655 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
787 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
790 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, in dpp20_program_shaper_lutb_settings()
793 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, in dpp20_program_shaper_lutb_settings()
797 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c209 REG_SET_2(DSCCIF_CONFIG0, 0, in dsc_write_to_registers()
265 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
269 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
276 REG_SET_2(DSCC_PPS_CONFIG5, 0, in dsc_write_to_registers()
285 REG_SET_2(DSCC_PPS_CONFIG7, 0, in dsc_write_to_registers()
289 REG_SET_2(DSCC_PPS_CONFIG8, 0, in dsc_write_to_registers()
293 REG_SET_2(DSCC_PPS_CONFIG9, 0, in dsc_write_to_registers()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_stream_encoder.c226 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
236 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
246 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
256 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
266 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
276 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
286 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
291 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_cm_common.c51 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_gamcor_xfer_func()
54 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_gamcor_xfer_func()
57 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_gamcor_xfer_func()
75 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_gamcor_xfer_func()
78 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_gamcor_xfer_func()
81 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_gamcor_xfer_func()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.c75 REG_SET_2(FORMAT_CONTROL, 0, in dpp401_dpp_setup()
190 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp401_dpp_setup()
195 REG_SET_2(PRE_DEALPHA, 0, in dpp401_dpp_setup()
198 REG_SET_2(PRE_REALPHA, 0, in dpp401_dpp_setup()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
H A Ddcn30_mpc.c495 REG_SET_2(SHAPER_RAMA_START_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
498 REG_SET_2(SHAPER_RAMA_START_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
501 REG_SET_2(SHAPER_RAMA_START_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
505 REG_SET_2(SHAPER_RAMA_END_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
508 REG_SET_2(SHAPER_RAMA_END_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
511 REG_SET_2(SHAPER_RAMA_END_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
644 REG_SET_2(SHAPER_RAMB_START_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
647 REG_SET_2(SHAPER_RAMB_START_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
650 REG_SET_2(SHAPER_RAMB_START_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
654 REG_SET_2(SHAPER_RAMB_END_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_lutb_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_cm_common.c56 REG_SET_2(cur_csc_reg, 0, in cm_helper_program_color_matrices()
93 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_xfer_func()
96 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_xfer_func()
99 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_xfer_func()
112 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_xfer_func()
118 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_xfer_func()
124 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_xfer_func()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.c193 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, in hubp21_set_viewport()
197 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, in hubp21_set_viewport()
202 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, in hubp21_set_viewport()
206 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, in hubp21_set_viewport()
211 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, in hubp21_set_viewport()
215 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, in hubp21_set_viewport()
219 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, in hubp21_set_viewport()
223 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, in hubp21_set_viewport()
246 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp21_set_vm_system_aperture_settings()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c76 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp2_set_vm_system_aperture_settings()
89 REG_SET_2(BLANK_OFFSET_0, 0, in hubp2_program_deadline()
99 REG_SET_2(DST_AFTER_SCALER, 0, in hubp2_program_deadline()
124 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp2_program_deadline()
146 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp2_program_deadline()
253 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp2_setup_interdependent()
260 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp2_setup_interdependent()
264 REG_SET_2(FLIP_PARAMETERS_0, 0, in hubp2_setup_interdependent()
277 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp2_setup_interdependent()
292 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp2_setup_interdependent()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_stream_encoder.c175 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
185 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
195 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
205 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c602 REG_SET_2(DSCCIF_CONFIG1, 0, in dsc_write_to_registers()
651 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
655 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
662 REG_SET_2(DSCC_PPS_CONFIG5, 0, in dsc_write_to_registers()
671 REG_SET_2(DSCC_PPS_CONFIG7, 0, in dsc_write_to_registers()
675 REG_SET_2(DSCC_PPS_CONFIG8, 0, in dsc_write_to_registers()
679 REG_SET_2(DSCC_PPS_CONFIG9, 0, in dsc_write_to_registers()
/linux/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
H A Ddcn31_hpo_dp_link_encoder.c406 REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL0, 0, in dcn31_hpo_dp_link_enc_set_throttled_vcp_size()
411 REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL1, 0, in dcn31_hpo_dp_link_enc_set_throttled_vcp_size()
416 REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL2, 0, in dcn31_hpo_dp_link_enc_set_throttled_vcp_size()
421 REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL3, 0, in dcn31_hpo_dp_link_enc_set_throttled_vcp_size()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.c87 REG_SET_2(OTG_VUPDATE_PARAM, 0, in optc1_program_global_sync()
102 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, in optc1_disable_stereo()
114 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, in optc1_setup_vertical_interrupt0()
883 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, in optc1_set_static_screen_control()
1116 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()
1128 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()

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