1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
4 */
5 #ifndef __QCOM_SCM_H
6 #define __QCOM_SCM_H
7
8 #include <linux/err.h>
9 #include <linux/types.h>
10 #include <linux/cpumask.h>
11
12 #include <dt-bindings/firmware/qcom,scm.h>
13
14 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
15 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
16 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
17 #define QCOM_SCM_HDCP_MAX_REQ_CNT 5
18
19 struct qcom_scm_hdcp_req {
20 u32 addr;
21 u32 val;
22 };
23
24 struct qcom_scm_vmperm {
25 int vmid;
26 int perm;
27 };
28
29 enum qcom_scm_ocmem_client {
30 QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
31 QCOM_SCM_OCMEM_GRAPHICS_ID,
32 QCOM_SCM_OCMEM_VIDEO_ID,
33 QCOM_SCM_OCMEM_LP_AUDIO_ID,
34 QCOM_SCM_OCMEM_SENSORS_ID,
35 QCOM_SCM_OCMEM_OTHER_OS_ID,
36 QCOM_SCM_OCMEM_DEBUG_ID,
37 };
38
39 enum qcom_scm_sec_dev_id {
40 QCOM_SCM_MDSS_DEV_ID = 1,
41 QCOM_SCM_OCMEM_DEV_ID = 5,
42 QCOM_SCM_PCIE0_DEV_ID = 11,
43 QCOM_SCM_PCIE1_DEV_ID = 12,
44 QCOM_SCM_GFX_DEV_ID = 18,
45 QCOM_SCM_UFS_DEV_ID = 19,
46 QCOM_SCM_ICE_DEV_ID = 20,
47 };
48
49 enum qcom_scm_ice_cipher {
50 QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
51 QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
52 QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
53 QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
54 };
55
56 #define QCOM_SCM_PERM_READ 0x4
57 #define QCOM_SCM_PERM_WRITE 0x2
58 #define QCOM_SCM_PERM_EXEC 0x1
59 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
60 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
61
62 bool qcom_scm_is_available(void);
63
64 int qcom_scm_set_cold_boot_addr(void *entry);
65 int qcom_scm_set_warm_boot_addr(void *entry);
66 void qcom_scm_cpu_power_down(u32 flags);
67 int qcom_scm_set_remote_state(u32 state, u32 id);
68
69 struct qcom_scm_pas_context {
70 struct device *dev;
71 u32 pas_id;
72 phys_addr_t mem_phys;
73 size_t mem_size;
74 void *ptr;
75 dma_addr_t phys;
76 ssize_t size;
77 bool use_tzmem;
78 };
79
80 struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev,
81 u32 pas_id,
82 phys_addr_t mem_phys,
83 size_t mem_size);
84 int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
85 struct qcom_scm_pas_context *ctx);
86 void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx);
87 int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size);
88 int qcom_scm_pas_auth_and_reset(u32 pas_id);
89 int qcom_scm_pas_shutdown(u32 pas_id);
90 bool qcom_scm_pas_supported(u32 pas_id);
91 struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx,
92 void *input_rt, size_t input_rt_size,
93 size_t *output_rt_size);
94
95 int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx);
96
97 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
98 int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
99
100 bool qcom_scm_restore_sec_cfg_available(void);
101 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
102 int qcom_scm_set_gpu_smmu_aperture(unsigned int context_bank);
103 bool qcom_scm_set_gpu_smmu_aperture_is_available(void);
104 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
105 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
106 int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
107 int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
108 u32 cp_nonpixel_start, u32 cp_nonpixel_size);
109 int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, u64 *src,
110 const struct qcom_scm_vmperm *newvm,
111 unsigned int dest_cnt);
112
113 bool qcom_scm_ocmem_lock_available(void);
114 int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
115 u32 mode);
116 int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size);
117
118 bool qcom_scm_ice_available(void);
119 int qcom_scm_ice_invalidate_key(u32 index);
120 int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
121 enum qcom_scm_ice_cipher cipher, u32 data_unit_size);
122 bool qcom_scm_has_wrapped_key_support(void);
123 int qcom_scm_derive_sw_secret(const u8 *eph_key, size_t eph_key_size,
124 u8 *sw_secret, size_t sw_secret_size);
125 int qcom_scm_generate_ice_key(u8 *lt_key, size_t lt_key_size);
126 int qcom_scm_prepare_ice_key(const u8 *lt_key, size_t lt_key_size,
127 u8 *eph_key, size_t eph_key_size);
128 int qcom_scm_import_ice_key(const u8 *raw_key, size_t raw_key_size,
129 u8 *lt_key, size_t lt_key_size);
130
131 bool qcom_scm_hdcp_available(void);
132 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
133
134 int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
135 int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
136
137 int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
138 u64 limit_node, u32 node_id, u64 version);
139 int qcom_scm_lmh_profile_change(u32 profile_id);
140 bool qcom_scm_lmh_dcvsh_available(void);
141
142 /*
143 * Request TZ to program set of access controlled registers necessary
144 * irrespective of any features
145 */
146 #define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0)
147 /*
148 * Request TZ to program BCL id to access controlled register when BCL is
149 * enabled
150 */
151 #define QCOM_SCM_GPU_BCL_EN_REQ BIT(1)
152 /*
153 * Request TZ to program set of access controlled register for CLX feature
154 * when enabled
155 */
156 #define QCOM_SCM_GPU_CLX_EN_REQ BIT(2)
157 /*
158 * Request TZ to program tsense ids to access controlled registers for reading
159 * gpu temperature sensors
160 */
161 #define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3)
162
163 int qcom_scm_gpu_init_regs(u32 gpu_req);
164
165 int qcom_scm_shm_bridge_create(u64 pfn_and_ns_perm_flags,
166 u64 ipfn_and_s_perm_flags, u64 size_and_flags,
167 u64 ns_vmids, u64 *handle);
168 int qcom_scm_shm_bridge_delete(u64 handle);
169
170 #ifdef CONFIG_QCOM_QSEECOM
171
172 int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id);
173 int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size,
174 void *rsp, size_t rsp_size);
175
176 #else /* CONFIG_QCOM_QSEECOM */
177
qcom_scm_qseecom_app_get_id(const char * app_name,u32 * app_id)178 static inline int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id)
179 {
180 return -EINVAL;
181 }
182
qcom_scm_qseecom_app_send(u32 app_id,void * req,size_t req_size,void * rsp,size_t rsp_size)183 static inline int qcom_scm_qseecom_app_send(u32 app_id,
184 void *req, size_t req_size,
185 void *rsp, size_t rsp_size)
186 {
187 return -EINVAL;
188 }
189
190 #endif /* CONFIG_QCOM_QSEECOM */
191
192 int qcom_scm_qtee_invoke_smc(phys_addr_t inbuf, size_t inbuf_size,
193 phys_addr_t outbuf, size_t outbuf_size,
194 u64 *result, u64 *response_type);
195 int qcom_scm_qtee_callback_response(phys_addr_t buf, size_t buf_size,
196 u64 *result, u64 *response_type);
197
198 #endif
199