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Searched refs:Phase (Results 1 – 22 of 22) sorted by relevance

/linux/Documentation/ABI/testing/
H A Dsysfs-driver-zynqmp-fpga57 Phase 0 = 000
58 Phase 1 = 001
59 Phase 2 = 011
60 Phase 3 = 010
61 Phase 4 = 110
62 Phase 5 = 111
63 Phase 6 = 101
64 Phase 7 = 100
H A Dsysfs-bus-iio-isl2950129 Phase data has to be collected when temperature and
H A Dsysfs-bus-iio842 Phase in radians of one frequency/clock output Y
/linux/Documentation/iio/
H A Dade9000.rst178 - Phase A: voltage and current (IA + VA)
179 - Phase B: voltage and current (IB + VB)
180 - Phase C: voltage and current (IC + VC)
187 Enable waveform capture for Phase A:
228 - Phase A voltage = in_voltage0_raw * in_voltage0_scale = 0.3769 V
239 - Phase A active power = in_power0_active_raw * in_power0_scale = 1.386 W
/linux/drivers/iio/frequency/
H A DKconfig6 # Phase-Locked Loop (PLL) frequency synthesizers
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
/linux/Documentation/driver-api/
H A Ddpll.rst10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
176 Phase offset measurement and adjustment
230 Phase adjust (also min and max) values are integers, but measured phase
235 Phase offset monitor
238 Phase offset measurement is typically performed against the current active
239 source. However, some DPLL (Digital Phase-Locked Loop) devices may offer
/linux/Documentation/hwmon/
H A Dtps40422.rst20 This driver supports TI TPS40422 Dual-Output or Two-Phase Synchronous Buck
H A Dmp2888.rst25 - Programmable Multi-Phase up to 10 Phases.
/linux/Documentation/gpu/nova/core/
H A Ddevinit.rst28 3. Clock and PLL (Phase-Locked Loop) configuration
/linux/drivers/staging/iio/Documentation/
H A Dsysfs-bus-iio-dds38 allows for pin controlled PSK Phase Shift Keying
/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg1804 * SCSI Phase
2747 * 960MHz Phase-Locked Loop Control 0
2774 * 960MHz Phase-Locked Loop Control 1
2815 * 960-MHz Phase-Locked Loop Test Count
2825 * 400-MHz Phase-Locked Loop Control 0
2851 * 400-MHz Phase-Locked Loop Control 1
2873 * 400-MHz Phase-Locked Loop Test Count
/linux/Documentation/input/devices/
H A Diforce-protocol.rst172 04 Phase. Val 00 = 0 deg, Val 40 = 90 degs.
/linux/drivers/scsi/pcmcia/
H A Dsym53c500_cs.c201 enum Phase { enum
/linux/Documentation/sound/cards/
H A Dcmipci.rst180 IEC958 In Phase Inverse
/linux/drivers/zorro/
H A Dzorro.ids414 2140 Phase 5
/linux/sound/pci/
H A DKconfig648 TerraTec EWX 24/96, EWS 88MT/D, DMX 6Fire, Phase 88;
667 7.1 Space/Universe, Phase 22/28; Onkyo SE-90PCI, SE-200PCI;
/linux/Documentation/networking/dsa/
H A Dsja1105.rst161 # Phase-align the base time to the start of the next second.
/linux/Documentation/sound/
H A Dalsa-configuration.rst1189 * TerraTec Phase 88
1232 * TerraTec Phase 22
1233 * TerraTec Phase 28
/linux/Documentation/filesystems/xfs/
H A Dxfs-online-fsck-design.rst4835 - Phase 1 checks that the provided path maps to an XFS filesystem and detect
4838 - Phase 2 scrubs groups (g) and (h) in parallel using a threaded workqueue.
4840 - Phase 3 scans inodes in parallel.
4843 - Phase 4 repairs everything in groups (i) through (d) so that phases 5 and 6
4846 - Phase 5 starts by checking groups (b) and (c) in parallel before moving on
4849 - Phase 6 depends on groups (i) through (b) to find file data blocks to verify,
4852 - Phase 7 checks group (a), having validated everything else.
4924 Phase 4 is responsible for scheduling a lot of repair work in as quick a
/linux/drivers/regulator/
H A DKconfig1476 Buck converters including Dual-Phase Buck converter, Buck-Boost
1628 The TPS51632 is 3-2-1 Phase D-Cap+ Step Down Driverless Controller
/linux/Documentation/scsi/
H A DChangeLog.sym53c8xx552 - Disable by default Phase Mismatch handling from SCRIPTS, since
H A DChangeLog.lpfc325 * Phase II of GFP_ATOMIC effort. Replaced iocb_mem_pool and