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Searched refs:PUNIT_REG_DSPSSPM (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Dvlv_iosf_sb_reg.h37 #define PUNIT_REG_DSPSSPM 0x36 macro
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_power_well.c1699 state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1712 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1733 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in chv_set_pipe_power_well()
1739 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl); in chv_set_pipe_power_well()
1741 ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), in chv_set_pipe_power_well()
1748 vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM)); in chv_set_pipe_power_well()
H A Dintel_cdclk.c617 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
699 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
702 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); in vlv_set_cdclk()
704 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), in vlv_set_cdclk()
784 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
787 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); in chv_set_cdclk()
789 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), in chv_set_cdclk()