1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020 - 2025 Intel Corporation 4 */ 5 6 #ifndef IPU7_ISYS_CSI2_REG_H 7 #define IPU7_ISYS_CSI2_REG_H 8 9 /* IS main regs base */ 10 #define IS_MAIN_BASE 0x240000 11 #define IS_MAIN_S2B_BASE (IS_MAIN_BASE + 0x22000) 12 #define IS_MAIN_B2O_BASE (IS_MAIN_BASE + 0x26000) 13 #define IS_MAIN_ISD_M0_BASE (IS_MAIN_BASE + 0x2b000) 14 #define IS_MAIN_ISD_M1_BASE (IS_MAIN_BASE + 0x2b100) 15 #define IS_MAIN_ISD_INT_BASE (IS_MAIN_BASE + 0x2b200) 16 #define IS_MAIN_GDA_BASE (IS_MAIN_BASE + 0x32000) 17 #define IS_MAIN_GPREGS_MAIN_BASE (IS_MAIN_BASE + 0x32500) 18 #define IS_MAIN_IRQ_CTRL_BASE (IS_MAIN_BASE + 0x32700) 19 #define IS_MAIN_PWM_CTRL_BASE (IS_MAIN_BASE + 0x32b00) 20 21 #define S2B_IRQ_COMMON_0_CTL_STATUS (IS_MAIN_S2B_BASE + 0x1c) 22 #define S2B_IRQ_COMMON_0_CTL_CLEAR (IS_MAIN_S2B_BASE + 0x20) 23 #define S2B_IRQ_COMMON_0_CTL_ENABLE (IS_MAIN_S2B_BASE + 0x24) 24 #define S2B_IID_IRQ_CTL_STATUS(iid) (IS_MAIN_S2B_BASE + 0x94 + \ 25 0x100 * (iid)) 26 27 #define B2O_IRQ_COMMON_0_CTL_STATUS (IS_MAIN_B2O_BASE + 0x30) 28 #define B2O_IRQ_COMMON_0_CTL_CLEAR (IS_MAIN_B2O_BASE + 0x34) 29 #define B2O_IRQ_COMMON_0_CTL_ENABLE (IS_MAIN_B2O_BASE + 0x38) 30 #define B2O_IID_IRQ_CTL_STATUS(oid) (IS_MAIN_B2O_BASE + 0x3dc + \ 31 0x200 * (oid)) 32 33 #define ISD_M0_IRQ_CTL_STATUS (IS_MAIN_ISD_M0_BASE + 0x1c) 34 #define ISD_M0_IRQ_CTL_CLEAR (IS_MAIN_ISD_M0_BASE + 0x20) 35 #define ISD_M0_IRQ_CTL_ENABLE (IS_MAIN_ISD_M0_BASE + 0x24) 36 37 #define ISD_M1_IRQ_CTL_STATUS (IS_MAIN_ISD_M1_BASE + 0x1c) 38 #define ISD_M1_IRQ_CTL_CLEAR (IS_MAIN_ISD_M1_BASE + 0x20) 39 #define ISD_M1_IRQ_CTL_ENABLE (IS_MAIN_ISD_M1_BASE + 0x24) 40 41 #define ISD_INT_IRQ_CTL_STATUS (IS_MAIN_ISD_INT_BASE + 0x1c) 42 #define ISD_INT_IRQ_CTL_CLEAR (IS_MAIN_ISD_INT_BASE + 0x20) 43 #define ISD_INT_IRQ_CTL_ENABLE (IS_MAIN_ISD_INT_BASE + 0x24) 44 45 #define GDA_IRQ_CTL_STATUS (IS_MAIN_GDA_BASE + 0x1c) 46 #define GDA_IRQ_CTL_CLEAR (IS_MAIN_GDA_BASE + 0x20) 47 #define GDA_IRQ_CTL_ENABLE (IS_MAIN_GDA_BASE + 0x24) 48 49 #define IS_MAIN_IRQ_CTL_EDGE IS_MAIN_IRQ_CTRL_BASE 50 #define IS_MAIN_IRQ_CTL_MASK (IS_MAIN_IRQ_CTRL_BASE + 0x4) 51 #define IS_MAIN_IRQ_CTL_STATUS (IS_MAIN_IRQ_CTRL_BASE + 0x8) 52 #define IS_MAIN_IRQ_CTL_CLEAR (IS_MAIN_IRQ_CTRL_BASE + 0xc) 53 #define IS_MAIN_IRQ_CTL_ENABLE (IS_MAIN_IRQ_CTRL_BASE + 0x10) 54 #define IS_MAIN_IRQ_CTL_LEVEL_NOT_PULSE (IS_MAIN_IRQ_CTRL_BASE + 0x14) 55 56 /* IS IO regs base */ 57 #define IS_PHY_NUM 4U 58 #define IS_IO_BASE 0x280000 59 60 /* dwc csi cdphy registers */ 61 #define IS_IO_CDPHY_BASE(i) (IS_IO_BASE + 0x10000 * (i)) 62 #define PPI_STARTUP_RW_COMMON_DPHY_0 0x1800 63 #define PPI_STARTUP_RW_COMMON_DPHY_1 0x1802 64 #define PPI_STARTUP_RW_COMMON_DPHY_2 0x1804 65 #define PPI_STARTUP_RW_COMMON_DPHY_3 0x1806 66 #define PPI_STARTUP_RW_COMMON_DPHY_4 0x1808 67 #define PPI_STARTUP_RW_COMMON_DPHY_5 0x180a 68 #define PPI_STARTUP_RW_COMMON_DPHY_6 0x180c 69 #define PPI_STARTUP_RW_COMMON_DPHY_7 0x180e 70 #define PPI_STARTUP_RW_COMMON_DPHY_8 0x1810 71 #define PPI_STARTUP_RW_COMMON_DPHY_9 0x1812 72 #define PPI_STARTUP_RW_COMMON_DPHY_A 0x1814 73 #define PPI_STARTUP_RW_COMMON_DPHY_10 0x1820 74 #define PPI_STARTUP_RW_COMMON_STARTUP_1_1 0x1822 75 #define PPI_STARTUP_RW_COMMON_STARTUP_1_2 0x1824 76 #define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_0 0x1840 77 #define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_1 0x1842 78 #define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_2 0x1844 79 #define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_3 0x1846 80 #define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_4 0x1848 81 #define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_5 0x184a 82 #define PPI_CALIBCTRL_RW_COMMON_BG_0 0x184c 83 #define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_7 0x184e 84 #define PPI_CALIBCTRL_RW_ADC_CFG_0 0x1850 85 #define PPI_CALIBCTRL_RW_ADC_CFG_1 0x1852 86 #define PPI_CALIBCTRL_R_ADC_DEBUG 0x1854 87 #define PPI_RW_LPDCOCAL_TOP_OVERRIDE 0x1c00 88 #define PPI_RW_LPDCOCAL_TIMEBASE 0x1c02 89 #define PPI_RW_LPDCOCAL_NREF 0x1c04 90 #define PPI_RW_LPDCOCAL_NREF_RANGE 0x1c06 91 #define PPI_RW_LPDCOCAL_NREF_TRIGGER_MAN 0x1c08 92 #define PPI_RW_LPDCOCAL_TWAIT_CONFIG 0x1c0a 93 #define PPI_RW_LPDCOCAL_VT_CONFIG 0x1c0c 94 #define PPI_R_LPDCOCAL_DEBUG_RB 0x1c0e 95 #define PPI_RW_LPDCOCAL_COARSE_CFG 0x1c10 96 #define PPI_R_LPDCOCAL_DEBUG_COARSE_RB 0x1c12 97 #define PPI_R_LPDCOCAL_DEBUG_COARSE_MEAS_0_RB 0x1c14 98 #define PPI_R_LPDCOCAL_DEBUG_COARSE_MEAS_1_RB 0x1c16 99 #define PPI_R_LPDCOCAL_DEBUG_COARSE_FWORD_RB 0x1c18 100 #define PPI_R_LPDCOCAL_DEBUG_MEASURE_CURR_ERROR 0x1c1a 101 #define PPI_R_LPDCOCAL_DEBUG_MEASURE_LAST_ERROR 0x1c1c 102 #define PPI_R_LPDCOCAL_DEBUG_VT 0x1c1e 103 #define PPI_RW_LB_TIMEBASE_CONFIG 0x1c20 104 #define PPI_RW_LB_STARTCMU_CONFIG 0x1c22 105 #define PPI_R_LBPULSE_COUNTER_RB 0x1c24 106 #define PPI_R_LB_START_CMU_RB 0x1c26 107 #define PPI_RW_LB_DPHY_BURST_START 0x1c28 108 #define PPI_RW_LB_CPHY_BURST_START 0x1c2a 109 #define PPI_RW_DDLCAL_CFG_0 0x1c40 110 #define PPI_RW_DDLCAL_CFG_1 0x1c42 111 #define PPI_RW_DDLCAL_CFG_2 0x1c44 112 #define PPI_RW_DDLCAL_CFG_3 0x1c46 113 #define PPI_RW_DDLCAL_CFG_4 0x1c48 114 #define PPI_RW_DDLCAL_CFG_5 0x1c4a 115 #define PPI_RW_DDLCAL_CFG_6 0x1c4c 116 #define PPI_RW_DDLCAL_CFG_7 0x1c4e 117 #define PPI_R_DDLCAL_DEBUG_0 0x1c50 118 #define PPI_R_DDLCAL_DEBUG_1 0x1c52 119 #define PPI_RW_PARITY_TEST 0x1c60 120 #define PPI_RW_STARTUP_OVR_0 0x1c62 121 #define PPI_RW_STARTUP_STATE_OVR_1 0x1c64 122 #define PPI_RW_DTB_SELECTOR 0x1c66 123 #define PPI_RW_DPHY_CLK_SPARE 0x1c6a 124 #define PPI_RW_COMMON_CFG 0x1c6c 125 #define PPI_RW_TERMCAL_CFG_0 0x1c80 126 #define PPI_R_TERMCAL_DEBUG_0 0x1c82 127 #define PPI_RW_TERMCAL_CTRL_0 0x1c84 128 #define PPI_RW_OFFSETCAL_CFG_0 0x1ca0 129 #define PPI_R_OFFSETCAL_DEBUG_LANE0 0x1ca2 130 #define PPI_R_OFFSETCAL_DEBUG_LANE1 0x1ca4 131 #define PPI_R_OFFSETCAL_DEBUG_LANE2 0x1ca6 132 #define PPI_R_OFFSETCAL_DEBUG_LANE3 0x1ca8 133 #define PPI_R_OFFSETCAL_DEBUG_LANE4 0x1caa 134 #define PPI_RW_HSDCOCAL_CFG_O 0x1d00 135 #define PPI_RW_HSDCOCAL_CFG_1 0x1d02 136 #define PPI_RW_HSDCOCAL_CFG_2 0x1d04 137 #define PPI_RW_HSDCOCAL_CFG_3 0x1d06 138 #define PPI_RW_HSDCOCAL_CFG_4 0x1d08 139 #define PPI_RW_HSDCOCAL_CFG_5 0x1d0a 140 #define PPI_RW_HSDCOCAL_CFG_6 0x1d0c 141 #define PPI_RW_HSDCOCAL_CFG_7 0x1d0e 142 #define PPI_RW_HSDCOCAL_CFG_8 0x1d10 143 #define PPI_R_HSDCOCAL_DEBUG_RB 0x1d12 144 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_0 0x2000 145 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_1 0x2002 146 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_2 0x2004 147 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_3 0x2006 148 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_4 0x2008 149 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_5 0x200a 150 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_6 0x200c 151 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_7 0x200e 152 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE0_OVR_0_8 0x2010 153 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_9 0x2012 154 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_10 0x2014 155 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_11 0x2016 156 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_12 0x2018 157 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_13 0x201a 158 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_14 0x201c 159 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE0_OVR_0_15 0x201e 160 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_0 0x2020 161 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_1 0x2022 162 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_2 0x2024 163 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_3 0x2026 164 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_4 0x2028 165 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_5 0x202a 166 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_6 0x202c 167 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_7 0x202e 168 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_8 0x2030 169 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_1_9 0x2032 170 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_10 0x2034 171 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_11 0x2036 172 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_12 0x2038 173 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_13 0x203a 174 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_14 0x203c 175 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_1_15 0x203e 176 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_0 0x2040 177 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_1 0x2042 178 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2 0x2044 179 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_3 0x2046 180 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_4 0x2048 181 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_5 0x204a 182 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_6 0x204c 183 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_7 0x204e 184 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_8 0x2050 185 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9 0x2052 186 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_10 0x2054 187 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_11 0x2056 188 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_12 0x2058 189 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_13 0x205a 190 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_14 0x205c 191 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15 0x205e 192 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_0 0x2060 193 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_1 0x2062 194 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_2 0x2064 195 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_3 0x2066 196 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_4 0x2068 197 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_5 0x206a 198 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_6 0x206c 199 #define CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_3_7 0x206e 200 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_8 0x2070 201 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_9 0x2072 202 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_10 0x2074 203 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_11 0x2076 204 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_12 0x2078 205 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_13 0x207a 206 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_14 0x207c 207 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_3_15 0x207e 208 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_0 0x2080 209 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_1 0x2082 210 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_2 0x2084 211 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_3 0x2086 212 #define CORE_DIG_IOCTRL_R_AFE_LANE0_CTRL_4_4 0x2088 213 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_0 0x20a0 214 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_1 0x20a2 215 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_2 0x20a4 216 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE0_OVR_5_3 0x20a6 217 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE0_OVR_5_4 0x20a8 218 #define CORE_DIG_RW_TRIO0_0 0x2100 219 #define CORE_DIG_RW_TRIO0_1 0x2102 220 #define CORE_DIG_RW_TRIO0_2 0x2104 221 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_0 0x2400 222 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_1 0x2402 223 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_2 0x2404 224 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_3 0x2406 225 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_4 0x2408 226 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_5 0x240a 227 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_6 0x240c 228 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_7 0x240e 229 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE1_OVR_0_8 0x2410 230 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_9 0x2412 231 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_10 0x2414 232 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_11 0x2416 233 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_12 0x2418 234 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_13 0x241a 235 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_14 0x241c 236 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE1_OVR_0_15 0x241e 237 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_0 0x2420 238 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_1 0x2422 239 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_2 0x2424 240 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_3 0x2426 241 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_4 0x2428 242 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_5 0x242a 243 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_6 0x242c 244 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_7 0x242e 245 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_8 0x2430 246 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_1_9 0x2432 247 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_10 0x2434 248 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_11 0x2436 249 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_12 0x2438 250 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_13 0x243a 251 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_14 0x243c 252 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_1_15 0x243e 253 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_0 0x2440 254 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_1 0x2442 255 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_2 0x2444 256 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_3 0x2446 257 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_4 0x2448 258 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_5 0x244a 259 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_6 0x244c 260 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_7 0x244e 261 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_8 0x2450 262 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9 0x2452 263 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_10 0x2454 264 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_11 0x2456 265 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_12 0x2458 266 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_13 0x245a 267 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_14 0x245c 268 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15 0x245e 269 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_0 0x2460 270 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_1 0x2462 271 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_2 0x2464 272 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_3 0x2466 273 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_4 0x2468 274 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_5 0x246a 275 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_6 0x246c 276 #define CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_3_7 0x246e 277 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_8 0x2470 278 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_9 0x2472 279 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_10 0x2474 280 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_11 0x2476 281 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_12 0x2478 282 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_13 0x247a 283 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_14 0x247c 284 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_3_15 0x247e 285 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_0 0x2480 286 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_1 0x2482 287 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_2 0x2484 288 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_3 0x2486 289 #define CORE_DIG_IOCTRL_R_AFE_LANE1_CTRL_4_4 0x2488 290 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_0 0x24a0 291 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_1 0x24a2 292 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_2 0x24a4 293 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE1_OVR_5_3 0x24a6 294 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE1_OVR_5_4 0x24a8 295 #define CORE_DIG_RW_TRIO1_0 0x2500 296 #define CORE_DIG_RW_TRIO1_1 0x2502 297 #define CORE_DIG_RW_TRIO1_2 0x2504 298 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_0 0x2800 299 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_1 0x2802 300 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_2 0x2804 301 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_3 0x2806 302 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_4 0x2808 303 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_5 0x280a 304 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_6 0x280c 305 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_7 0x280e 306 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE2_OVR_0_8 0x2810 307 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_9 0x2812 308 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_10 0x2814 309 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_11 0x2816 310 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_12 0x2818 311 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_13 0x281a 312 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_14 0x281c 313 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE2_OVR_0_15 0x281e 314 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_0 0x2820 315 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_1 0x2822 316 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_2 0x2824 317 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_3 0x2826 318 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_4 0x2828 319 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_5 0x282a 320 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_6 0x282c 321 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_7 0x282e 322 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_8 0x2830 323 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_1_9 0x2832 324 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_10 0x2834 325 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_11 0x2836 326 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_12 0x2838 327 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_13 0x283a 328 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_14 0x283c 329 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_1_15 0x283e 330 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_0 0x2840 331 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_1 0x2842 332 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_2 0x2844 333 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_3 0x2846 334 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_4 0x2848 335 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_5 0x284a 336 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_6 0x284c 337 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_7 0x284e 338 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_8 0x2850 339 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9 0x2852 340 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_10 0x2854 341 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_11 0x2856 342 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_12 0x2858 343 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_13 0x285a 344 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_14 0x285c 345 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15 0x285e 346 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_0 0x2860 347 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_1 0x2862 348 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_2 0x2864 349 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_3 0x2866 350 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_4 0x2868 351 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_5 0x286a 352 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_6 0x286c 353 #define CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_3_7 0x286e 354 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_8 0x2870 355 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_9 0x2872 356 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_10 0x2874 357 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_11 0x2876 358 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_12 0x2878 359 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_13 0x287a 360 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_14 0x287c 361 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_3_15 0x287e 362 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_0 0x2880 363 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_1 0x2882 364 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_2 0x2884 365 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_3 0x2886 366 #define CORE_DIG_IOCTRL_R_AFE_LANE2_CTRL_4_4 0x2888 367 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_0 0x28a0 368 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_1 0x28a2 369 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_2 0x28a4 370 #define CORE_DIG_IOCTRL_RW_CPHY_PPI_LANE2_OVR_5_3 0x28a6 371 #define CORE_DIG_IOCTRL_R_CPHY_PPI_LANE2_OVR_5_4 0x28a8 372 #define CORE_DIG_RW_TRIO2_0 0x2900 373 #define CORE_DIG_RW_TRIO2_1 0x2902 374 #define CORE_DIG_RW_TRIO2_2 0x2904 375 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_0 0x2c00 376 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_1 0x2c02 377 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_2 0x2c04 378 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_3 0x2c06 379 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_4 0x2c08 380 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_5 0x2c0a 381 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_6 0x2c0c 382 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_7 0x2c0e 383 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_LANE3_OVR_0_8 0x2c10 384 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_9 0x2c12 385 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_10 0x2c14 386 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_11 0x2c16 387 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_12 0x2c18 388 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_13 0x2c1a 389 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_14 0x2c1c 390 #define CORE_DIG_IOCTRL_R_DPHY_PPI_LANE3_OVR_0_15 0x2c1e 391 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_0 0x2c40 392 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_1 0x2c42 393 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_2 0x2c44 394 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_3 0x2c46 395 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_4 0x2c48 396 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_5 0x2c4a 397 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_6 0x2c4c 398 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_7 0x2c4e 399 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_8 0x2c50 400 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_9 0x2c52 401 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_10 0x2c54 402 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_11 0x2c56 403 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_12 0x2c58 404 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_13 0x2c5a 405 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_14 0x2c5c 406 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_15 0x2c5e 407 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_0 0x2c60 408 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_1 0x2c62 409 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_2 0x2c64 410 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_3 0x2c66 411 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_4 0x2c68 412 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_5 0x2c6a 413 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_6 0x2c6c 414 #define CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_3_7 0x2c6e 415 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_8 0x2c70 416 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_9 0x2c72 417 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_10 0x2c74 418 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_11 0x2c76 419 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_12 0x2c78 420 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_13 0x2c7a 421 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_14 0x2c7c 422 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_3_15 0x2c7e 423 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_0 0x2c80 424 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_1 0x2c82 425 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_2 0x2c84 426 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_3 0x2c86 427 #define CORE_DIG_IOCTRL_R_AFE_LANE3_CTRL_4_4 0x2c88 428 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_0 0x3040 429 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_1 0x3042 430 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_2 0x3044 431 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_3 0x3046 432 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_4 0x3048 433 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_5 0x304a 434 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_6 0x304c 435 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_7 0x304e 436 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_8 0x3050 437 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_9 0x3052 438 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_10 0x3054 439 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_11 0x3056 440 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_12 0x3058 441 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_13 0x305a 442 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_14 0x305c 443 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_15 0x305e 444 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_0 0x3060 445 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_1 0x3062 446 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_2 0x3064 447 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_3 0x3066 448 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_4 0x3068 449 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_5 0x306a 450 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_6 0x306c 451 #define CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_3_7 0x306e 452 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_8 0x3070 453 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_9 0x3072 454 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_10 0x3074 455 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_11 0x3076 456 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_12 0x3078 457 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_13 0x307a 458 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_14 0x307c 459 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_3_15 0x307e 460 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_0 0x3080 461 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_1 0x3082 462 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_2 0x3084 463 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_3 0x3086 464 #define CORE_DIG_IOCTRL_R_AFE_LANE4_CTRL_4_4 0x3088 465 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_0 0x3400 466 #define CORE_DIG_IOCTRL_RW_DPHY_PPI_CLK_OVR_0_1 0x3402 467 #define CORE_DIG_IOCTRL_R_DPHY_PPI_CLK_OVR_0_2 0x3404 468 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_0 0x3800 469 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_1 0x3802 470 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_2 0x3804 471 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_3 0x3806 472 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_4 0x3808 473 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_5 0x380a 474 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_6 0x380c 475 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_7 0x380e 476 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_8 0x3810 477 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_9 0x3812 478 #define CORE_DIG_IOCTRL_RW_COMMON_PPI_OVR_0_10 0x3814 479 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_11 0x3816 480 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_12 0x3818 481 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_13 0x381a 482 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_14 0x381c 483 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_0_15 0x381e 484 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_0 0x3820 485 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_1 0x3822 486 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_2 0x3824 487 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_3 0x3826 488 #define CORE_DIG_IOCTRL_R_COMMON_PPI_OVR_1_4 0x3828 489 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0 0x3840 490 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1 0x3842 491 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_2 0x3844 492 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3 0x3846 493 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_4 0x3848 494 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5 0x384a 495 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6 0x384c 496 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7 0x384e 497 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_8 0x3850 498 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_9 0x3852 499 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_10 0x3854 500 #define CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_11 0x3856 501 #define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_12 0x3858 502 #define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_13 0x385a 503 #define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_14 0x385c 504 #define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_2_15 0x385e 505 #define CORE_DIG_IOCTRL_R_AFE_CB_CTRL_3_0 0x3860 506 #define CORE_DIG_RW_COMMON_0 0x3880 507 #define CORE_DIG_RW_COMMON_1 0x3882 508 #define CORE_DIG_RW_COMMON_2 0x3884 509 #define CORE_DIG_RW_COMMON_3 0x3886 510 #define CORE_DIG_RW_COMMON_4 0x3888 511 #define CORE_DIG_RW_COMMON_5 0x388a 512 #define CORE_DIG_RW_COMMON_6 0x388c 513 #define CORE_DIG_RW_COMMON_7 0x388e 514 #define CORE_DIG_RW_COMMON_8 0x3890 515 #define CORE_DIG_RW_COMMON_9 0x3892 516 #define CORE_DIG_RW_COMMON_10 0x3894 517 #define CORE_DIG_RW_COMMON_11 0x3896 518 #define CORE_DIG_RW_COMMON_12 0x3898 519 #define CORE_DIG_RW_COMMON_13 0x389a 520 #define CORE_DIG_RW_COMMON_14 0x389c 521 #define CORE_DIG_RW_COMMON_15 0x389e 522 #define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0 0x39e0 523 #define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_1 0x39e2 524 #define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2 0x39e4 525 #define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_3 0x39e6 526 #define CORE_DIG_COMMON_RW_DESKEW_FINE_MEM 0x3fe0 527 #define CORE_DIG_COMMON_R_DESKEW_FINE_MEM 0x3fe2 528 #define PPI_RW_DPHY_LANE0_LBERT_0 0x4000 529 #define PPI_RW_DPHY_LANE0_LBERT_1 0x4002 530 #define PPI_R_DPHY_LANE0_LBERT_0 0x4004 531 #define PPI_R_DPHY_LANE0_LBERT_1 0x4006 532 #define PPI_RW_DPHY_LANE0_SPARE 0x4008 533 #define PPI_RW_DPHY_LANE1_LBERT_0 0x4400 534 #define PPI_RW_DPHY_LANE1_LBERT_1 0x4402 535 #define PPI_R_DPHY_LANE1_LBERT_0 0x4404 536 #define PPI_R_DPHY_LANE1_LBERT_1 0x4406 537 #define PPI_RW_DPHY_LANE1_SPARE 0x4408 538 #define PPI_RW_DPHY_LANE2_LBERT_0 0x4800 539 #define PPI_RW_DPHY_LANE2_LBERT_1 0x4802 540 #define PPI_R_DPHY_LANE2_LBERT_0 0x4804 541 #define PPI_R_DPHY_LANE2_LBERT_1 0x4806 542 #define PPI_RW_DPHY_LANE2_SPARE 0x4808 543 #define PPI_RW_DPHY_LANE3_LBERT_0 0x4c00 544 #define PPI_RW_DPHY_LANE3_LBERT_1 0x4c02 545 #define PPI_R_DPHY_LANE3_LBERT_0 0x4c04 546 #define PPI_R_DPHY_LANE3_LBERT_1 0x4c06 547 #define PPI_RW_DPHY_LANE3_SPARE 0x4c08 548 #define CORE_DIG_DLANE_0_RW_CFG_0 0x6000 549 #define CORE_DIG_DLANE_0_RW_CFG_1 0x6002 550 #define CORE_DIG_DLANE_0_RW_CFG_2 0x6004 551 #define CORE_DIG_DLANE_0_RW_LP_0 0x6080 552 #define CORE_DIG_DLANE_0_RW_LP_1 0x6082 553 #define CORE_DIG_DLANE_0_RW_LP_2 0x6084 554 #define CORE_DIG_DLANE_0_R_LP_0 0x60a0 555 #define CORE_DIG_DLANE_0_R_LP_1 0x60a2 556 #define CORE_DIG_DLANE_0_R_HS_TX_0 0x60e0 557 #define CORE_DIG_DLANE_0_RW_HS_RX_0 0x6100 558 #define CORE_DIG_DLANE_0_RW_HS_RX_1 0x6102 559 #define CORE_DIG_DLANE_0_RW_HS_RX_2 0x6104 560 #define CORE_DIG_DLANE_0_RW_HS_RX_3 0x6106 561 #define CORE_DIG_DLANE_0_RW_HS_RX_4 0x6108 562 #define CORE_DIG_DLANE_0_RW_HS_RX_5 0x610a 563 #define CORE_DIG_DLANE_0_RW_HS_RX_6 0x610c 564 #define CORE_DIG_DLANE_0_RW_HS_RX_7 0x610e 565 #define CORE_DIG_DLANE_0_RW_HS_RX_8 0x6110 566 #define CORE_DIG_DLANE_0_RW_HS_RX_9 0x6112 567 #define CORE_DIG_DLANE_0_R_HS_RX_0 0x6120 568 #define CORE_DIG_DLANE_0_R_HS_RX_1 0x6122 569 #define CORE_DIG_DLANE_0_R_HS_RX_2 0x6124 570 #define CORE_DIG_DLANE_0_R_HS_RX_3 0x6126 571 #define CORE_DIG_DLANE_0_R_HS_RX_4 0x6128 572 #define CORE_DIG_DLANE_0_RW_HS_TX_0 0x6200 573 #define CORE_DIG_DLANE_0_RW_HS_TX_1 0x6202 574 #define CORE_DIG_DLANE_0_RW_HS_TX_2 0x6204 575 #define CORE_DIG_DLANE_0_RW_HS_TX_3 0x6206 576 #define CORE_DIG_DLANE_0_RW_HS_TX_4 0x6208 577 #define CORE_DIG_DLANE_0_RW_HS_TX_5 0x620a 578 #define CORE_DIG_DLANE_0_RW_HS_TX_6 0x620c 579 #define CORE_DIG_DLANE_0_RW_HS_TX_7 0x620e 580 #define CORE_DIG_DLANE_0_RW_HS_TX_8 0x6210 581 #define CORE_DIG_DLANE_0_RW_HS_TX_9 0x6212 582 #define CORE_DIG_DLANE_0_RW_HS_TX_10 0x6214 583 #define CORE_DIG_DLANE_0_RW_HS_TX_11 0x6216 584 #define CORE_DIG_DLANE_0_RW_HS_TX_12 0x6218 585 #define CORE_DIG_DLANE_1_RW_CFG_0 0x6400 586 #define CORE_DIG_DLANE_1_RW_CFG_1 0x6402 587 #define CORE_DIG_DLANE_1_RW_CFG_2 0x6404 588 #define CORE_DIG_DLANE_1_RW_LP_0 0x6480 589 #define CORE_DIG_DLANE_1_RW_LP_1 0x6482 590 #define CORE_DIG_DLANE_1_RW_LP_2 0x6484 591 #define CORE_DIG_DLANE_1_R_LP_0 0x64a0 592 #define CORE_DIG_DLANE_1_R_LP_1 0x64a2 593 #define CORE_DIG_DLANE_1_R_HS_TX_0 0x64e0 594 #define CORE_DIG_DLANE_1_RW_HS_RX_0 0x6500 595 #define CORE_DIG_DLANE_1_RW_HS_RX_1 0x6502 596 #define CORE_DIG_DLANE_1_RW_HS_RX_2 0x6504 597 #define CORE_DIG_DLANE_1_RW_HS_RX_3 0x6506 598 #define CORE_DIG_DLANE_1_RW_HS_RX_4 0x6508 599 #define CORE_DIG_DLANE_1_RW_HS_RX_5 0x650a 600 #define CORE_DIG_DLANE_1_RW_HS_RX_6 0x650c 601 #define CORE_DIG_DLANE_1_RW_HS_RX_7 0x650e 602 #define CORE_DIG_DLANE_1_RW_HS_RX_8 0x6510 603 #define CORE_DIG_DLANE_1_RW_HS_RX_9 0x6512 604 #define CORE_DIG_DLANE_1_R_HS_RX_0 0x6520 605 #define CORE_DIG_DLANE_1_R_HS_RX_1 0x6522 606 #define CORE_DIG_DLANE_1_R_HS_RX_2 0x6524 607 #define CORE_DIG_DLANE_1_R_HS_RX_3 0x6526 608 #define CORE_DIG_DLANE_1_R_HS_RX_4 0x6528 609 #define CORE_DIG_DLANE_1_RW_HS_TX_0 0x6600 610 #define CORE_DIG_DLANE_1_RW_HS_TX_1 0x6602 611 #define CORE_DIG_DLANE_1_RW_HS_TX_2 0x6604 612 #define CORE_DIG_DLANE_1_RW_HS_TX_3 0x6606 613 #define CORE_DIG_DLANE_1_RW_HS_TX_4 0x6608 614 #define CORE_DIG_DLANE_1_RW_HS_TX_5 0x660a 615 #define CORE_DIG_DLANE_1_RW_HS_TX_6 0x660c 616 #define CORE_DIG_DLANE_1_RW_HS_TX_7 0x660e 617 #define CORE_DIG_DLANE_1_RW_HS_TX_8 0x6610 618 #define CORE_DIG_DLANE_1_RW_HS_TX_9 0x6612 619 #define CORE_DIG_DLANE_1_RW_HS_TX_10 0x6614 620 #define CORE_DIG_DLANE_1_RW_HS_TX_11 0x6616 621 #define CORE_DIG_DLANE_1_RW_HS_TX_12 0x6618 622 #define CORE_DIG_DLANE_2_RW_CFG_0 0x6800 623 #define CORE_DIG_DLANE_2_RW_CFG_1 0x6802 624 #define CORE_DIG_DLANE_2_RW_CFG_2 0x6804 625 #define CORE_DIG_DLANE_2_RW_LP_0 0x6880 626 #define CORE_DIG_DLANE_2_RW_LP_1 0x6882 627 #define CORE_DIG_DLANE_2_RW_LP_2 0x6884 628 #define CORE_DIG_DLANE_2_R_LP_0 0x68a0 629 #define CORE_DIG_DLANE_2_R_LP_1 0x68a2 630 #define CORE_DIG_DLANE_2_R_HS_TX_0 0x68e0 631 #define CORE_DIG_DLANE_2_RW_HS_RX_0 0x6900 632 #define CORE_DIG_DLANE_2_RW_HS_RX_1 0x6902 633 #define CORE_DIG_DLANE_2_RW_HS_RX_2 0x6904 634 #define CORE_DIG_DLANE_2_RW_HS_RX_3 0x6906 635 #define CORE_DIG_DLANE_2_RW_HS_RX_4 0x6908 636 #define CORE_DIG_DLANE_2_RW_HS_RX_5 0x690a 637 #define CORE_DIG_DLANE_2_RW_HS_RX_6 0x690c 638 #define CORE_DIG_DLANE_2_RW_HS_RX_7 0x690e 639 #define CORE_DIG_DLANE_2_RW_HS_RX_8 0x6910 640 #define CORE_DIG_DLANE_2_RW_HS_RX_9 0x6912 641 #define CORE_DIG_DLANE_2_R_HS_RX_0 0x6920 642 #define CORE_DIG_DLANE_2_R_HS_RX_1 0x6922 643 #define CORE_DIG_DLANE_2_R_HS_RX_2 0x6924 644 #define CORE_DIG_DLANE_2_R_HS_RX_3 0x6926 645 #define CORE_DIG_DLANE_2_R_HS_RX_4 0x6928 646 #define CORE_DIG_DLANE_2_RW_HS_TX_0 0x6a00 647 #define CORE_DIG_DLANE_2_RW_HS_TX_1 0x6a02 648 #define CORE_DIG_DLANE_2_RW_HS_TX_2 0x6a04 649 #define CORE_DIG_DLANE_2_RW_HS_TX_3 0x6a06 650 #define CORE_DIG_DLANE_2_RW_HS_TX_4 0x6a08 651 #define CORE_DIG_DLANE_2_RW_HS_TX_5 0x6a0a 652 #define CORE_DIG_DLANE_2_RW_HS_TX_6 0x6a0c 653 #define CORE_DIG_DLANE_2_RW_HS_TX_7 0x6a0e 654 #define CORE_DIG_DLANE_2_RW_HS_TX_8 0x6a10 655 #define CORE_DIG_DLANE_2_RW_HS_TX_9 0x6a12 656 #define CORE_DIG_DLANE_2_RW_HS_TX_10 0x6a14 657 #define CORE_DIG_DLANE_2_RW_HS_TX_11 0x6a16 658 #define CORE_DIG_DLANE_2_RW_HS_TX_12 0x6a18 659 #define CORE_DIG_DLANE_3_RW_CFG_0 0x6c00 660 #define CORE_DIG_DLANE_3_RW_CFG_1 0x6c02 661 #define CORE_DIG_DLANE_3_RW_CFG_2 0x6c04 662 #define CORE_DIG_DLANE_3_RW_LP_0 0x6c80 663 #define CORE_DIG_DLANE_3_RW_LP_1 0x6c82 664 #define CORE_DIG_DLANE_3_RW_LP_2 0x6c84 665 #define CORE_DIG_DLANE_3_R_LP_0 0x6ca0 666 #define CORE_DIG_DLANE_3_R_LP_1 0x6ca2 667 #define CORE_DIG_DLANE_3_R_HS_TX_0 0x6ce0 668 #define CORE_DIG_DLANE_3_RW_HS_RX_0 0x6d00 669 #define CORE_DIG_DLANE_3_RW_HS_RX_1 0x6d02 670 #define CORE_DIG_DLANE_3_RW_HS_RX_2 0x6d04 671 #define CORE_DIG_DLANE_3_RW_HS_RX_3 0x6d06 672 #define CORE_DIG_DLANE_3_RW_HS_RX_4 0x6d08 673 #define CORE_DIG_DLANE_3_RW_HS_RX_5 0x6d0a 674 #define CORE_DIG_DLANE_3_RW_HS_RX_6 0x6d0c 675 #define CORE_DIG_DLANE_3_RW_HS_RX_7 0x6d0e 676 #define CORE_DIG_DLANE_3_RW_HS_RX_8 0x6d10 677 #define CORE_DIG_DLANE_3_RW_HS_RX_9 0x6d12 678 #define CORE_DIG_DLANE_3_R_HS_RX_0 0x6d20 679 #define CORE_DIG_DLANE_3_R_HS_RX_1 0x6d22 680 #define CORE_DIG_DLANE_3_R_HS_RX_2 0x6d24 681 #define CORE_DIG_DLANE_3_R_HS_RX_3 0x6d26 682 #define CORE_DIG_DLANE_3_R_HS_RX_4 0x6d28 683 #define CORE_DIG_DLANE_3_RW_HS_TX_0 0x6e00 684 #define CORE_DIG_DLANE_3_RW_HS_TX_1 0x6e02 685 #define CORE_DIG_DLANE_3_RW_HS_TX_2 0x6e04 686 #define CORE_DIG_DLANE_3_RW_HS_TX_3 0x6e06 687 #define CORE_DIG_DLANE_3_RW_HS_TX_4 0x6e08 688 #define CORE_DIG_DLANE_3_RW_HS_TX_5 0x6e0a 689 #define CORE_DIG_DLANE_3_RW_HS_TX_6 0x6e0c 690 #define CORE_DIG_DLANE_3_RW_HS_TX_7 0x6e0e 691 #define CORE_DIG_DLANE_3_RW_HS_TX_8 0x6e10 692 #define CORE_DIG_DLANE_3_RW_HS_TX_9 0x6e12 693 #define CORE_DIG_DLANE_3_RW_HS_TX_10 0x6e14 694 #define CORE_DIG_DLANE_3_RW_HS_TX_11 0x6e16 695 #define CORE_DIG_DLANE_3_RW_HS_TX_12 0x6e18 696 #define CORE_DIG_DLANE_CLK_RW_CFG_0 0x7000 697 #define CORE_DIG_DLANE_CLK_RW_CFG_1 0x7002 698 #define CORE_DIG_DLANE_CLK_RW_CFG_2 0x7004 699 #define CORE_DIG_DLANE_CLK_RW_LP_0 0x7080 700 #define CORE_DIG_DLANE_CLK_RW_LP_1 0x7082 701 #define CORE_DIG_DLANE_CLK_RW_LP_2 0x7084 702 #define CORE_DIG_DLANE_CLK_R_LP_0 0x70a0 703 #define CORE_DIG_DLANE_CLK_R_LP_1 0x70a2 704 #define CORE_DIG_DLANE_CLK_R_HS_TX_0 0x70e0 705 #define CORE_DIG_DLANE_CLK_RW_HS_RX_0 0x7100 706 #define CORE_DIG_DLANE_CLK_RW_HS_RX_1 0x7102 707 #define CORE_DIG_DLANE_CLK_RW_HS_RX_2 0x7104 708 #define CORE_DIG_DLANE_CLK_RW_HS_RX_3 0x7106 709 #define CORE_DIG_DLANE_CLK_RW_HS_RX_4 0x7108 710 #define CORE_DIG_DLANE_CLK_RW_HS_RX_5 0x710a 711 #define CORE_DIG_DLANE_CLK_RW_HS_RX_6 0x710c 712 #define CORE_DIG_DLANE_CLK_RW_HS_RX_7 0x710e 713 #define CORE_DIG_DLANE_CLK_RW_HS_RX_8 0x7110 714 #define CORE_DIG_DLANE_CLK_RW_HS_RX_9 0x7112 715 #define CORE_DIG_DLANE_CLK_R_HS_RX_0 0x7120 716 #define CORE_DIG_DLANE_CLK_R_HS_RX_1 0x7122 717 #define CORE_DIG_DLANE_CLK_R_HS_RX_2 0x7124 718 #define CORE_DIG_DLANE_CLK_R_HS_RX_3 0x7126 719 #define CORE_DIG_DLANE_CLK_R_HS_RX_4 0x7128 720 #define CORE_DIG_DLANE_CLK_RW_HS_TX_0 0x7200 721 #define CORE_DIG_DLANE_CLK_RW_HS_TX_1 0x7202 722 #define CORE_DIG_DLANE_CLK_RW_HS_TX_2 0x7204 723 #define CORE_DIG_DLANE_CLK_RW_HS_TX_3 0x7206 724 #define CORE_DIG_DLANE_CLK_RW_HS_TX_4 0x7208 725 #define CORE_DIG_DLANE_CLK_RW_HS_TX_5 0x720a 726 #define CORE_DIG_DLANE_CLK_RW_HS_TX_6 0x720c 727 #define CORE_DIG_DLANE_CLK_RW_HS_TX_7 0x720e 728 #define CORE_DIG_DLANE_CLK_RW_HS_TX_8 0x7210 729 #define CORE_DIG_DLANE_CLK_RW_HS_TX_9 0x7212 730 #define CORE_DIG_DLANE_CLK_RW_HS_TX_10 0x7214 731 #define CORE_DIG_DLANE_CLK_RW_HS_TX_11 0x7216 732 #define CORE_DIG_DLANE_CLK_RW_HS_TX_12 0x7218 733 #define PPI_RW_CPHY_TRIO0_LBERT_0 0x8000 734 #define PPI_RW_CPHY_TRIO0_LBERT_1 0x8002 735 #define PPI_R_CPHY_TRIO0_LBERT_0 0x8004 736 #define PPI_R_CPHY_TRIO0_LBERT_1 0x8006 737 #define PPI_RW_CPHY_TRIO0_SPARE 0x8008 738 #define PPI_RW_CPHY_TRIO1_LBERT_0 0x8400 739 #define PPI_RW_CPHY_TRIO1_LBERT_1 0x8402 740 #define PPI_R_CPHY_TRIO1_LBERT_0 0x8404 741 #define PPI_R_CPHY_TRIO1_LBERT_1 0x8406 742 #define PPI_RW_CPHY_TRIO1_SPARE 0x8408 743 #define PPI_RW_CPHY_TRIO2_LBERT_0 0x8800 744 #define PPI_RW_CPHY_TRIO2_LBERT_1 0x8802 745 #define PPI_R_CPHY_TRIO2_LBERT_0 0x8804 746 #define PPI_R_CPHY_TRIO2_LBERT_1 0x8806 747 #define PPI_RW_CPHY_TRIO2_SPARE 0x8808 748 #define CORE_DIG_CLANE_0_RW_CFG_0 0xa000 749 #define CORE_DIG_CLANE_0_RW_CFG_2 0xa004 750 #define CORE_DIG_CLANE_0_RW_LP_0 0xa080 751 #define CORE_DIG_CLANE_0_RW_LP_1 0xa082 752 #define CORE_DIG_CLANE_0_RW_LP_2 0xa084 753 #define CORE_DIG_CLANE_0_R_LP_0 0xa0a0 754 #define CORE_DIG_CLANE_0_R_LP_1 0xa0a2 755 #define CORE_DIG_CLANE_0_RW_HS_RX_0 0xa100 756 #define CORE_DIG_CLANE_0_RW_HS_RX_1 0xa102 757 #define CORE_DIG_CLANE_0_RW_HS_RX_2 0xa104 758 #define CORE_DIG_CLANE_0_RW_HS_RX_3 0xa106 759 #define CORE_DIG_CLANE_0_RW_HS_RX_4 0xa108 760 #define CORE_DIG_CLANE_0_RW_HS_RX_5 0xa10a 761 #define CORE_DIG_CLANE_0_RW_HS_RX_6 0xa10c 762 #define CORE_DIG_CLANE_0_R_RX_0 0xa120 763 #define CORE_DIG_CLANE_0_R_RX_1 0xa122 764 #define CORE_DIG_CLANE_0_R_TX_0 0xa124 765 #define CORE_DIG_CLANE_0_R_RX_2 0xa126 766 #define CORE_DIG_CLANE_0_R_RX_3 0xa128 767 #define CORE_DIG_CLANE_0_RW_HS_TX_0 0xa200 768 #define CORE_DIG_CLANE_0_RW_HS_TX_1 0xa202 769 #define CORE_DIG_CLANE_0_RW_HS_TX_2 0xa204 770 #define CORE_DIG_CLANE_0_RW_HS_TX_3 0xa206 771 #define CORE_DIG_CLANE_0_RW_HS_TX_4 0xa208 772 #define CORE_DIG_CLANE_0_RW_HS_TX_5 0xa20a 773 #define CORE_DIG_CLANE_0_RW_HS_TX_6 0xa20c 774 #define CORE_DIG_CLANE_0_RW_HS_TX_7 0xa20e 775 #define CORE_DIG_CLANE_0_RW_HS_TX_8 0xa210 776 #define CORE_DIG_CLANE_0_RW_HS_TX_9 0xa212 777 #define CORE_DIG_CLANE_0_RW_HS_TX_10 0xa214 778 #define CORE_DIG_CLANE_0_RW_HS_TX_11 0xa216 779 #define CORE_DIG_CLANE_0_RW_HS_TX_12 0xa218 780 #define CORE_DIG_CLANE_0_RW_HS_TX_13 0xa21a 781 #define CORE_DIG_CLANE_1_RW_CFG_0 0xa400 782 #define CORE_DIG_CLANE_1_RW_CFG_2 0xa404 783 #define CORE_DIG_CLANE_1_RW_LP_0 0xa480 784 #define CORE_DIG_CLANE_1_RW_LP_1 0xa482 785 #define CORE_DIG_CLANE_1_RW_LP_2 0xa484 786 #define CORE_DIG_CLANE_1_R_LP_0 0xa4a0 787 #define CORE_DIG_CLANE_1_R_LP_1 0xa4a2 788 #define CORE_DIG_CLANE_1_RW_HS_RX_0 0xa500 789 #define CORE_DIG_CLANE_1_RW_HS_RX_1 0xa502 790 #define CORE_DIG_CLANE_1_RW_HS_RX_2 0xa504 791 #define CORE_DIG_CLANE_1_RW_HS_RX_3 0xa506 792 #define CORE_DIG_CLANE_1_RW_HS_RX_4 0xa508 793 #define CORE_DIG_CLANE_1_RW_HS_RX_5 0xa50a 794 #define CORE_DIG_CLANE_1_RW_HS_RX_6 0xa50c 795 #define CORE_DIG_CLANE_1_R_RX_0 0xa520 796 #define CORE_DIG_CLANE_1_R_RX_1 0xa522 797 #define CORE_DIG_CLANE_1_R_TX_0 0xa524 798 #define CORE_DIG_CLANE_1_R_RX_2 0xa526 799 #define CORE_DIG_CLANE_1_R_RX_3 0xa528 800 #define CORE_DIG_CLANE_1_RW_HS_TX_0 0xa600 801 #define CORE_DIG_CLANE_1_RW_HS_TX_1 0xa602 802 #define CORE_DIG_CLANE_1_RW_HS_TX_2 0xa604 803 #define CORE_DIG_CLANE_1_RW_HS_TX_3 0xa606 804 #define CORE_DIG_CLANE_1_RW_HS_TX_4 0xa608 805 #define CORE_DIG_CLANE_1_RW_HS_TX_5 0xa60a 806 #define CORE_DIG_CLANE_1_RW_HS_TX_6 0xa60c 807 #define CORE_DIG_CLANE_1_RW_HS_TX_7 0xa60e 808 #define CORE_DIG_CLANE_1_RW_HS_TX_8 0xa610 809 #define CORE_DIG_CLANE_1_RW_HS_TX_9 0xa612 810 #define CORE_DIG_CLANE_1_RW_HS_TX_10 0xa614 811 #define CORE_DIG_CLANE_1_RW_HS_TX_11 0xa616 812 #define CORE_DIG_CLANE_1_RW_HS_TX_12 0xa618 813 #define CORE_DIG_CLANE_1_RW_HS_TX_13 0xa61a 814 #define CORE_DIG_CLANE_2_RW_CFG_0 0xa800 815 #define CORE_DIG_CLANE_2_RW_CFG_2 0xa804 816 #define CORE_DIG_CLANE_2_RW_LP_0 0xa880 817 #define CORE_DIG_CLANE_2_RW_LP_1 0xa882 818 #define CORE_DIG_CLANE_2_RW_LP_2 0xa884 819 #define CORE_DIG_CLANE_2_R_LP_0 0xa8a0 820 #define CORE_DIG_CLANE_2_R_LP_1 0xa8a2 821 #define CORE_DIG_CLANE_2_RW_HS_RX_0 0xa900 822 #define CORE_DIG_CLANE_2_RW_HS_RX_1 0xa902 823 #define CORE_DIG_CLANE_2_RW_HS_RX_2 0xa904 824 #define CORE_DIG_CLANE_2_RW_HS_RX_3 0xa906 825 #define CORE_DIG_CLANE_2_RW_HS_RX_4 0xa908 826 #define CORE_DIG_CLANE_2_RW_HS_RX_5 0xa90a 827 #define CORE_DIG_CLANE_2_RW_HS_RX_6 0xa90c 828 #define CORE_DIG_CLANE_2_R_RX_0 0xa920 829 #define CORE_DIG_CLANE_2_R_RX_1 0xa922 830 #define CORE_DIG_CLANE_2_R_TX_0 0xa924 831 #define CORE_DIG_CLANE_2_R_RX_2 0xa926 832 #define CORE_DIG_CLANE_2_R_RX_3 0xa928 833 #define CORE_DIG_CLANE_2_RW_HS_TX_0 0xaa00 834 #define CORE_DIG_CLANE_2_RW_HS_TX_1 0xaa02 835 #define CORE_DIG_CLANE_2_RW_HS_TX_2 0xaa04 836 #define CORE_DIG_CLANE_2_RW_HS_TX_3 0xaa06 837 #define CORE_DIG_CLANE_2_RW_HS_TX_4 0xaa08 838 #define CORE_DIG_CLANE_2_RW_HS_TX_5 0xaa0a 839 #define CORE_DIG_CLANE_2_RW_HS_TX_6 0xaa0c 840 #define CORE_DIG_CLANE_2_RW_HS_TX_7 0xaa0e 841 #define CORE_DIG_CLANE_2_RW_HS_TX_8 0xaa10 842 #define CORE_DIG_CLANE_2_RW_HS_TX_9 0xaa12 843 #define CORE_DIG_CLANE_2_RW_HS_TX_10 0xaa14 844 #define CORE_DIG_CLANE_2_RW_HS_TX_11 0xaa16 845 #define CORE_DIG_CLANE_2_RW_HS_TX_12 0xaa18 846 #define CORE_DIG_CLANE_2_RW_HS_TX_13 0xaa1a 847 848 /* dwc csi host controller registers */ 849 #define IS_IO_CSI2_HOST_BASE(i) (IS_IO_BASE + 0x40000 + \ 850 0x2000 * (i)) 851 #define VERSION 0x0 852 #define N_LANES 0x4 853 #define CSI2_RESETN 0x8 854 #define INT_ST_MAIN 0xc 855 #define DATA_IDS_1 0x10 856 #define DATA_IDS_2 0x14 857 #define CDPHY_MODE 0x1c 858 #define DATA_IDS_VC_1 0x30 859 #define DATA_IDS_VC_2 0x34 860 #define PHY_SHUTDOWNZ 0x40 861 #define DPHY_RSTZ 0x44 862 #define PHY_RX 0x48 863 #define PHY_STOPSTATE 0x4c 864 #define PHY_TEST_CTRL0 0x50 865 #define PHY_TEST_CTRL1 0x54 866 #define PPI_PG_PATTERN_VRES 0x60 867 #define PPI_PG_PATTERN_HRES 0x64 868 #define PPI_PG_CONFIG 0x68 869 #define PPI_PG_ENABLE 0x6c 870 #define PPI_PG_STATUS 0x70 871 #define VC_EXTENSION 0xc8 872 #define PHY_CAL 0xcc 873 #define INT_ST_PHY_FATAL 0xe0 874 #define INT_MSK_PHY_FATAL 0xe4 875 #define INT_FORCE_PHY_FATAL 0xe8 876 #define INT_ST_PKT_FATAL 0xf0 877 #define INT_MSK_PKT_FATAL 0xf4 878 #define INT_FORCE_PKT_FATAL 0xf8 879 #define INT_ST_PHY 0x110 880 #define INT_MSK_PHY 0x114 881 #define INT_FORCE_PHY 0x118 882 #define INT_ST_LINE 0x130 883 #define INT_MSK_LINE 0x134 884 #define INT_FORCE_LINE 0x138 885 #define INT_ST_BNDRY_FRAME_FATAL 0x280 886 #define INT_MSK_BNDRY_FRAME_FATAL 0x284 887 #define INT_FORCE_BNDRY_FRAME_FATAL 0x288 888 #define INT_ST_SEQ_FRAME_FATAL 0x290 889 #define INT_MSK_SEQ_FRAME_FATAL 0x294 890 #define INT_FORCE_SEQ_FRAME_FATAL 0x298 891 #define INT_ST_CRC_FRAME_FATAL 0x2a0 892 #define INT_MSK_CRC_FRAME_FATAL 0x2a4 893 #define INT_FORCE_CRC_FRAME_FATAL 0x2a8 894 #define INT_ST_PLD_CRC_FATAL 0x2b0 895 #define INT_MSK_PLD_CRC_FATAL 0x2b4 896 #define INT_FORCE_PLD_CRC_FATAL 0x2b8 897 #define INT_ST_DATA_ID 0x2c0 898 #define INT_MSK_DATA_ID 0x2c4 899 #define INT_FORCE_DATA_ID 0x2c8 900 #define INT_ST_ECC_CORRECTED 0x2d0 901 #define INT_MSK_ECC_CORRECTED 0x2d4 902 #define INT_FORCE_ECC_CORRECTED 0x2d8 903 #define SCRAMBLING 0x300 904 #define SCRAMBLING_SEED1 0x304 905 #define SCRAMBLING_SEED2 0x308 906 #define SCRAMBLING_SEED3 0x30c 907 #define SCRAMBLING_SEED4 0x310 908 #define SCRAMBLING 0x300 909 910 #define IS_IO_CSI2_ADPL_PORT_BASE(i) (IS_IO_BASE + 0x40800 + \ 911 0x2000 * (i)) 912 #define CSI2_ADPL_INPUT_MODE 0x0 913 #define CSI2_ADPL_CSI_RX_ERR_IRQ_CLEAR_EN 0x4 914 #define CSI2_ADPL_CSI_RX_ERR_IRQ_CLEAR_ADDR 0x8 915 #define CSI2_ADPL_CSI_RX_ERR_IRQ_STATUS 0xc 916 #define CSI2_ADPL_IRQ_CTL_COMMON_STATUS 0xa4 917 #define CSI2_ADPL_IRQ_CTL_COMMON_CLEAR 0xa8 918 #define CSI2_ADPL_IRQ_CTL_COMMON_ENABLE 0xac 919 #define CSI2_ADPL_IRQ_CTL_FS_STATUS 0xbc 920 #define CSI2_ADPL_IRQ_CTL_FS_CLEAR 0xc0 921 #define CSI2_ADPL_IRQ_CTL_FS_ENABLE 0xc4 922 #define CSI2_ADPL_IRQ_CTL_FE_STATUS 0xc8 923 #define CSI2_ADPL_IRQ_CTL_FE_CLEAR 0xcc 924 #define CSI2_ADPL_IRQ_CTL_FE_ENABLE 0xd0 925 926 /* software control the legacy csi irq */ 927 #define IS_IO_CSI2_ERR_LEGACY_IRQ_CTL_BASE(i) (IS_IO_BASE + 0x40c00 + \ 928 0x2000 * (i)) 929 #define IS_IO_CSI2_SYNC_LEGACY_IRQ_CTL_BASE(i) (IS_IO_BASE + 0x40d00 + \ 930 0x2000 * (i)) 931 #define IS_IO_CSI2_LEGACY_IRQ_CTRL_BASE (IS_IO_BASE + 0x49000) 932 #define IS_IO_CSI2_IRQ_CTRL_BASE (IS_IO_BASE + 0x4e100) 933 934 #define IRQ_CTL_EDGE 0x0 935 #define IRQ_CTL_MASK 0x4 936 #define IRQ_CTL_STATUS 0x8 937 #define IRQ_CTL_CLEAR 0xc 938 #define IRQ_CTL_ENABLE 0x10 939 /* FE irq for PTL */ 940 #define IRQ1_CTL_MASK 0x14 941 #define IRQ1_CTL_STATUS 0x18 942 #define IRQ1_CTL_CLEAR 0x1c 943 #define IRQ1_CTL_ENABLE 0x20 944 945 /* software to set the clock gate to use the port or mgc */ 946 #define IS_IO_GPREGS_BASE (IS_IO_BASE + 0x49200) 947 #define SRST_PORT_ARB 0x0 948 #define SRST_MGC 0x4 949 #define SRST_WIDTH_CONV 0x8 950 #define SRST_CSI_IRQ 0xc 951 #define SRST_CSI_LEGACY_IRQ 0x10 952 #define CLK_EN_TXCLKESC 0x14 953 #define CLK_DIV_FACTOR_IS_CLK 0x18 954 #define CLK_DIV_FACTOR_APB_CLK 0x1c 955 #define CSI_PORT_CLK_GATE 0x20 956 #define CSI_PORTAB_AGGREGATION 0x24 957 #define MGC_CLK_GATE 0x2c 958 #define CG_CTRL_BITS 0x3c 959 #define SPARE_RW 0xf8 960 #define SPARE_RO 0xfc 961 962 #define IS_IO_CSI2_MPF_PORT_BASE(i) (IS_IO_BASE + 0x53000 + \ 963 0x1000 * (i)) 964 #define MPF_16_IRQ_CNTRL_STATUS 0x238 965 #define MPF_16_IRQ_CNTRL_CLEAR 0x23c 966 #define MPF_16_IRQ_CNTRL_ENABLE 0x240 967 968 /* software config the phy */ 969 #define IS_IO_CSI2_GPREGS_BASE (IS_IO_BASE + 0x53400) 970 #define IPU8_IS_IO_CSI2_GPREGS_BASE (IS_IO_BASE + 0x40e00) 971 #define CSI_ADAPT_LAYER_SRST 0x0 972 #define MPF_SRST_RST 0x4 973 #define CSI_ERR_IRQ_CTRL_SRST 0x8 974 #define CSI_SYNC_RC_SRST 0xc 975 #define CSI_CG_CTRL_BITS 0x10 976 #define SOC_CSI2HOST_SELECT 0x14 977 #define PHY_RESET 0x18 978 #define PHY_SHUTDOWN 0x1c 979 #define PHY_MODE 0x20 980 #define PHY_READY 0x24 981 #define PHY_CLK_LANE_FORCE_CONTROL 0x28 982 #define PHY_CLK_LANE_CONTROL 0x2c 983 #define PHY_CLK_LANE_STATUS 0x30 984 #define PHY_LANE_RX_ESC_REQ 0x34 985 #define PHY_LANE_RX_ESC_DATA 0x38 986 #define PHY_LANE_TURNDISABLE 0x3c 987 #define PHY_LANE_DIRECTION 0x40 988 #define PHY_LANE_FORCE_CONTROL 0x44 989 #define PHY_LANE_CONTROL_EN 0x48 990 #define PHY_LANE_CONTROL_DATAWIDTH 0x4c 991 #define PHY_LANE_STATUS 0x50 992 #define PHY_LANE_ERR 0x54 993 #define PHY_LANE_RXALP 0x58 994 #define PHY_LANE_RXALP_NIBBLE 0x5c 995 #define PHY_PARITY_ERROR 0x60 996 #define PHY_DEBUG_REGS_CLK_GATE_EN 0x64 997 #define SPARE_RW 0xf8 998 #define SPARE_RO 0xfc 999 1000 /* software not touch */ 1001 #define PORT_ARB_BASE (IS_IO_BASE + 0x4e000) 1002 #define PORT_ARB_IRQ_CTL_STATUS 0x4 1003 #define PORT_ARB_IRQ_CTL_CLEAR 0x8 1004 #define PORT_ARB_IRQ_CTL_ENABLE 0xc 1005 1006 #define MGC_PPC 4U 1007 #define MGC_DTYPE_RAW(i) (((i) - 8) / 2) 1008 #define IS_IO_MGC_BASE (IS_IO_BASE + 0x48000) 1009 #define MGC_KICK 0x0 1010 #define MGC_ASYNC_STOP 0x4 1011 #define MGC_PORT_OFFSET 0x100 1012 #define MGC_CSI_PORT_MAP(i) (0x8 + (i) * 0x4) 1013 #define MGC_MG_PORT(i) (IS_IO_MGC_BASE + \ 1014 (i) * MGC_PORT_OFFSET) 1015 /* per mgc instance */ 1016 #define MGC_MG_CSI_ADAPT_LAYER_TYPE 0x28 1017 #define MGC_MG_MODE 0x2c 1018 #define MGC_MG_INIT_COUNTER 0x30 1019 #define MGC_MG_MIPI_VC 0x34 1020 #define MGC_MG_MIPI_DTYPES 0x38 1021 #define MGC_MG_MULTI_DTYPES_MODE 0x3c 1022 #define MGC_MG_NOF_FRAMES 0x40 1023 #define MGC_MG_FRAME_DIM 0x44 1024 #define MGC_MG_HBLANK 0x48 1025 #define MGC_MG_VBLANK 0x4c 1026 #define MGC_MG_TPG_MODE 0x50 1027 #define MGC_MG_TPG_R0 0x54 1028 #define MGC_MG_TPG_G0 0x58 1029 #define MGC_MG_TPG_B0 0x5c 1030 #define MGC_MG_TPG_R1 0x60 1031 #define MGC_MG_TPG_G1 0x64 1032 #define MGC_MG_TPG_B1 0x68 1033 #define MGC_MG_TPG_FACTORS 0x6c 1034 #define MGC_MG_TPG_MASKS 0x70 1035 #define MGC_MG_TPG_XY_MASK 0x74 1036 #define MGC_MG_TPG_TILE_DIM 0x78 1037 #define MGC_MG_PRBS_LFSR_INIT_0 0x7c 1038 #define MGC_MG_PRBS_LFSR_INIT_1 0x80 1039 #define MGC_MG_SYNC_STOP_POINT 0x84 1040 #define MGC_MG_SYNC_STOP_POINT_LOC 0x88 1041 #define MGC_MG_ERR_INJECT 0x8c 1042 #define MGC_MG_ERR_LOCATION 0x90 1043 #define MGC_MG_DTO_SPEED_CTRL_EN 0x94 1044 #define MGC_MG_DTO_SPEED_CTRL_INCR_VAL 0x98 1045 #define MGC_MG_HOR_LOC_STTS 0x9c 1046 #define MGC_MG_VER_LOC_STTS 0xa0 1047 #define MGC_MG_FRAME_NUM_STTS 0xa4 1048 #define MGC_MG_BUSY_STTS 0xa8 1049 #define MGC_MG_STOPPED_STTS 0xac 1050 /* tile width and height in pixels for Chess board and Color palette */ 1051 #define MGC_TPG_TILE_WIDTH 64U 1052 #define MGC_TPG_TILE_HEIGHT 64U 1053 1054 #define IPU_CSI_PORT_A_ADDR_OFFSET 0x0 1055 #define IPU_CSI_PORT_B_ADDR_OFFSET 0x0 1056 #define IPU_CSI_PORT_C_ADDR_OFFSET 0x0 1057 #define IPU_CSI_PORT_D_ADDR_OFFSET 0x0 1058 1059 /* 1060 * 0 - CSI RX Port 0 interrupt; 1061 * 1 - MPF Port 0 interrupt; 1062 * 2 - CSI RX Port 1 interrupt; 1063 * 3 - MPF Port 1 interrupt; 1064 * 4 - CSI RX Port 2 interrupt; 1065 * 5 - MPF Port 2 interrupt; 1066 * 6 - CSI RX Port 3 interrupt; 1067 * 7 - MPF Port 3 interrupt; 1068 * 8 - Port ARB FIFO 0 overflow; 1069 * 9 - Port ARB FIFO 1 overflow; 1070 * 10 - Port ARB FIFO 2 overflow; 1071 * 11 - Port ARB FIFO 3 overflow; 1072 * 12 - isys_cfgnoc_err_probe_intl; 1073 * 13-15 - reserved 1074 */ 1075 #define IPU7_CSI_IS_IO_IRQ_MASK 0xffff 1076 1077 /* Adapter layer irq */ 1078 #define IPU7_CSI_ADPL_IRQ_MASK 0xffff 1079 1080 /* sw irq from legacy irq control 1081 * legacy irq status 1082 * IPU7 1083 * 0 - CSI Port 0 error interrupt 1084 * 1 - CSI Port 0 sync interrupt 1085 * 2 - CSI Port 1 error interrupt 1086 * 3 - CSI Port 1 sync interrupt 1087 * 4 - CSI Port 2 error interrupt 1088 * 5 - CSI Port 2 sync interrupt 1089 * 6 - CSI Port 3 error interrupt 1090 * 7 - CSI Port 3 sync interrupt 1091 * IPU7P5 1092 * 0 - CSI Port 0 error interrupt 1093 * 1 - CSI Port 0 fs interrupt 1094 * 2 - CSI Port 0 fe interrupt 1095 * 3 - CSI Port 1 error interrupt 1096 * 4 - CSI Port 1 fs interrupt 1097 * 5 - CSI Port 1 fe interrupt 1098 * 6 - CSI Port 2 error interrupt 1099 * 7 - CSI Port 2 fs interrupt 1100 * 8 - CSI Port 2 fe interrupt 1101 */ 1102 #define IPU7_CSI_RX_LEGACY_IRQ_MASK 0x1ff 1103 1104 /* legacy error status per port 1105 * 0 - Error handler FIFO full; 1106 * 1 - Reserved Short Packet encoding detected; 1107 * 2 - Reserved Long Packet encoding detected; 1108 * 3 - Received packet is too short (fewer data words than specified in header); 1109 * 4 - Received packet is too long (more data words than specified in header); 1110 * 5 - Short packet discarded due to errors; 1111 * 6 - Long packet discarded due to errors; 1112 * 7 - CSI Combo Rx interrupt; 1113 * 8 - IDI CDC FIFO overflow; remaining bits are reserved and tied to 0; 1114 */ 1115 #define IPU7_CSI_RX_ERROR_IRQ_MASK 0xfff 1116 1117 /* 1118 * 0 - VC0 frame start received 1119 * 1 - VC0 frame end received 1120 * 2 - VC1 frame start received 1121 * 3 - VC1 frame end received 1122 * 4 - VC2 frame start received 1123 * 5 - VC2 frame end received 1124 * 6 - VC3 frame start received 1125 * 7 - VC3 frame end received 1126 * 8 - VC4 frame start received 1127 * 9 - VC4 frame end received 1128 * 10 - VC5 frame start received 1129 * 11 - VC5 frame end received 1130 * 12 - VC6 frame start received 1131 * 13 - VC6 frame end received 1132 * 14 - VC7 frame start received 1133 * 15 - VC7 frame end received 1134 * 16 - VC8 frame start received 1135 * 17 - VC8 frame end received 1136 * 18 - VC9 frame start received 1137 * 19 - VC9 frame end received 1138 * 20 - VC10 frame start received 1139 * 21 - VC10 frame end received 1140 * 22 - VC11 frame start received 1141 * 23 - VC11 frame end received 1142 * 24 - VC12 frame start received 1143 * 25 - VC12 frame end received 1144 * 26 - VC13 frame start received 1145 * 27 - VC13 frame end received 1146 * 28 - VC14 frame start received 1147 * 29 - VC14 frame end received 1148 * 30 - VC15 frame start received 1149 * 31 - VC15 frame end received 1150 */ 1151 1152 #define IPU7_CSI_RX_SYNC_IRQ_MASK 0x0 1153 #define IPU7P5_CSI_RX_SYNC_FE_IRQ_MASK 0x0 1154 1155 #define CSI_RX_NUM_ERRORS_IN_IRQ 12U 1156 #define CSI_RX_NUM_SYNC_IN_IRQ 32U 1157 1158 enum CSI_FE_MODE_TYPE { 1159 CSI_FE_DPHY_MODE = 0, 1160 CSI_FE_CPHY_MODE = 1, 1161 }; 1162 1163 enum CSI_FE_INPUT_MODE { 1164 CSI_SENSOR_INPUT = 0, 1165 CSI_MIPIGEN_INPUT = 1, 1166 }; 1167 1168 enum MGC_CSI_ADPL_TYPE { 1169 MGC_MAPPED_2_LANES = 0, 1170 MGC_MAPPED_4_LANES = 1, 1171 }; 1172 1173 enum CSI2HOST_SELECTION { 1174 CSI2HOST_SEL_SOC = 0, 1175 CSI2HOST_SEL_CSI2HOST = 1, 1176 }; 1177 1178 #define IPU7_ISYS_LEGACY_IRQ_CSI2(port) (0x3 << (port)) 1179 #define IPU7P5_ISYS_LEGACY_IRQ_CSI2(port) (0x7 << (port)) 1180 1181 /* ---------------------------------------------------------------- */ 1182 #define CSI_REG_BASE 0x220000 1183 #define CSI_REG_BASE_PORT(id) ((id) * 0x1000) 1184 1185 /* CSI Port General Purpose Registers */ 1186 #define CSI_REG_PORT_GPREG_SRST 0x0 1187 #define CSI_REG_PORT_GPREG_CSI2_SLV_REG_SRST 0x4 1188 #define CSI_REG_PORT_GPREG_CSI2_PORT_CONTROL 0x8 1189 1190 #define CSI_RX_NUM_IRQ 32U 1191 1192 #define IPU7_CSI_RX_SYNC_FS_VC 0x55555555 1193 #define IPU7_CSI_RX_SYNC_FE_VC 0xaaaaaaaa 1194 #define IPU7P5_CSI_RX_SYNC_FS_VC 0xffff 1195 #define IPU7P5_CSI_RX_SYNC_FE_VC 0xffff 1196 1197 #endif /* IPU7_ISYS_CSI2_REG_H */ 1198