Home
last modified time | relevance | path

Searched refs:PORT_B (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c310 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { in emulate_monitor_status_change()
317 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in emulate_monitor_status_change()
319 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in emulate_monitor_status_change()
322 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= in emulate_monitor_status_change()
326 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
328 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
333 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
364 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
418 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { in emulate_monitor_status_change()
420 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); in emulate_monitor_status_change()
[all …]
H A Dvgpu.c378 ret = intel_gvt_set_edid(vgpu, PORT_B); in intel_gvt_create_vgpu()
H A Dhandlers.c570 case PORT_B: in bxt_vgpu_get_dp_bitrate()
677 if (port != PORT_B && port != PORT_D) { in vgpu_update_refresh_rate()
964 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
2377 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2383 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2389 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
2793 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, in init_bxt_mmio_info()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c263 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
272 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
282 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
292 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
307 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
403 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
415 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
426 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
438 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
453 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDV…
[all …]
H A Dintel_pch_display.c85 assert_pch_dp_disabled(display, pipe, PORT_B, PCH_DP_B); in assert_pch_ports_disabled()
100 assert_pch_hdmi_disabled(display, pipe, PORT_B, PCH_HDMIB); in assert_pch_ports_disabled()
169 ibx_sanitize_pch_dp_port(display, PORT_B, PCH_DP_B); in ibx_sanitize_pch_ports()
174 ibx_sanitize_pch_hdmi_port(display, PORT_B, PCH_HDMIB); in ibx_sanitize_pch_ports()
438 drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D); in ilk_pch_enable()
H A Dintel_lpe_audio.c337 ppdata = &pdata->port[port - PORT_B]; in intel_lpe_audio_notify()
364 pdata->notify_audio_lpe(display->audio.lpe.platdev, port - PORT_B); in intel_lpe_audio_notify()
H A Dintel_display_limits.h96 PORT_B, enumerator
H A Dintel_dpio_phy.c176 [DPIO_CH0] = { .port = PORT_B },
199 [DPIO_CH0] = { .port = PORT_B },
665 case PORT_B: in vlv_dig_port_to_channel()
679 case PORT_B: in vlv_dig_port_to_phy()
1182 case PORT_B: in vlv_wait_port_ready()
H A Dicl_dsi.c242 port = PORT_B; in icl_dsi_frame_update()
1116 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1544 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1556 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1559 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1685 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
2008 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
H A Dintel_sdvo.c234 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_write_sdvox()
412 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")
1627 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_pre_enable()
2622 if (sdvo->base.port == PORT_B) in intel_sdvo_select_ddc_bus()
2645 if (sdvo->base.port == PORT_B) in intel_sdvo_select_i2c_bus()
2689 if (sdvo->base.port == PORT_B) { in intel_sdvo_get_target_addr()
2716 if (sdvo->base.port == PORT_B) in intel_sdvo_get_target_addr()
3368 return port == PORT_B; in is_sdvo_port_valid()
3370 return port == PORT_B || port == PORT_C; in is_sdvo_port_valid()
3466 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_init()
H A Dintel_audio_regs.h161 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \
H A Dintel_dsi_vbt.c92 if (intel_dsi->ports & BIT(PORT_B)) in intel_dsi_seq_port_to_port()
93 return PORT_B; in intel_dsi_seq_port_to_port()
H A Dintel_bios.c1650 enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C; in parse_dsi_backlight_ports()
2345 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2360 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2371 [PORT_B] = { -1 }, in dvo_port_to_port()
2380 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2420 return PORT_B; in dsi_dvo_port_to_port()
H A Dintel_dvo.c107 .port = PORT_B,
H A Dintel_display.c7876 found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); in intel_setup_outputs()
7878 g4x_hdmi_init(display, PCH_HDMIB, PORT_B); in intel_setup_outputs()
7880 g4x_dp_init(display, PCH_DP_B, PORT_B); in intel_setup_outputs()
7915 has_edp = intel_dp_is_port_edp(display, PORT_B); in intel_setup_outputs()
7916 has_port = intel_bios_is_port_present(display, PORT_B); in intel_setup_outputs()
7918 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); in intel_setup_outputs()
7920 g4x_hdmi_init(display, VLV_HDMIB, PORT_B); in intel_setup_outputs()
7955 found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); in intel_setup_outputs()
7959 g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); in intel_setup_outputs()
7963 g4x_dp_init(display, DP_B, PORT_B); in intel_setup_outputs()
H A Dintel_display_irq.c1335 PORT_A : PORT_B; in gen11_dsi_te_interrupt_handler()
1367 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; in gen11_dsi_te_interrupt_handler()
1760 port = PORT_B; in gen11_dsi_configure_te()
H A Dintel_hdcp.c465 case PORT_B: in intel_hdcp_get_repeater_ctl()
2285 case PORT_B ... PORT_F: in intel_get_hdcp_ddi_index()
H A Dintel_psr.c1232 return pipe <= PIPE_B && port <= PORT_B; in dc3co_is_pipe_port_compatible()
H A Dintel_dp.c6943 port != PORT_B && port != PORT_C)) in intel_dp_init_connector()