Searched refs:PLLnCR1_FRATE_SEL (Results 1 – 1 of 1) sorted by relevance
56 #define PLLnCR1_FRATE_SEL GENMASK(28, 24) macro547 switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) { in lynx_28g_lane_set_nrate()1043 switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) { in lynx_28g_pll_read_configuration()