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Searched refs:PLL_36XX_RATE (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c695 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
696 PLL_36XX_RATE(24 * MHZ, 288000000, 96, 2, 2, 0),
697 PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3, 0),
698 PLL_36XX_RATE(24 * MHZ, 144000000, 96, 2, 3, 0),
699 PLL_36XX_RATE(24 * MHZ, 96000000, 128, 2, 4, 0),
700 PLL_36XX_RATE(24 * MHZ, 84000000, 112, 2, 4, 0),
701 PLL_36XX_RATE(24 * MHZ, 80000003, 106, 2, 4, 43691),
702 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
703 PLL_36XX_RATE(24 * MHZ, 67737598, 270, 3, 5, 62285),
704 PLL_36XX_RATE(24 * MHZ, 65535999, 174, 2, 5, 49982),
[all …]
H A Dclk-exynos5410.c228 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
229 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
230 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
231 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
232 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
233 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
234 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
235 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
236 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
237 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
H A Dclk-exynos5260.c68 PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),
69 PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),
70 PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),
71 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
72 PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
73 PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),
74 PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),
75 PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),
76 PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
77 PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),
[all …]
H A Dclk-artpec8.c170 PLL_36XX_RATE(25 * MHZ, 589823913U, 47, 1, 1, 12184),
171 PLL_36XX_RATE(25 * MHZ, 393215942U, 47, 3, 0, 12184),
172 PLL_36XX_RATE(25 * MHZ, 294911956U, 47, 1, 2, 12184),
173 PLL_36XX_RATE(25 * MHZ, 100000000U, 32, 2, 2, 0),
174 PLL_36XX_RATE(25 * MHZ, 98303985U, 47, 3, 2, 12184),
175 PLL_36XX_RATE(25 * MHZ, 49151992U, 47, 3, 3, 12184),
H A Dclk-pll.h70 #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \ macro
H A Dclk-exynos5433.c789 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
790 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
791 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
792 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
793 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
794 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
795 PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923),
796 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
797 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
798 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
H A Dclk-exynos7.c138 PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),