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Searched refs:PIPE_A (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_pch_display.c29 (HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
37 return PIPE_A; in intel_crtc_pch_transcoder()
124 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_hdmi_port()
132 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port()
143 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_dp_port()
151 val |= DP_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_dp_port()
555 assert_fdi_rx_enabled(display, PIPE_A); in lpt_enable_pch_transcoder()
557 val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
563 intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
589 intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); in lpt_disable_pch_transcoder()
[all …]
H A Dintel_fdi.c221 case PIPE_A: in ilk_check_fdi_lanes()
420 case PIPE_A: in ivb_update_fdi_bc_bifurcation()
867 intel_de_write(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
877 intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
878 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
883 intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
912 intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
916 intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
917 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
923 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
[all …]
H A Dskl_watermark.c760 .active_pipes = BIT(PIPE_A),
762 [PIPE_A] = BIT(DBUF_S1),
772 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
774 [PIPE_A] = BIT(DBUF_S1),
785 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
787 [PIPE_A] = BIT(DBUF_S1),
799 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
801 [PIPE_A] = BIT(DBUF_S1),
823 .active_pipes = BIT(PIPE_A),
825 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
[all …]
H A Dintel_display_device.c170 [PIPE_A] = CURSOR_A_OFFSET, \
175 [PIPE_A] = CURSOR_A_OFFSET, \
181 [PIPE_A] = CURSOR_A_OFFSET, \
188 [PIPE_A] = CURSOR_A_OFFSET, \
195 [PIPE_A] = CURSOR_A_OFFSET, \
241 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
254 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
304 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
393 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
450 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
[all …]
H A Dintel_display_limits.h17 PIPE_A = 0, enumerator
34 TRANSCODER_A = PIPE_A,
H A Dg4x_dp.c271 *pipe = PIPE_A; in cpt_dp_port_selected()
441 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); in intel_dp_link_down()
442 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in intel_dp_link_down()
446 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
455 intel_wait_for_vblank_if_active(display, PIPE_A); in intel_dp_link_down()
456 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); in intel_dp_link_down()
457 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in intel_dp_link_down()
1391 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
H A Dintel_crt.c255 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in hsw_disable_crt()
284 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in hsw_post_disable_crt()
296 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in hsw_pre_pll_enable_crt()
341 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in hsw_enable_crt()
1065 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1131 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
H A Dintel_display_power_well.c1103 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1104 i830_enable_pipe(display, PIPE_A); in i830_pipes_power_well_enable()
1113 i830_disable_pipe(display, PIPE_A); in i830_pipes_power_well_disable()
1119 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1259 if (pipe != PIPE_A) in vlv_display_power_well_init()
1538 assert_pll_disabled(display, PIPE_A); in chv_dpio_cmn_power_well_disable()
1693 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1724 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
H A Dintel_display_irq.c413 i915_enable_pipestat(display, PIPE_A, in i915_enable_asle_pipestat()
562 case PIPE_A: in i9xx_pipestat_irq_ack()
717 intel_pch_fifo_underrun_irq_handler(display, PIPE_A); in ibx_irq_handler()
726 case PIPE_A: in ivb_err_int_pipe_fault_mask()
847 case PIPE_A: in ilk_gtt_fault_pipe_fault_mask()
1351 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
1827 case PIPE_A: in vlv_dpinvgtt_pipe_fault_mask()
1991 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_display_irq_postinstall()
2005 i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_display_irq_postinstall()
2006 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_display_irq_postinstall()
[all …]
H A Dhsw_ips.c189 return HAS_IPS(display) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
H A Dintel_display_power_map.c1336 .irq_pipe_mask = BIT(PIPE_A),
1493 .irq_pipe_mask = BIT(PIPE_A),
1660 .irq_pipe_mask = BIT(PIPE_A),
1733 .irq_pipe_mask = BIT(PIPE_A),
H A Dintel_dmc.c260 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
482 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) in adlp_pipedmc_clock_gating_wa()
499 MTL_PIPEDMC_GATING_DIS(PIPE_A) | in mtl_pipedmc_clock_gating_wa()
935 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A)); in intel_dmc_load_program()
H A Dintel_sdvo.c1864 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); in intel_disable_sdvo()
1865 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in intel_disable_sdvo()
1868 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_sdvo()
1874 intel_wait_for_vblank_if_active(display, PIPE_A); in intel_disable_sdvo()
1875 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); in intel_disable_sdvo()
1876 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in intel_disable_sdvo()
H A Dintel_vdsc.c51 drm_WARN_ON(display->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
409 pipe == PIPE_A) in intel_dsc_power_domain()
H A Dintel_dpio_phy.c693 case PIPE_A: in vlv_pipe_to_phy()
707 case PIPE_A: in vlv_pipe_to_channel()
H A Dintel_pfit.c90 max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048; in intel_pch_pfit_check_src_size()
H A Dvlv_dsi.c997 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1963 encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
H A Dicl_dsi.c833 case PIPE_A: in gen11_dsi_configure_transcoder()
1741 *pipe = PIPE_A; in gen11_dsi_get_hw_state()
H A Dintel_backlight.c189 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_get_backlight()
1402 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
H A Dintel_display_trace.h67 static_assert(PIPE_A == _TRACE_PIPE_A);
H A Dintel_vrr.c367 ((pipe == PIPE_A) || (pipe == PIPE_B))); in intel_vrr_dc_balance_possible()
/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c714 vgpu->id, pipe_name(PIPE_A), new_rate); in vgpu_update_refresh_rate()
914 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
917 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
920 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
1028 calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))
1052 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
2308 MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2309 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2317 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2318 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
[all …]
H A Dreg.h68 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
78 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
H A Ddisplay.c61 pipe = PIPE_A; in get_edp_pipe()
92 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
644 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
650 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
H A Dcmd_parser.c1297 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1299 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1353 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
1366 info->pipe = PIPE_A; in skl_decode_mi_display_flip()

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