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Searched refs:PIPE0_DMIF_BUFFER_CONTROL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.h247 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
248 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
275 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
276 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
/linux/drivers/gpu/drm/radeon/
H A Dsid.h328 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
H A Dcikd.h440 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
H A Devergreend.h1216 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
H A Dsi.c1983 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
1986 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
H A Dcik.c8855 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
8858 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v10_0.c633 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); in dce_v10_0_line_buffer_adjust()
638 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v10_0_line_buffer_adjust()