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Searched refs:PIC32_CLR (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/tty/serial/
H A Dpic32_uart.c154 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), in pic32_uart_set_mctrl()
211 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_stop_tx()
235 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_stop_rx()
251 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_break_ctl()
289 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_do_rx()
444 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_dsbl_and_mask()
446 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), in pic32_uart_dsbl_and_mask()
543 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_startup()
547 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_startup()
615 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), in pic32_uart_set_termios()
[all …]
/linux/drivers/irqchip/
H A Dirq-pic32-evic.c67 writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON)); in pic32_set_ext_polarity()
113 evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10)); in pic32_set_irq_priority()
151 iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10); in pic32_irq_domain_map()
152 ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10); in pic32_irq_domain_map()
255 u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10)); in pic32_of_init()
/linux/drivers/rtc/
H A Drtc-pic32.c106 PIC32_CLR(PIC32_RTCALRM))); in pic32_rtc_setaie()
122 writel(PIC32_RTCALRM_AMASK, base + PIC32_CLR(PIC32_RTCALRM)); in pic32_rtc_setfreq()
273 writel(PIC32_RTCCON_ON, base + PIC32_CLR(PIC32_RTCCON)); in pic32_rtc_enable()
278 writel(3 << 9, base + PIC32_CLR(PIC32_RTCCON)); in pic32_rtc_enable()
/linux/drivers/watchdog/
H A Dpic32-dmt.c53 writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG)); in dmt_disable()
117 writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base)); in pic32_dmt_bootstatus()
H A Dpic32-wdt.c66 writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base)); in pic32_wdt_bootstatus()
119 writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG)); in pic32_wdt_stop()
/linux/include/linux/platform_data/
H A Dpic32.h14 #define PIC32_CLR(_reg) ((_reg) + 0x04) macro
/linux/arch/mips/pic32/pic32mzda/
H A Dconfig.c111 writel(-1, PIC32_CLR(pic32_conf_base + PIC32_RCON)); in pic32_config_init()
/linux/drivers/clk/microchip/
H A Dclk-core.c115 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
267 writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg)); in roclk_disable()
525 writel(REFO_ON, PIC32_CLR(refo->ctrl_reg)); in roclk_set_rate_and_parent()
973 writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg)); in sosc_clk_disable()
/linux/drivers/pinctrl/
H A Dpinctrl-pic32.c1807 writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); in pic32_gpio_request_enable()
1839 writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); in pic32_gpio_set()
1851 writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG)); in pic32_gpio_direction_output()
1949 writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); in pic32_pinconf_set()
2011 writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); in pic32_gpio_irq_mask()
2043 writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG)); in pic32_gpio_irq_set_type()
2049 writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG)); in pic32_gpio_irq_set_type()