1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2021 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-fwnode.h>
14
15 #define OV13B10_REG_VALUE_08BIT 1
16 #define OV13B10_REG_VALUE_16BIT 2
17 #define OV13B10_REG_VALUE_24BIT 3
18
19 #define OV13B10_REG_MODE_SELECT 0x0100
20 #define OV13B10_MODE_STANDBY 0x00
21 #define OV13B10_MODE_STREAMING 0x01
22
23 #define OV13B10_REG_SOFTWARE_RST 0x0103
24 #define OV13B10_SOFTWARE_RST 0x01
25
26 /* Chip ID */
27 #define OV13B10_REG_CHIP_ID 0x300a
28 #define OV13B10_CHIP_ID 0x560d42
29
30 /* V_TIMING internal */
31 #define OV13B10_REG_VTS 0x380e
32 #define OV13B10_VTS_30FPS 0x0c7c
33 #define OV13B10_VTS_60FPS 0x063e
34 #define OV13B10_VTS_120FPS 0x0320
35 #define OV13B10_VTS_MAX 0x7fff
36
37 /* Exposure control */
38 #define OV13B10_REG_EXPOSURE 0x3500
39 #define OV13B10_EXPOSURE_MIN 4
40 #define OV13B10_EXPOSURE_STEP 1
41 #define OV13B10_EXPOSURE_DEFAULT 0x40
42
43 /* Analog gain control */
44 #define OV13B10_REG_ANALOG_GAIN 0x3508
45 #define OV13B10_ANA_GAIN_MIN 0x80
46 #define OV13B10_ANA_GAIN_MAX 0x07c0
47 #define OV13B10_ANA_GAIN_STEP 1
48 #define OV13B10_ANA_GAIN_DEFAULT 0x80
49
50 /* Digital gain control */
51 #define OV13B10_REG_DGTL_GAIN_H 0x350a
52 #define OV13B10_REG_DGTL_GAIN_M 0x350b
53 #define OV13B10_REG_DGTL_GAIN_L 0x350c
54
55 #define OV13B10_DGTL_GAIN_MIN 1024 /* Min = 1 X */
56 #define OV13B10_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */
57 #define OV13B10_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */
58 #define OV13B10_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
59
60 #define OV13B10_DGTL_GAIN_L_SHIFT 6
61 #define OV13B10_DGTL_GAIN_L_MASK 0x3
62 #define OV13B10_DGTL_GAIN_M_SHIFT 2
63 #define OV13B10_DGTL_GAIN_M_MASK 0xff
64 #define OV13B10_DGTL_GAIN_H_SHIFT 10
65 #define OV13B10_DGTL_GAIN_H_MASK 0x3
66
67 /* Test Pattern Control */
68 #define OV13B10_REG_TEST_PATTERN 0x5080
69 #define OV13B10_TEST_PATTERN_ENABLE BIT(7)
70 #define OV13B10_TEST_PATTERN_MASK 0xf3
71 #define OV13B10_TEST_PATTERN_BAR_SHIFT 2
72
73 /* Flip Control */
74 #define OV13B10_REG_FORMAT1 0x3820
75 #define OV13B10_REG_FORMAT2 0x3821
76
77 /* Horizontal Window Offset */
78 #define OV13B10_REG_H_WIN_OFFSET 0x3811
79
80 /* Vertical Window Offset */
81 #define OV13B10_REG_V_WIN_OFFSET 0x3813
82
83 struct ov13b10_reg {
84 u16 address;
85 u8 val;
86 };
87
88 struct ov13b10_reg_list {
89 u32 num_of_regs;
90 const struct ov13b10_reg *regs;
91 };
92
93 /* Link frequency config */
94 struct ov13b10_link_freq_config {
95 u64 link_freq;
96
97 /* registers for this link frequency */
98 struct ov13b10_reg_list reg_list;
99 };
100
101 /* Mode : resolution and related config&values */
102 struct ov13b10_mode {
103 /* Frame width */
104 u32 width;
105 /* Frame height */
106 u32 height;
107
108 /* V-timing */
109 u32 vts_def;
110 u32 vts_min;
111
112 /* Index of Link frequency config to be used */
113 u32 link_freq_index;
114
115 /* Pixels per line in current mode */
116 u32 ppl;
117
118 /* Default register values */
119 struct ov13b10_reg_list reg_list;
120 };
121
122 /* 4208x3120 needs 1120Mbps/lane, 4 lanes */
123 static const struct ov13b10_reg mipi_data_rate_1120mbps[] = {
124 {0x0103, 0x01},
125 {0x0303, 0x04},
126 {0x0305, 0xaf},
127 {0x0321, 0x00},
128 {0x0323, 0x04},
129 {0x0324, 0x01},
130 {0x0325, 0xa4},
131 {0x0326, 0x81},
132 {0x0327, 0x04},
133 {0x3012, 0x07},
134 {0x3013, 0x32},
135 {0x3107, 0x23},
136 {0x3501, 0x0c},
137 {0x3502, 0x10},
138 {0x3504, 0x08},
139 {0x3508, 0x07},
140 {0x3509, 0xc0},
141 {0x3600, 0x16},
142 {0x3601, 0x54},
143 {0x3612, 0x4e},
144 {0x3620, 0x00},
145 {0x3621, 0x68},
146 {0x3622, 0x66},
147 {0x3623, 0x03},
148 {0x3662, 0x92},
149 {0x3666, 0xbb},
150 {0x3667, 0x44},
151 {0x366e, 0xff},
152 {0x366f, 0xf3},
153 {0x3675, 0x44},
154 {0x3676, 0x00},
155 {0x367f, 0xe9},
156 {0x3681, 0x32},
157 {0x3682, 0x1f},
158 {0x3683, 0x0b},
159 {0x3684, 0x0b},
160 {0x3704, 0x0f},
161 {0x3706, 0x40},
162 {0x3708, 0x3b},
163 {0x3709, 0x72},
164 {0x370b, 0xa2},
165 {0x3714, 0x24},
166 {0x371a, 0x3e},
167 {0x3725, 0x42},
168 {0x3739, 0x12},
169 {0x3767, 0x00},
170 {0x377a, 0x0d},
171 {0x3789, 0x18},
172 {0x3790, 0x40},
173 {0x3791, 0xa2},
174 {0x37c2, 0x04},
175 {0x37c3, 0xf1},
176 {0x37d9, 0x0c},
177 {0x37da, 0x02},
178 {0x37dc, 0x02},
179 {0x37e1, 0x04},
180 {0x37e2, 0x0a},
181 {0x3800, 0x00},
182 {0x3801, 0x00},
183 {0x3802, 0x00},
184 {0x3803, 0x08},
185 {0x3804, 0x10},
186 {0x3805, 0x8f},
187 {0x3806, 0x0c},
188 {0x3807, 0x47},
189 {0x3808, 0x10},
190 {0x3809, 0x70},
191 {0x380a, 0x0c},
192 {0x380b, 0x30},
193 {0x380c, 0x04},
194 {0x380d, 0x98},
195 {0x380e, 0x0c},
196 {0x380f, 0x7c},
197 {0x3811, 0x0f},
198 {0x3813, 0x09},
199 {0x3814, 0x01},
200 {0x3815, 0x01},
201 {0x3816, 0x01},
202 {0x3817, 0x01},
203 {0x381f, 0x08},
204 {0x3820, 0x88},
205 {0x3821, 0x00},
206 {0x3822, 0x14},
207 {0x382e, 0xe6},
208 {0x3c80, 0x00},
209 {0x3c87, 0x01},
210 {0x3c8c, 0x19},
211 {0x3c8d, 0x1c},
212 {0x3ca0, 0x00},
213 {0x3ca1, 0x00},
214 {0x3ca2, 0x00},
215 {0x3ca3, 0x00},
216 {0x3ca4, 0x50},
217 {0x3ca5, 0x11},
218 {0x3ca6, 0x01},
219 {0x3ca7, 0x00},
220 {0x3ca8, 0x00},
221 {0x4008, 0x02},
222 {0x4009, 0x0f},
223 {0x400a, 0x01},
224 {0x400b, 0x19},
225 {0x4011, 0x21},
226 {0x4017, 0x08},
227 {0x4019, 0x04},
228 {0x401a, 0x58},
229 {0x4032, 0x1e},
230 {0x4050, 0x02},
231 {0x4051, 0x09},
232 {0x405e, 0x00},
233 {0x4066, 0x02},
234 {0x4501, 0x00},
235 {0x4502, 0x10},
236 {0x4505, 0x00},
237 {0x4800, 0x64},
238 {0x481b, 0x3e},
239 {0x481f, 0x30},
240 {0x4825, 0x34},
241 {0x4837, 0x0e},
242 {0x484b, 0x01},
243 {0x4883, 0x02},
244 {0x5000, 0xff},
245 {0x5001, 0x0f},
246 {0x5045, 0x20},
247 {0x5046, 0x20},
248 {0x5047, 0xa4},
249 {0x5048, 0x20},
250 {0x5049, 0xa4},
251 };
252
253 static const struct ov13b10_reg mode_4208x3120_regs[] = {
254 {0x0305, 0xaf},
255 {0x3501, 0x0c},
256 {0x3662, 0x92},
257 {0x3714, 0x24},
258 {0x3739, 0x12},
259 {0x37c2, 0x04},
260 {0x37d9, 0x0c},
261 {0x37e2, 0x0a},
262 {0x3800, 0x00},
263 {0x3801, 0x00},
264 {0x3802, 0x00},
265 {0x3803, 0x08},
266 {0x3804, 0x10},
267 {0x3805, 0x8f},
268 {0x3806, 0x0c},
269 {0x3807, 0x47},
270 {0x3808, 0x10},
271 {0x3809, 0x70},
272 {0x380a, 0x0c},
273 {0x380b, 0x30},
274 {0x380c, 0x04},
275 {0x380d, 0x98},
276 {0x380e, 0x0c},
277 {0x380f, 0x7c},
278 {0x3810, 0x00},
279 {0x3811, 0x0f},
280 {0x3812, 0x00},
281 {0x3813, 0x09},
282 {0x3814, 0x01},
283 {0x3816, 0x01},
284 {0x3820, 0x88},
285 {0x3c8c, 0x19},
286 {0x4008, 0x02},
287 {0x4009, 0x0f},
288 {0x4050, 0x02},
289 {0x4051, 0x09},
290 {0x4501, 0x00},
291 {0x4505, 0x00},
292 {0x4837, 0x0e},
293 {0x5000, 0xff},
294 {0x5001, 0x0f},
295 };
296
297 static const struct ov13b10_reg mode_4160x3120_regs[] = {
298 {0x0305, 0xaf},
299 {0x3501, 0x0c},
300 {0x3662, 0x92},
301 {0x3714, 0x24},
302 {0x3739, 0x12},
303 {0x37c2, 0x04},
304 {0x37d9, 0x0c},
305 {0x37e2, 0x0a},
306 {0x3800, 0x00},
307 {0x3801, 0x00},
308 {0x3802, 0x00},
309 {0x3803, 0x08},
310 {0x3804, 0x10},
311 {0x3805, 0x8f},
312 {0x3806, 0x0c},
313 {0x3807, 0x47},
314 {0x3808, 0x10},
315 {0x3809, 0x40},
316 {0x380a, 0x0c},
317 {0x380b, 0x30},
318 {0x380c, 0x04},
319 {0x380d, 0x98},
320 {0x380e, 0x0c},
321 {0x380f, 0x7c},
322 {0x3810, 0x00},
323 {0x3811, 0x27},
324 {0x3812, 0x00},
325 {0x3813, 0x09},
326 {0x3814, 0x01},
327 {0x3816, 0x01},
328 {0x3820, 0x88},
329 {0x3c8c, 0x19},
330 {0x4008, 0x02},
331 {0x4009, 0x0f},
332 {0x4050, 0x02},
333 {0x4051, 0x09},
334 {0x4501, 0x00},
335 {0x4505, 0x00},
336 {0x4837, 0x0e},
337 {0x5000, 0xff},
338 {0x5001, 0x0f},
339 };
340
341 static const struct ov13b10_reg mode_4160x2340_regs[] = {
342 {0x0305, 0xaf},
343 {0x3501, 0x0c},
344 {0x3662, 0x92},
345 {0x3714, 0x24},
346 {0x3739, 0x12},
347 {0x37c2, 0x04},
348 {0x37d9, 0x0c},
349 {0x37e2, 0x0a},
350 {0x3800, 0x00},
351 {0x3801, 0x00},
352 {0x3802, 0x00},
353 {0x3803, 0x08},
354 {0x3804, 0x10},
355 {0x3805, 0x8f},
356 {0x3806, 0x0c},
357 {0x3807, 0x47},
358 {0x3808, 0x10},
359 {0x3809, 0x40},
360 {0x380a, 0x09},
361 {0x380b, 0x24},
362 {0x380c, 0x04},
363 {0x380d, 0x98},
364 {0x380e, 0x0c},
365 {0x380f, 0x7c},
366 {0x3810, 0x00},
367 {0x3811, 0x27},
368 {0x3812, 0x01},
369 {0x3813, 0x8f},
370 {0x3814, 0x01},
371 {0x3816, 0x01},
372 {0x3820, 0x88},
373 {0x3c8c, 0x19},
374 {0x4008, 0x02},
375 {0x4009, 0x0f},
376 {0x4050, 0x02},
377 {0x4051, 0x09},
378 {0x4501, 0x00},
379 {0x4505, 0x00},
380 {0x4837, 0x0e},
381 {0x5000, 0xff},
382 {0x5001, 0x0f},
383 };
384
385 static const struct ov13b10_reg mode_2104x1560_regs[] = {
386 {0x0305, 0xaf},
387 {0x3501, 0x06},
388 {0x3662, 0x88},
389 {0x3714, 0x28},
390 {0x3739, 0x10},
391 {0x37c2, 0x14},
392 {0x37d9, 0x06},
393 {0x37e2, 0x0c},
394 {0x3800, 0x00},
395 {0x3801, 0x00},
396 {0x3802, 0x00},
397 {0x3803, 0x08},
398 {0x3804, 0x10},
399 {0x3805, 0x8f},
400 {0x3806, 0x0c},
401 {0x3807, 0x47},
402 {0x3808, 0x08},
403 {0x3809, 0x38},
404 {0x380a, 0x06},
405 {0x380b, 0x18},
406 {0x380c, 0x04},
407 {0x380d, 0x98},
408 {0x380e, 0x06},
409 {0x380f, 0x3e},
410 {0x3810, 0x00},
411 {0x3811, 0x07},
412 {0x3812, 0x00},
413 {0x3813, 0x05},
414 {0x3814, 0x03},
415 {0x3816, 0x03},
416 {0x3820, 0x8b},
417 {0x3c8c, 0x18},
418 {0x4008, 0x00},
419 {0x4009, 0x05},
420 {0x4050, 0x00},
421 {0x4051, 0x05},
422 {0x4501, 0x08},
423 {0x4505, 0x00},
424 {0x4837, 0x0e},
425 {0x5000, 0xfd},
426 {0x5001, 0x0d},
427 };
428
429 static const struct ov13b10_reg mode_2080x1170_regs[] = {
430 {0x0305, 0xaf},
431 {0x3501, 0x06},
432 {0x3662, 0x88},
433 {0x3714, 0x28},
434 {0x3739, 0x10},
435 {0x37c2, 0x14},
436 {0x37d9, 0x06},
437 {0x37e2, 0x0c},
438 {0x3800, 0x00},
439 {0x3801, 0x00},
440 {0x3802, 0x00},
441 {0x3803, 0x08},
442 {0x3804, 0x10},
443 {0x3805, 0x8f},
444 {0x3806, 0x0c},
445 {0x3807, 0x47},
446 {0x3808, 0x08},
447 {0x3809, 0x20},
448 {0x380a, 0x04},
449 {0x380b, 0x92},
450 {0x380c, 0x04},
451 {0x380d, 0x98},
452 {0x380e, 0x06},
453 {0x380f, 0x3e},
454 {0x3810, 0x00},
455 {0x3811, 0x13},
456 {0x3812, 0x00},
457 {0x3813, 0xc9},
458 {0x3814, 0x03},
459 {0x3816, 0x03},
460 {0x3820, 0x8b},
461 {0x3c8c, 0x18},
462 {0x4008, 0x00},
463 {0x4009, 0x05},
464 {0x4050, 0x00},
465 {0x4051, 0x05},
466 {0x4501, 0x08},
467 {0x4505, 0x00},
468 {0x4837, 0x0e},
469 {0x5000, 0xfd},
470 {0x5001, 0x0d},
471 };
472
473 static const struct ov13b10_reg mode_1364x768_120fps_regs[] = {
474 {0x0305, 0xaf},
475 {0x3011, 0x7c},
476 {0x3501, 0x03},
477 {0x3502, 0x00},
478 {0x3662, 0x88},
479 {0x3714, 0x28},
480 {0x3739, 0x10},
481 {0x37c2, 0x14},
482 {0x37d9, 0x06},
483 {0x37e2, 0x0c},
484 {0x37e4, 0x00},
485 {0x3800, 0x02},
486 {0x3801, 0xe4},
487 {0x3802, 0x03},
488 {0x3803, 0x48},
489 {0x3804, 0x0d},
490 {0x3805, 0xab},
491 {0x3806, 0x09},
492 {0x3807, 0x60},
493 {0x3808, 0x05},
494 {0x3809, 0x54},
495 {0x380a, 0x03},
496 {0x380b, 0x00},
497 {0x380c, 0x04},
498 {0x380d, 0x8e},
499 {0x380e, 0x03},
500 {0x380f, 0x20},
501 {0x3811, 0x07},
502 {0x3813, 0x07},
503 {0x3814, 0x03},
504 {0x3816, 0x03},
505 {0x3820, 0x8b},
506 {0x3c8c, 0x18},
507 {0x4008, 0x00},
508 {0x4009, 0x05},
509 {0x4050, 0x00},
510 {0x4051, 0x05},
511 {0x4501, 0x08},
512 {0x4505, 0x04},
513 {0x5000, 0xfd},
514 {0x5001, 0x0d},
515 };
516
517 static const struct ov13b10_reg mode_2lanes_2104x1560_60fps_regs[] = {
518 {0x3016, 0x32},
519 {0x3106, 0x29},
520 {0x0305, 0xaf},
521 {0x3501, 0x06},
522 {0x3662, 0x88},
523 {0x3714, 0x28},
524 {0x3739, 0x10},
525 {0x37c2, 0x14},
526 {0x37d9, 0x06},
527 {0x37e2, 0x0c},
528 {0x3800, 0x00},
529 {0x3801, 0x00},
530 {0x3802, 0x00},
531 {0x3803, 0x08},
532 {0x3804, 0x10},
533 {0x3805, 0x8f},
534 {0x3806, 0x0c},
535 {0x3807, 0x47},
536 {0x3808, 0x08},
537 {0x3809, 0x38},
538 {0x380a, 0x06},
539 {0x380b, 0x18},
540 {0x380c, 0x04},
541 {0x380d, 0x98},
542 {0x380e, 0x06},
543 {0x380f, 0x3e},
544 {0x3810, 0x00},
545 {0x3811, 0x07},
546 {0x3812, 0x00},
547 {0x3813, 0x05},
548 {0x3814, 0x03},
549 {0x3816, 0x03},
550 {0x3820, 0x8b},
551 {0x3c8c, 0x18},
552 {0x4008, 0x00},
553 {0x4009, 0x05},
554 {0x4050, 0x00},
555 {0x4051, 0x05},
556 {0x4501, 0x08},
557 {0x4505, 0x00},
558 {0x4837, 0x0e},
559 {0x5000, 0xfd},
560 {0x5001, 0x0d},
561 };
562
563 static const char * const ov13b10_test_pattern_menu[] = {
564 "Disabled",
565 "Vertical Color Bar Type 1",
566 "Vertical Color Bar Type 2",
567 "Vertical Color Bar Type 3",
568 "Vertical Color Bar Type 4"
569 };
570
571 /* Configurations for supported link frequencies */
572 #define OV13B10_LINK_FREQ_560MHZ 560000000ULL
573 #define OV13B10_LINK_FREQ_INDEX_0 0
574
575 #define OV13B10_EXT_CLK 19200000
576 #define OV13B10_4_DATA_LANES 4
577 #define OV13B10_2_DATA_LANES 2
578
579 /*
580 * pixel_rate = data_rate * nr_of_lanes / bits_per_pixel
581 * data_rate => link_freq * 2; number of lanes => 4 or 2; bits per pixel => 10
582 */
link_freq_to_pixel_rate(u64 f,u8 lanes)583 static u64 link_freq_to_pixel_rate(u64 f, u8 lanes)
584 {
585 f *= 2 * lanes;
586 do_div(f, 10);
587
588 return f;
589 }
590
591 /* Menu items for LINK_FREQ V4L2 control */
592 static const s64 link_freq_menu_items[] = {
593 OV13B10_LINK_FREQ_560MHZ
594 };
595
596 /* Link frequency configs */
597 static const struct ov13b10_link_freq_config
598 link_freq_configs[] = {
599 {
600 .link_freq = OV13B10_LINK_FREQ_560MHZ,
601 .reg_list = {
602 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1120mbps),
603 .regs = mipi_data_rate_1120mbps,
604 }
605 }
606 };
607
608 /* Mode configs */
609 static const struct ov13b10_mode supported_4_lanes_modes[] = {
610 /* 4 data lanes */
611 {
612 .width = 4208,
613 .height = 3120,
614 .vts_def = OV13B10_VTS_30FPS,
615 .vts_min = OV13B10_VTS_30FPS,
616 .ppl = 4704,
617 .reg_list = {
618 .num_of_regs = ARRAY_SIZE(mode_4208x3120_regs),
619 .regs = mode_4208x3120_regs,
620 },
621 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
622 },
623 {
624 .width = 4160,
625 .height = 3120,
626 .vts_def = OV13B10_VTS_30FPS,
627 .vts_min = OV13B10_VTS_30FPS,
628 .ppl = 4704,
629 .reg_list = {
630 .num_of_regs = ARRAY_SIZE(mode_4160x3120_regs),
631 .regs = mode_4160x3120_regs,
632 },
633 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
634 },
635 {
636 .width = 4160,
637 .height = 2340,
638 .vts_def = OV13B10_VTS_30FPS,
639 .vts_min = OV13B10_VTS_30FPS,
640 .ppl = 4704,
641 .reg_list = {
642 .num_of_regs = ARRAY_SIZE(mode_4160x2340_regs),
643 .regs = mode_4160x2340_regs,
644 },
645 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
646 },
647 {
648 .width = 2104,
649 .height = 1560,
650 .vts_def = OV13B10_VTS_60FPS,
651 .vts_min = OV13B10_VTS_60FPS,
652 .ppl = 4704,
653 .reg_list = {
654 .num_of_regs = ARRAY_SIZE(mode_2104x1560_regs),
655 .regs = mode_2104x1560_regs,
656 },
657 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
658 },
659 {
660 .width = 2080,
661 .height = 1170,
662 .vts_def = OV13B10_VTS_60FPS,
663 .vts_min = OV13B10_VTS_60FPS,
664 .ppl = 4704,
665 .reg_list = {
666 .num_of_regs = ARRAY_SIZE(mode_2080x1170_regs),
667 .regs = mode_2080x1170_regs,
668 },
669 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
670 },
671 {
672 .width = 1364,
673 .height = 768,
674 .vts_def = OV13B10_VTS_120FPS,
675 .vts_min = OV13B10_VTS_120FPS,
676 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
677 .ppl = 4664,
678 .reg_list = {
679 .num_of_regs = ARRAY_SIZE(mode_1364x768_120fps_regs),
680 .regs = mode_1364x768_120fps_regs,
681 },
682 },
683 };
684
685 static const struct ov13b10_mode supported_2_lanes_modes[] = {
686 /* 2 data lanes */
687 {
688 .width = 2104,
689 .height = 1560,
690 .vts_def = OV13B10_VTS_60FPS,
691 .vts_min = OV13B10_VTS_60FPS,
692 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
693 .ppl = 2352,
694 .reg_list = {
695 .num_of_regs =
696 ARRAY_SIZE(mode_2lanes_2104x1560_60fps_regs),
697 .regs = mode_2lanes_2104x1560_60fps_regs,
698 },
699 },
700 };
701
702 struct ov13b10 {
703 struct v4l2_subdev sd;
704 struct media_pad pad;
705
706 struct v4l2_ctrl_handler ctrl_handler;
707
708 struct clk *img_clk;
709 struct regulator *avdd;
710 struct gpio_desc *reset;
711
712 /* V4L2 Controls */
713 struct v4l2_ctrl *link_freq;
714 struct v4l2_ctrl *pixel_rate;
715 struct v4l2_ctrl *vblank;
716 struct v4l2_ctrl *hblank;
717 struct v4l2_ctrl *exposure;
718
719 /* Supported modes */
720 const struct ov13b10_mode *supported_modes;
721
722 /* Current mode */
723 const struct ov13b10_mode *cur_mode;
724
725 /* Mutex for serialized access */
726 struct mutex mutex;
727
728 u8 supported_modes_num;
729
730 /* Data lanes used */
731 u8 data_lanes;
732
733 /* True if the device has been identified */
734 bool identified;
735 };
736
737 #define to_ov13b10(_sd) container_of(_sd, struct ov13b10, sd)
738
739 /* Read registers up to 4 at a time */
ov13b10_read_reg(struct ov13b10 * ov13b,u16 reg,u32 len,u32 * val)740 static int ov13b10_read_reg(struct ov13b10 *ov13b,
741 u16 reg, u32 len, u32 *val)
742 {
743 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
744 struct i2c_msg msgs[2];
745 u8 *data_be_p;
746 int ret;
747 __be32 data_be = 0;
748 __be16 reg_addr_be = cpu_to_be16(reg);
749
750 if (len > 4)
751 return -EINVAL;
752
753 data_be_p = (u8 *)&data_be;
754 /* Write register address */
755 msgs[0].addr = client->addr;
756 msgs[0].flags = 0;
757 msgs[0].len = 2;
758 msgs[0].buf = (u8 *)®_addr_be;
759
760 /* Read data from register */
761 msgs[1].addr = client->addr;
762 msgs[1].flags = I2C_M_RD;
763 msgs[1].len = len;
764 msgs[1].buf = &data_be_p[4 - len];
765
766 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
767 if (ret != ARRAY_SIZE(msgs))
768 return -EIO;
769
770 *val = be32_to_cpu(data_be);
771
772 return 0;
773 }
774
775 /* Write registers up to 4 at a time */
ov13b10_write_reg(struct ov13b10 * ov13b,u16 reg,u32 len,u32 __val)776 static int ov13b10_write_reg(struct ov13b10 *ov13b,
777 u16 reg, u32 len, u32 __val)
778 {
779 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
780 int buf_i, val_i;
781 u8 buf[6], *val_p;
782 __be32 val;
783
784 if (len > 4)
785 return -EINVAL;
786
787 buf[0] = reg >> 8;
788 buf[1] = reg & 0xff;
789
790 val = cpu_to_be32(__val);
791 val_p = (u8 *)&val;
792 buf_i = 2;
793 val_i = 4 - len;
794
795 while (val_i < 4)
796 buf[buf_i++] = val_p[val_i++];
797
798 if (i2c_master_send(client, buf, len + 2) != len + 2)
799 return -EIO;
800
801 return 0;
802 }
803
804 /* Write a list of registers */
ov13b10_write_regs(struct ov13b10 * ov13b,const struct ov13b10_reg * regs,u32 len)805 static int ov13b10_write_regs(struct ov13b10 *ov13b,
806 const struct ov13b10_reg *regs, u32 len)
807 {
808 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
809 int ret;
810 u32 i;
811
812 for (i = 0; i < len; i++) {
813 ret = ov13b10_write_reg(ov13b, regs[i].address, 1,
814 regs[i].val);
815 if (ret) {
816 dev_err_ratelimited(&client->dev,
817 "Failed to write reg 0x%4.4x. error = %d\n",
818 regs[i].address, ret);
819
820 return ret;
821 }
822 }
823
824 return 0;
825 }
826
ov13b10_write_reg_list(struct ov13b10 * ov13b,const struct ov13b10_reg_list * r_list)827 static int ov13b10_write_reg_list(struct ov13b10 *ov13b,
828 const struct ov13b10_reg_list *r_list)
829 {
830 return ov13b10_write_regs(ov13b, r_list->regs, r_list->num_of_regs);
831 }
832
833 /* Open sub-device */
ov13b10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)834 static int ov13b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
835 {
836 struct ov13b10 *ov13b = to_ov13b10(sd);
837 const struct ov13b10_mode *default_mode = ov13b->supported_modes;
838 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_state_get_format(fh->state,
839 0);
840
841 mutex_lock(&ov13b->mutex);
842
843 /* Initialize try_fmt */
844 try_fmt->width = default_mode->width;
845 try_fmt->height = default_mode->height;
846 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
847 try_fmt->field = V4L2_FIELD_NONE;
848
849 /* No crop or compose */
850 mutex_unlock(&ov13b->mutex);
851
852 return 0;
853 }
854
ov13b10_update_digital_gain(struct ov13b10 * ov13b,u32 d_gain)855 static int ov13b10_update_digital_gain(struct ov13b10 *ov13b, u32 d_gain)
856 {
857 int ret;
858 u32 val;
859
860 /*
861 * 0x350C[7:6], 0x350B[7:0], 0x350A[1:0]
862 */
863
864 val = (d_gain & OV13B10_DGTL_GAIN_L_MASK) << OV13B10_DGTL_GAIN_L_SHIFT;
865 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_L,
866 OV13B10_REG_VALUE_08BIT, val);
867 if (ret)
868 return ret;
869
870 val = (d_gain >> OV13B10_DGTL_GAIN_M_SHIFT) & OV13B10_DGTL_GAIN_M_MASK;
871 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_M,
872 OV13B10_REG_VALUE_08BIT, val);
873 if (ret)
874 return ret;
875
876 val = (d_gain >> OV13B10_DGTL_GAIN_H_SHIFT) & OV13B10_DGTL_GAIN_H_MASK;
877 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_H,
878 OV13B10_REG_VALUE_08BIT, val);
879
880 return ret;
881 }
882
ov13b10_enable_test_pattern(struct ov13b10 * ov13b,u32 pattern)883 static int ov13b10_enable_test_pattern(struct ov13b10 *ov13b, u32 pattern)
884 {
885 int ret;
886 u32 val;
887
888 ret = ov13b10_read_reg(ov13b, OV13B10_REG_TEST_PATTERN,
889 OV13B10_REG_VALUE_08BIT, &val);
890 if (ret)
891 return ret;
892
893 if (pattern) {
894 val &= OV13B10_TEST_PATTERN_MASK;
895 val |= ((pattern - 1) << OV13B10_TEST_PATTERN_BAR_SHIFT) |
896 OV13B10_TEST_PATTERN_ENABLE;
897 } else {
898 val &= ~OV13B10_TEST_PATTERN_ENABLE;
899 }
900
901 return ov13b10_write_reg(ov13b, OV13B10_REG_TEST_PATTERN,
902 OV13B10_REG_VALUE_08BIT, val);
903 }
904
ov13b10_set_ctrl_hflip(struct ov13b10 * ov13b,u32 ctrl_val)905 static int ov13b10_set_ctrl_hflip(struct ov13b10 *ov13b, u32 ctrl_val)
906 {
907 int ret;
908 u32 val;
909
910 ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
911 OV13B10_REG_VALUE_08BIT, &val);
912 if (ret)
913 return ret;
914
915 ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
916 OV13B10_REG_VALUE_08BIT,
917 ctrl_val ? val & ~BIT(3) : val);
918
919 if (ret)
920 return ret;
921
922 ret = ov13b10_read_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
923 OV13B10_REG_VALUE_08BIT, &val);
924 if (ret)
925 return ret;
926
927 /*
928 * Applying cropping offset to reverse the change of Bayer order
929 * after mirroring image
930 */
931 return ov13b10_write_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
932 OV13B10_REG_VALUE_08BIT,
933 ctrl_val ? ++val : val);
934 }
935
ov13b10_set_ctrl_vflip(struct ov13b10 * ov13b,u32 ctrl_val)936 static int ov13b10_set_ctrl_vflip(struct ov13b10 *ov13b, u32 ctrl_val)
937 {
938 int ret;
939 u32 val;
940
941 ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
942 OV13B10_REG_VALUE_08BIT, &val);
943 if (ret)
944 return ret;
945
946 ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
947 OV13B10_REG_VALUE_08BIT,
948 ctrl_val ? val | BIT(4) | BIT(5) : val);
949
950 if (ret)
951 return ret;
952
953 ret = ov13b10_read_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
954 OV13B10_REG_VALUE_08BIT, &val);
955 if (ret)
956 return ret;
957
958 /*
959 * Applying cropping offset to reverse the change of Bayer order
960 * after flipping image
961 */
962 return ov13b10_write_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
963 OV13B10_REG_VALUE_08BIT,
964 ctrl_val ? --val : val);
965 }
966
ov13b10_set_ctrl(struct v4l2_ctrl * ctrl)967 static int ov13b10_set_ctrl(struct v4l2_ctrl *ctrl)
968 {
969 struct ov13b10 *ov13b = container_of(ctrl->handler,
970 struct ov13b10, ctrl_handler);
971 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
972 s64 max;
973 int ret;
974
975 /* Propagate change of current control to all related controls */
976 switch (ctrl->id) {
977 case V4L2_CID_VBLANK:
978 /* Update max exposure while meeting expected vblanking */
979 max = ov13b->cur_mode->height + ctrl->val - 8;
980 __v4l2_ctrl_modify_range(ov13b->exposure,
981 ov13b->exposure->minimum,
982 max, ov13b->exposure->step, max);
983 break;
984 }
985
986 /*
987 * Applying V4L2 control value only happens
988 * when power is up for streaming
989 */
990 if (!pm_runtime_get_if_in_use(&client->dev))
991 return 0;
992
993 ret = 0;
994 switch (ctrl->id) {
995 case V4L2_CID_ANALOGUE_GAIN:
996 ret = ov13b10_write_reg(ov13b, OV13B10_REG_ANALOG_GAIN,
997 OV13B10_REG_VALUE_16BIT,
998 ctrl->val << 1);
999 break;
1000 case V4L2_CID_DIGITAL_GAIN:
1001 ret = ov13b10_update_digital_gain(ov13b, ctrl->val);
1002 break;
1003 case V4L2_CID_EXPOSURE:
1004 ret = ov13b10_write_reg(ov13b, OV13B10_REG_EXPOSURE,
1005 OV13B10_REG_VALUE_24BIT,
1006 ctrl->val);
1007 break;
1008 case V4L2_CID_VBLANK:
1009 ret = ov13b10_write_reg(ov13b, OV13B10_REG_VTS,
1010 OV13B10_REG_VALUE_16BIT,
1011 ov13b->cur_mode->height
1012 + ctrl->val);
1013 break;
1014 case V4L2_CID_TEST_PATTERN:
1015 ret = ov13b10_enable_test_pattern(ov13b, ctrl->val);
1016 break;
1017 case V4L2_CID_HFLIP:
1018 ov13b10_set_ctrl_hflip(ov13b, ctrl->val);
1019 break;
1020 case V4L2_CID_VFLIP:
1021 ov13b10_set_ctrl_vflip(ov13b, ctrl->val);
1022 break;
1023 default:
1024 dev_info(&client->dev,
1025 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1026 ctrl->id, ctrl->val);
1027 break;
1028 }
1029
1030 pm_runtime_put(&client->dev);
1031
1032 return ret;
1033 }
1034
1035 static const struct v4l2_ctrl_ops ov13b10_ctrl_ops = {
1036 .s_ctrl = ov13b10_set_ctrl,
1037 };
1038
ov13b10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1039 static int ov13b10_enum_mbus_code(struct v4l2_subdev *sd,
1040 struct v4l2_subdev_state *sd_state,
1041 struct v4l2_subdev_mbus_code_enum *code)
1042 {
1043 /* Only one bayer order(GRBG) is supported */
1044 if (code->index > 0)
1045 return -EINVAL;
1046
1047 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1048
1049 return 0;
1050 }
1051
ov13b10_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1052 static int ov13b10_enum_frame_size(struct v4l2_subdev *sd,
1053 struct v4l2_subdev_state *sd_state,
1054 struct v4l2_subdev_frame_size_enum *fse)
1055 {
1056 struct ov13b10 *ov13b = to_ov13b10(sd);
1057 const struct ov13b10_mode *supported_modes = ov13b->supported_modes;
1058
1059 if (fse->index >= ov13b->supported_modes_num)
1060 return -EINVAL;
1061
1062 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1063 return -EINVAL;
1064
1065 fse->min_width = supported_modes[fse->index].width;
1066 fse->max_width = fse->min_width;
1067 fse->min_height = supported_modes[fse->index].height;
1068 fse->max_height = fse->min_height;
1069
1070 return 0;
1071 }
1072
ov13b10_update_pad_format(const struct ov13b10_mode * mode,struct v4l2_subdev_format * fmt)1073 static void ov13b10_update_pad_format(const struct ov13b10_mode *mode,
1074 struct v4l2_subdev_format *fmt)
1075 {
1076 fmt->format.width = mode->width;
1077 fmt->format.height = mode->height;
1078 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1079 fmt->format.field = V4L2_FIELD_NONE;
1080 }
1081
ov13b10_do_get_pad_format(struct ov13b10 * ov13b,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1082 static int ov13b10_do_get_pad_format(struct ov13b10 *ov13b,
1083 struct v4l2_subdev_state *sd_state,
1084 struct v4l2_subdev_format *fmt)
1085 {
1086 struct v4l2_mbus_framefmt *framefmt;
1087
1088 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1089 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1090 fmt->format = *framefmt;
1091 } else {
1092 ov13b10_update_pad_format(ov13b->cur_mode, fmt);
1093 }
1094
1095 return 0;
1096 }
1097
ov13b10_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1098 static int ov13b10_get_pad_format(struct v4l2_subdev *sd,
1099 struct v4l2_subdev_state *sd_state,
1100 struct v4l2_subdev_format *fmt)
1101 {
1102 struct ov13b10 *ov13b = to_ov13b10(sd);
1103 int ret;
1104
1105 mutex_lock(&ov13b->mutex);
1106 ret = ov13b10_do_get_pad_format(ov13b, sd_state, fmt);
1107 mutex_unlock(&ov13b->mutex);
1108
1109 return ret;
1110 }
1111
1112 static int
ov13b10_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1113 ov13b10_set_pad_format(struct v4l2_subdev *sd,
1114 struct v4l2_subdev_state *sd_state,
1115 struct v4l2_subdev_format *fmt)
1116 {
1117 struct ov13b10 *ov13b = to_ov13b10(sd);
1118 const struct ov13b10_mode *mode;
1119 const struct ov13b10_mode *supported_modes = ov13b->supported_modes;
1120 struct v4l2_mbus_framefmt *framefmt;
1121 s32 vblank_def;
1122 s32 vblank_min;
1123 s64 h_blank;
1124 s64 pixel_rate;
1125 s64 link_freq;
1126
1127 mutex_lock(&ov13b->mutex);
1128
1129 /* Only one raw bayer(GRBG) order is supported */
1130 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1131 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1132
1133 mode = v4l2_find_nearest_size(supported_modes,
1134 ov13b->supported_modes_num,
1135 width, height,
1136 fmt->format.width, fmt->format.height);
1137 ov13b10_update_pad_format(mode, fmt);
1138 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1139 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1140 *framefmt = fmt->format;
1141 } else {
1142 ov13b->cur_mode = mode;
1143 __v4l2_ctrl_s_ctrl(ov13b->link_freq, mode->link_freq_index);
1144 link_freq = link_freq_menu_items[mode->link_freq_index];
1145 pixel_rate = link_freq_to_pixel_rate(link_freq,
1146 ov13b->data_lanes);
1147 __v4l2_ctrl_s_ctrl_int64(ov13b->pixel_rate, pixel_rate);
1148
1149 /* Update limits and set FPS to default */
1150 vblank_def = mode->vts_def - mode->height;
1151 vblank_min = mode->vts_min - mode->height;
1152 __v4l2_ctrl_modify_range(ov13b->vblank, vblank_min,
1153 OV13B10_VTS_MAX - mode->height,
1154 1, vblank_def);
1155 __v4l2_ctrl_s_ctrl(ov13b->vblank, vblank_def);
1156 h_blank = mode->ppl - mode->width;
1157 __v4l2_ctrl_modify_range(ov13b->hblank, h_blank,
1158 h_blank, 1, h_blank);
1159 }
1160
1161 mutex_unlock(&ov13b->mutex);
1162
1163 return 0;
1164 }
1165
1166 /* Verify chip ID */
ov13b10_identify_module(struct ov13b10 * ov13b)1167 static int ov13b10_identify_module(struct ov13b10 *ov13b)
1168 {
1169 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1170 int ret;
1171 u32 val;
1172
1173 if (ov13b->identified)
1174 return 0;
1175
1176 ret = ov13b10_read_reg(ov13b, OV13B10_REG_CHIP_ID,
1177 OV13B10_REG_VALUE_24BIT, &val);
1178 if (ret)
1179 return ret;
1180
1181 if (val != OV13B10_CHIP_ID) {
1182 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1183 OV13B10_CHIP_ID, val);
1184 return -EIO;
1185 }
1186
1187 ov13b->identified = true;
1188
1189 return 0;
1190 }
1191
ov13b10_power_off(struct device * dev)1192 static int ov13b10_power_off(struct device *dev)
1193 {
1194 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1195 struct ov13b10 *ov13b10 = to_ov13b10(sd);
1196
1197 gpiod_set_value_cansleep(ov13b10->reset, 1);
1198
1199 if (ov13b10->avdd)
1200 regulator_disable(ov13b10->avdd);
1201
1202 clk_disable_unprepare(ov13b10->img_clk);
1203
1204 return 0;
1205 }
1206
ov13b10_power_on(struct device * dev)1207 static int ov13b10_power_on(struct device *dev)
1208 {
1209 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1210 struct ov13b10 *ov13b10 = to_ov13b10(sd);
1211 int ret;
1212
1213 ret = clk_prepare_enable(ov13b10->img_clk);
1214 if (ret < 0) {
1215 dev_err(dev, "failed to enable imaging clock: %d", ret);
1216 return ret;
1217 }
1218
1219 if (ov13b10->avdd) {
1220 ret = regulator_enable(ov13b10->avdd);
1221 if (ret < 0) {
1222 dev_err(dev, "failed to enable avdd: %d", ret);
1223 clk_disable_unprepare(ov13b10->img_clk);
1224 return ret;
1225 }
1226 }
1227
1228 gpiod_set_value_cansleep(ov13b10->reset, 0);
1229 /* 5ms to wait ready after XSHUTDN assert */
1230 usleep_range(5000, 5500);
1231
1232 return 0;
1233 }
1234
ov13b10_start_streaming(struct ov13b10 * ov13b)1235 static int ov13b10_start_streaming(struct ov13b10 *ov13b)
1236 {
1237 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1238 const struct ov13b10_reg_list *reg_list;
1239 int ret, link_freq_index;
1240
1241 ret = ov13b10_identify_module(ov13b);
1242 if (ret)
1243 return ret;
1244
1245 /* Get out of from software reset */
1246 ret = ov13b10_write_reg(ov13b, OV13B10_REG_SOFTWARE_RST,
1247 OV13B10_REG_VALUE_08BIT, OV13B10_SOFTWARE_RST);
1248 if (ret) {
1249 dev_err(&client->dev, "%s failed to set powerup registers\n",
1250 __func__);
1251 return ret;
1252 }
1253
1254 link_freq_index = ov13b->cur_mode->link_freq_index;
1255 reg_list = &link_freq_configs[link_freq_index].reg_list;
1256 ret = ov13b10_write_reg_list(ov13b, reg_list);
1257 if (ret) {
1258 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1259 return ret;
1260 }
1261
1262 /* Apply default values of current mode */
1263 reg_list = &ov13b->cur_mode->reg_list;
1264 ret = ov13b10_write_reg_list(ov13b, reg_list);
1265 if (ret) {
1266 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1267 return ret;
1268 }
1269
1270 /* Apply customized values from user */
1271 ret = __v4l2_ctrl_handler_setup(ov13b->sd.ctrl_handler);
1272 if (ret)
1273 return ret;
1274
1275 return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1276 OV13B10_REG_VALUE_08BIT,
1277 OV13B10_MODE_STREAMING);
1278 }
1279
1280 /* Stop streaming */
ov13b10_stop_streaming(struct ov13b10 * ov13b)1281 static int ov13b10_stop_streaming(struct ov13b10 *ov13b)
1282 {
1283 return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1284 OV13B10_REG_VALUE_08BIT, OV13B10_MODE_STANDBY);
1285 }
1286
ov13b10_set_stream(struct v4l2_subdev * sd,int enable)1287 static int ov13b10_set_stream(struct v4l2_subdev *sd, int enable)
1288 {
1289 struct ov13b10 *ov13b = to_ov13b10(sd);
1290 struct i2c_client *client = v4l2_get_subdevdata(sd);
1291 int ret = 0;
1292
1293 mutex_lock(&ov13b->mutex);
1294
1295 if (enable) {
1296 ret = pm_runtime_resume_and_get(&client->dev);
1297 if (ret < 0)
1298 goto err_unlock;
1299
1300 /*
1301 * Apply default & customized values
1302 * and then start streaming.
1303 */
1304 ret = ov13b10_start_streaming(ov13b);
1305 if (ret)
1306 goto err_rpm_put;
1307 } else {
1308 ov13b10_stop_streaming(ov13b);
1309 pm_runtime_put(&client->dev);
1310 }
1311
1312 mutex_unlock(&ov13b->mutex);
1313
1314 return ret;
1315
1316 err_rpm_put:
1317 pm_runtime_put(&client->dev);
1318 err_unlock:
1319 mutex_unlock(&ov13b->mutex);
1320
1321 return ret;
1322 }
1323
ov13b10_suspend(struct device * dev)1324 static int ov13b10_suspend(struct device *dev)
1325 {
1326 ov13b10_power_off(dev);
1327
1328 return 0;
1329 }
1330
ov13b10_resume(struct device * dev)1331 static int ov13b10_resume(struct device *dev)
1332 {
1333 return ov13b10_power_on(dev);
1334 }
1335
1336 static const struct v4l2_subdev_video_ops ov13b10_video_ops = {
1337 .s_stream = ov13b10_set_stream,
1338 };
1339
1340 static const struct v4l2_subdev_pad_ops ov13b10_pad_ops = {
1341 .enum_mbus_code = ov13b10_enum_mbus_code,
1342 .get_fmt = ov13b10_get_pad_format,
1343 .set_fmt = ov13b10_set_pad_format,
1344 .enum_frame_size = ov13b10_enum_frame_size,
1345 };
1346
1347 static const struct v4l2_subdev_ops ov13b10_subdev_ops = {
1348 .video = &ov13b10_video_ops,
1349 .pad = &ov13b10_pad_ops,
1350 };
1351
1352 static const struct media_entity_operations ov13b10_subdev_entity_ops = {
1353 .link_validate = v4l2_subdev_link_validate,
1354 };
1355
1356 static const struct v4l2_subdev_internal_ops ov13b10_internal_ops = {
1357 .open = ov13b10_open,
1358 };
1359
1360 /* Initialize control handlers */
ov13b10_init_controls(struct ov13b10 * ov13b)1361 static int ov13b10_init_controls(struct ov13b10 *ov13b)
1362 {
1363 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1364 struct v4l2_fwnode_device_properties props;
1365 struct v4l2_ctrl_handler *ctrl_hdlr;
1366 s64 exposure_max;
1367 s64 vblank_def;
1368 s64 vblank_min;
1369 s64 hblank;
1370 s64 pixel_rate_min;
1371 s64 pixel_rate_max;
1372 const struct ov13b10_mode *mode;
1373 u32 max;
1374 int ret;
1375
1376 ctrl_hdlr = &ov13b->ctrl_handler;
1377 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1378 if (ret)
1379 return ret;
1380
1381 mutex_init(&ov13b->mutex);
1382 ctrl_hdlr->lock = &ov13b->mutex;
1383 max = ARRAY_SIZE(link_freq_menu_items) - 1;
1384 ov13b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1385 &ov13b10_ctrl_ops,
1386 V4L2_CID_LINK_FREQ,
1387 max,
1388 0,
1389 link_freq_menu_items);
1390 if (ov13b->link_freq)
1391 ov13b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1392
1393 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0],
1394 ov13b->data_lanes);
1395 pixel_rate_min = 0;
1396 /* By default, PIXEL_RATE is read only */
1397 ov13b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1398 V4L2_CID_PIXEL_RATE,
1399 pixel_rate_min, pixel_rate_max,
1400 1, pixel_rate_max);
1401
1402 mode = ov13b->cur_mode;
1403 vblank_def = mode->vts_def - mode->height;
1404 vblank_min = mode->vts_min - mode->height;
1405 ov13b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1406 V4L2_CID_VBLANK,
1407 vblank_min,
1408 OV13B10_VTS_MAX - mode->height, 1,
1409 vblank_def);
1410
1411 hblank = mode->ppl - mode->width;
1412 ov13b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1413 V4L2_CID_HBLANK,
1414 hblank, hblank, 1, hblank);
1415 if (ov13b->hblank)
1416 ov13b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1417
1418 exposure_max = mode->vts_def - 8;
1419 ov13b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1420 V4L2_CID_EXPOSURE,
1421 OV13B10_EXPOSURE_MIN,
1422 exposure_max, OV13B10_EXPOSURE_STEP,
1423 exposure_max);
1424
1425 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1426 OV13B10_ANA_GAIN_MIN, OV13B10_ANA_GAIN_MAX,
1427 OV13B10_ANA_GAIN_STEP, OV13B10_ANA_GAIN_DEFAULT);
1428
1429 /* Digital gain */
1430 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1431 OV13B10_DGTL_GAIN_MIN, OV13B10_DGTL_GAIN_MAX,
1432 OV13B10_DGTL_GAIN_STEP, OV13B10_DGTL_GAIN_DEFAULT);
1433
1434 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13b10_ctrl_ops,
1435 V4L2_CID_TEST_PATTERN,
1436 ARRAY_SIZE(ov13b10_test_pattern_menu) - 1,
1437 0, 0, ov13b10_test_pattern_menu);
1438
1439 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1440 V4L2_CID_HFLIP, 0, 1, 1, 0);
1441 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1442 V4L2_CID_VFLIP, 0, 1, 1, 0);
1443
1444 if (ctrl_hdlr->error) {
1445 ret = ctrl_hdlr->error;
1446 dev_err(&client->dev, "%s control init failed (%d)\n",
1447 __func__, ret);
1448 goto error;
1449 }
1450
1451 ret = v4l2_fwnode_device_parse(&client->dev, &props);
1452 if (ret)
1453 goto error;
1454
1455 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13b10_ctrl_ops,
1456 &props);
1457 if (ret)
1458 goto error;
1459
1460 ov13b->sd.ctrl_handler = ctrl_hdlr;
1461
1462 return 0;
1463
1464 error:
1465 v4l2_ctrl_handler_free(ctrl_hdlr);
1466 mutex_destroy(&ov13b->mutex);
1467
1468 return ret;
1469 }
1470
ov13b10_free_controls(struct ov13b10 * ov13b)1471 static void ov13b10_free_controls(struct ov13b10 *ov13b)
1472 {
1473 v4l2_ctrl_handler_free(ov13b->sd.ctrl_handler);
1474 mutex_destroy(&ov13b->mutex);
1475 }
1476
ov13b10_get_pm_resources(struct device * dev)1477 static int ov13b10_get_pm_resources(struct device *dev)
1478 {
1479 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1480 struct ov13b10 *ov13b = to_ov13b10(sd);
1481 int ret;
1482
1483 ov13b->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1484 if (IS_ERR(ov13b->reset))
1485 return dev_err_probe(dev, PTR_ERR(ov13b->reset),
1486 "failed to get reset gpio\n");
1487
1488 ov13b->img_clk = devm_clk_get_optional(dev, NULL);
1489 if (IS_ERR(ov13b->img_clk))
1490 return dev_err_probe(dev, PTR_ERR(ov13b->img_clk),
1491 "failed to get imaging clock\n");
1492
1493 ov13b->avdd = devm_regulator_get_optional(dev, "avdd");
1494 if (IS_ERR(ov13b->avdd)) {
1495 ret = PTR_ERR(ov13b->avdd);
1496 ov13b->avdd = NULL;
1497 if (ret != -ENODEV)
1498 return dev_err_probe(dev, ret,
1499 "failed to get avdd regulator\n");
1500 }
1501
1502 return 0;
1503 }
1504
ov13b10_check_hwcfg(struct device * dev,struct ov13b10 * ov13b)1505 static int ov13b10_check_hwcfg(struct device *dev, struct ov13b10 *ov13b)
1506 {
1507 struct v4l2_fwnode_endpoint bus_cfg = {
1508 .bus_type = V4L2_MBUS_CSI2_DPHY
1509 };
1510 struct fwnode_handle *ep;
1511 struct fwnode_handle *fwnode = dev_fwnode(dev);
1512 unsigned int i, j;
1513 int ret;
1514 u32 ext_clk;
1515 u8 dlane;
1516
1517 if (!fwnode)
1518 return -ENXIO;
1519
1520 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1521 if (!ep)
1522 return -EPROBE_DEFER;
1523
1524 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1525 &ext_clk);
1526 if (ret) {
1527 dev_err(dev, "can't get clock frequency");
1528 return ret;
1529 }
1530
1531 if (ext_clk != OV13B10_EXT_CLK) {
1532 dev_err(dev, "external clock %d is not supported",
1533 ext_clk);
1534 return -EINVAL;
1535 }
1536
1537 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1538 fwnode_handle_put(ep);
1539 if (ret)
1540 return ret;
1541
1542 dlane = bus_cfg.bus.mipi_csi2.num_data_lanes;
1543 switch (dlane) {
1544 case OV13B10_4_DATA_LANES:
1545 ov13b->supported_modes = supported_4_lanes_modes;
1546 ov13b->supported_modes_num =
1547 ARRAY_SIZE(supported_4_lanes_modes);
1548 break;
1549
1550 case OV13B10_2_DATA_LANES:
1551 ov13b->supported_modes = supported_2_lanes_modes;
1552 ov13b->supported_modes_num =
1553 ARRAY_SIZE(supported_2_lanes_modes);
1554 break;
1555
1556 default:
1557 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1558 dlane);
1559 ret = -EINVAL;
1560 goto out_err;
1561 }
1562
1563 ov13b->data_lanes = dlane;
1564 ov13b->cur_mode = ov13b->supported_modes;
1565 dev_dbg(dev, "%u lanes with %u modes selected\n",
1566 ov13b->data_lanes, ov13b->supported_modes_num);
1567
1568 if (!bus_cfg.nr_of_link_frequencies) {
1569 dev_err(dev, "no link frequencies defined");
1570 ret = -EINVAL;
1571 goto out_err;
1572 }
1573
1574 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1575 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1576 if (link_freq_menu_items[i] ==
1577 bus_cfg.link_frequencies[j])
1578 break;
1579 }
1580
1581 if (j == bus_cfg.nr_of_link_frequencies) {
1582 dev_err(dev, "no link frequency %lld supported",
1583 link_freq_menu_items[i]);
1584 ret = -EINVAL;
1585 goto out_err;
1586 }
1587 }
1588
1589 out_err:
1590 v4l2_fwnode_endpoint_free(&bus_cfg);
1591
1592 return ret;
1593 }
1594
ov13b10_probe(struct i2c_client * client)1595 static int ov13b10_probe(struct i2c_client *client)
1596 {
1597 struct ov13b10 *ov13b;
1598 bool full_power;
1599 int ret;
1600
1601 ov13b = devm_kzalloc(&client->dev, sizeof(*ov13b), GFP_KERNEL);
1602 if (!ov13b)
1603 return -ENOMEM;
1604
1605 /* Check HW config */
1606 ret = ov13b10_check_hwcfg(&client->dev, ov13b);
1607 if (ret) {
1608 dev_err(&client->dev, "failed to check hwcfg: %d", ret);
1609 return ret;
1610 }
1611
1612 /* Initialize subdev */
1613 v4l2_i2c_subdev_init(&ov13b->sd, client, &ov13b10_subdev_ops);
1614
1615 ret = ov13b10_get_pm_resources(&client->dev);
1616 if (ret)
1617 return ret;
1618
1619 full_power = acpi_dev_state_d0(&client->dev);
1620 if (full_power) {
1621 ret = ov13b10_power_on(&client->dev);
1622 if (ret) {
1623 dev_err(&client->dev, "failed to power on\n");
1624 return ret;
1625 }
1626
1627 /* Check module identity */
1628 ret = ov13b10_identify_module(ov13b);
1629 if (ret) {
1630 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1631 goto error_power_off;
1632 }
1633 }
1634
1635 ret = ov13b10_init_controls(ov13b);
1636 if (ret)
1637 goto error_power_off;
1638
1639 /* Initialize subdev */
1640 ov13b->sd.internal_ops = &ov13b10_internal_ops;
1641 ov13b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1642 ov13b->sd.entity.ops = &ov13b10_subdev_entity_ops;
1643 ov13b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1644
1645 /* Initialize source pad */
1646 ov13b->pad.flags = MEDIA_PAD_FL_SOURCE;
1647 ret = media_entity_pads_init(&ov13b->sd.entity, 1, &ov13b->pad);
1648 if (ret) {
1649 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1650 goto error_handler_free;
1651 }
1652
1653
1654 /*
1655 * Device is already turned on by i2c-core with ACPI domain PM.
1656 * Enable runtime PM and turn off the device.
1657 */
1658 /* Set the device's state to active if it's in D0 state. */
1659 if (full_power)
1660 pm_runtime_set_active(&client->dev);
1661 pm_runtime_enable(&client->dev);
1662 pm_runtime_idle(&client->dev);
1663
1664 ret = v4l2_async_register_subdev_sensor(&ov13b->sd);
1665 if (ret < 0)
1666 goto error_media_entity_runtime_pm;
1667
1668 return 0;
1669
1670 error_media_entity_runtime_pm:
1671 pm_runtime_disable(&client->dev);
1672 if (full_power)
1673 pm_runtime_set_suspended(&client->dev);
1674 media_entity_cleanup(&ov13b->sd.entity);
1675
1676 error_handler_free:
1677 ov13b10_free_controls(ov13b);
1678 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1679
1680 error_power_off:
1681 ov13b10_power_off(&client->dev);
1682
1683 return ret;
1684 }
1685
ov13b10_remove(struct i2c_client * client)1686 static void ov13b10_remove(struct i2c_client *client)
1687 {
1688 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1689 struct ov13b10 *ov13b = to_ov13b10(sd);
1690
1691 v4l2_async_unregister_subdev(sd);
1692 media_entity_cleanup(&sd->entity);
1693 ov13b10_free_controls(ov13b);
1694
1695 pm_runtime_disable(&client->dev);
1696 pm_runtime_set_suspended(&client->dev);
1697 }
1698
1699 static DEFINE_RUNTIME_DEV_PM_OPS(ov13b10_pm_ops, ov13b10_suspend,
1700 ov13b10_resume, NULL);
1701
1702 #ifdef CONFIG_ACPI
1703 static const struct acpi_device_id ov13b10_acpi_ids[] = {
1704 {"OVTIDB10"},
1705 {"OVTI13B1"},
1706 { /* sentinel */ }
1707 };
1708
1709 MODULE_DEVICE_TABLE(acpi, ov13b10_acpi_ids);
1710 #endif
1711
1712 static struct i2c_driver ov13b10_i2c_driver = {
1713 .driver = {
1714 .name = "ov13b10",
1715 .pm = pm_ptr(&ov13b10_pm_ops),
1716 .acpi_match_table = ACPI_PTR(ov13b10_acpi_ids),
1717 },
1718 .probe = ov13b10_probe,
1719 .remove = ov13b10_remove,
1720 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1721 };
1722
1723 module_i2c_driver(ov13b10_i2c_driver);
1724
1725 MODULE_AUTHOR("Kao, Arec <arec.kao@intel.com>");
1726 MODULE_DESCRIPTION("Omnivision ov13b10 sensor driver");
1727 MODULE_LICENSE("GPL v2");
1728