1 // SPDX-License-Identifier: GPL-2.0 2 3 #[repr(C)] 4 #[derive(Default)] 5 pub struct __IncompleteArrayField<T>(::core::marker::PhantomData<T>, [T; 0]); 6 impl<T> __IncompleteArrayField<T> { 7 #[inline] 8 pub const fn new() -> Self { 9 __IncompleteArrayField(::core::marker::PhantomData, []) 10 } 11 #[inline] 12 pub fn as_ptr(&self) -> *const T { 13 self as *const _ as *const T 14 } 15 #[inline] 16 pub fn as_mut_ptr(&mut self) -> *mut T { 17 self as *mut _ as *mut T 18 } 19 #[inline] 20 pub unsafe fn as_slice(&self, len: usize) -> &[T] { 21 ::core::slice::from_raw_parts(self.as_ptr(), len) 22 } 23 #[inline] 24 pub unsafe fn as_mut_slice(&mut self, len: usize) -> &mut [T] { 25 ::core::slice::from_raw_parts_mut(self.as_mut_ptr(), len) 26 } 27 } 28 impl<T> ::core::fmt::Debug for __IncompleteArrayField<T> { 29 fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result { 30 fmt.write_str("__IncompleteArrayField") 31 } 32 } 33 pub const NV_VGPU_MSG_SIGNATURE_VALID: u32 = 1129337430; 34 pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2: u32 = 0; 35 pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL: u32 = 23068672; 36 pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X: u32 = 8388608; 37 pub const GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB: u32 = 98304; 38 pub const GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE: u32 = 100663296; 39 pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB: u32 = 64; 40 pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB: u32 = 256; 41 pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB: u32 = 88; 42 pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB: u32 = 280; 43 pub const GSP_FW_WPR_META_REVISION: u32 = 1; 44 pub const GSP_FW_WPR_META_MAGIC: i64 = -2577556379034558285; 45 pub const REGISTRY_TABLE_ENTRY_TYPE_DWORD: u32 = 1; 46 pub const GSP_MSG_QUEUE_ELEMENT_SIZE_MAX: u32 = 65536; 47 pub type __u8 = ffi::c_uchar; 48 pub type __u16 = ffi::c_ushort; 49 pub type __u32 = ffi::c_uint; 50 pub type __u64 = ffi::c_ulonglong; 51 pub type u8_ = __u8; 52 pub type u16_ = __u16; 53 pub type u32_ = __u32; 54 pub type u64_ = __u64; 55 pub const NV_VGPU_MSG_FUNCTION_NOP: _bindgen_ty_2 = 0; 56 pub const NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO: _bindgen_ty_2 = 1; 57 pub const NV_VGPU_MSG_FUNCTION_ALLOC_ROOT: _bindgen_ty_2 = 2; 58 pub const NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE: _bindgen_ty_2 = 3; 59 pub const NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY: _bindgen_ty_2 = 4; 60 pub const NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA: _bindgen_ty_2 = 5; 61 pub const NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA: _bindgen_ty_2 = 6; 62 pub const NV_VGPU_MSG_FUNCTION_MAP_MEMORY: _bindgen_ty_2 = 7; 63 pub const NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA: _bindgen_ty_2 = 8; 64 pub const NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT: _bindgen_ty_2 = 9; 65 pub const NV_VGPU_MSG_FUNCTION_FREE: _bindgen_ty_2 = 10; 66 pub const NV_VGPU_MSG_FUNCTION_LOG: _bindgen_ty_2 = 11; 67 pub const NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM: _bindgen_ty_2 = 12; 68 pub const NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY: _bindgen_ty_2 = 13; 69 pub const NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA: _bindgen_ty_2 = 14; 70 pub const NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA: _bindgen_ty_2 = 15; 71 pub const NV_VGPU_MSG_FUNCTION_GET_EDID: _bindgen_ty_2 = 16; 72 pub const NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL: _bindgen_ty_2 = 17; 73 pub const NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT: _bindgen_ty_2 = 18; 74 pub const NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE: _bindgen_ty_2 = 19; 75 pub const NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY: _bindgen_ty_2 = 20; 76 pub const NV_VGPU_MSG_FUNCTION_DUP_OBJECT: _bindgen_ty_2 = 21; 77 pub const NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS: _bindgen_ty_2 = 22; 78 pub const NV_VGPU_MSG_FUNCTION_ALLOC_EVENT: _bindgen_ty_2 = 23; 79 pub const NV_VGPU_MSG_FUNCTION_SEND_EVENT: _bindgen_ty_2 = 24; 80 pub const NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL: _bindgen_ty_2 = 25; 81 pub const NV_VGPU_MSG_FUNCTION_DMA_CONTROL: _bindgen_ty_2 = 26; 82 pub const NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM: _bindgen_ty_2 = 27; 83 pub const NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE: _bindgen_ty_2 = 28; 84 pub const NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA: _bindgen_ty_2 = 29; 85 pub const NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT: _bindgen_ty_2 = 30; 86 pub const NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT: _bindgen_ty_2 = 31; 87 pub const NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE: _bindgen_ty_2 = 32; 88 pub const NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL: _bindgen_ty_2 = 33; 89 pub const NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API: _bindgen_ty_2 = 34; 90 pub const NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ: _bindgen_ty_2 = 35; 91 pub const NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE: _bindgen_ty_2 = 36; 92 pub const NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA: _bindgen_ty_2 = 37; 93 pub const NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT: _bindgen_ty_2 = 38; 94 pub const NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO: _bindgen_ty_2 = 39; 95 pub const NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE: _bindgen_ty_2 = 40; 96 pub const NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO: _bindgen_ty_2 = 41; 97 pub const NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO: _bindgen_ty_2 = 42; 98 pub const NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY: _bindgen_ty_2 = 43; 99 pub const NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY: _bindgen_ty_2 = 44; 100 pub const NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES: _bindgen_ty_2 = 45; 101 pub const NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE: _bindgen_ty_2 = 46; 102 pub const NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER: _bindgen_ty_2 = 47; 103 pub const NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE: _bindgen_ty_2 = 48; 104 pub const NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA: _bindgen_ty_2 = 49; 105 pub const NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS: _bindgen_ty_2 = 50; 106 pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO: _bindgen_ty_2 = 51; 107 pub const NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM: _bindgen_ty_2 = 52; 108 pub const NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2: _bindgen_ty_2 = 53; 109 pub const NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY: _bindgen_ty_2 = 54; 110 pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO: _bindgen_ty_2 = 55; 111 pub const NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES: _bindgen_ty_2 = 56; 112 pub const NV_VGPU_MSG_FUNCTION_RESERVED_57: _bindgen_ty_2 = 57; 113 pub const NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT: _bindgen_ty_2 = 58; 114 pub const NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE: _bindgen_ty_2 = 59; 115 pub const NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION: _bindgen_ty_2 = 60; 116 pub const NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES: _bindgen_ty_2 = 61; 117 pub const NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY: _bindgen_ty_2 = 62; 118 pub const NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32: _bindgen_ty_2 = 63; 119 pub const NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT: _bindgen_ty_2 = 64; 120 pub const NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO: _bindgen_ty_2 = 65; 121 pub const NV_VGPU_MSG_FUNCTION_RMFS_INIT: _bindgen_ty_2 = 66; 122 pub const NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE: _bindgen_ty_2 = 67; 123 pub const NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP: _bindgen_ty_2 = 68; 124 pub const NV_VGPU_MSG_FUNCTION_RMFS_TEST: _bindgen_ty_2 = 69; 125 pub const NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE: _bindgen_ty_2 = 70; 126 pub const NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD: _bindgen_ty_2 = 71; 127 pub const NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO: _bindgen_ty_2 = 72; 128 pub const NV_VGPU_MSG_FUNCTION_SET_REGISTRY: _bindgen_ty_2 = 73; 129 pub const NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU: _bindgen_ty_2 = 74; 130 pub const NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION: _bindgen_ty_2 = 75; 131 pub const NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: _bindgen_ty_2 = 76; 132 pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2: _bindgen_ty_2 = 77; 133 pub const NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT: _bindgen_ty_2 = 78; 134 pub const NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY: _bindgen_ty_2 = 79; 135 pub const NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO: _bindgen_ty_2 = 80; 136 pub const NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER: _bindgen_ty_2 = 81; 137 pub const NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER: _bindgen_ty_2 = 82; 138 pub const NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER: _bindgen_ty_2 = 83; 139 pub const NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER: _bindgen_ty_2 = 84; 140 pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE: _bindgen_ty_2 = 85; 141 pub const NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO: _bindgen_ty_2 = 86; 142 pub const NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO: _bindgen_ty_2 = 87; 143 pub const NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL: _bindgen_ty_2 = 88; 144 pub const NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL: _bindgen_ty_2 = 89; 145 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT: _bindgen_ty_2 = 90; 146 pub const NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO: _bindgen_ty_2 = 91; 147 pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST: _bindgen_ty_2 = 92; 148 pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL: _bindgen_ty_2 = 93; 149 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE: _bindgen_ty_2 = 94; 150 pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR: _bindgen_ty_2 = 95; 151 pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR: _bindgen_ty_2 = 96; 152 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE: _bindgen_ty_2 = 97; 153 pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE: _bindgen_ty_2 = 98; 154 pub const NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT: _bindgen_ty_2 = 99; 155 pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS: _bindgen_ty_2 = 100; 156 pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL: _bindgen_ty_2 = 101; 157 pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL: _bindgen_ty_2 = 102; 158 pub const NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC: _bindgen_ty_2 = 103; 159 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2: _bindgen_ty_2 = 104; 160 pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT: _bindgen_ty_2 = 105; 161 pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY: _bindgen_ty_2 = 106; 162 pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS: _bindgen_ty_2 = 107; 163 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES: _bindgen_ty_2 = 108; 164 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES: _bindgen_ty_2 = 109; 165 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK: _bindgen_ty_2 = 110; 166 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX: _bindgen_ty_2 = 111; 167 pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND: _bindgen_ty_2 = 112; 168 pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE: _bindgen_ty_2 = 113; 169 pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND: _bindgen_ty_2 = 114; 170 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX: _bindgen_ty_2 = 115; 171 pub const NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES: _bindgen_ty_2 = 116; 172 pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT: _bindgen_ty_2 = 117; 173 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES: _bindgen_ty_2 = 118; 174 pub const NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS: _bindgen_ty_2 = 119; 175 pub const NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE: _bindgen_ty_2 = 120; 176 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK: _bindgen_ty_2 = 121; 177 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY: _bindgen_ty_2 = 122; 178 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK: _bindgen_ty_2 = 123; 179 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS: _bindgen_ty_2 = 124; 180 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS: _bindgen_ty_2 = 125; 181 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX: _bindgen_ty_2 = 126; 182 pub const NV_VGPU_MSG_FUNCTION_RESERVED_0: _bindgen_ty_2 = 127; 183 pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC: _bindgen_ty_2 = 128; 184 pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY: _bindgen_ty_2 = 129; 185 pub const NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS: _bindgen_ty_2 = 130; 186 pub const NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES: _bindgen_ty_2 = 131; 187 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT: _bindgen_ty_2 = 132; 188 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT: _bindgen_ty_2 = 133; 189 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS: _bindgen_ty_2 = 134; 190 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG: _bindgen_ty_2 = 135; 191 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE: _bindgen_ty_2 = 136; 192 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE: _bindgen_ty_2 = 137; 193 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG: _bindgen_ty_2 = 138; 194 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE: _bindgen_ty_2 = 139; 195 pub const NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM: _bindgen_ty_2 = 140; 196 pub const NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT: _bindgen_ty_2 = 141; 197 pub const NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2: _bindgen_ty_2 = 142; 198 pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES: _bindgen_ty_2 = 143; 199 pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO: _bindgen_ty_2 = 144; 200 pub const NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES: _bindgen_ty_2 = 145; 201 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX: _bindgen_ty_2 = 146; 202 pub const NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO: _bindgen_ty_2 = 147; 203 pub const NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO: _bindgen_ty_2 = 148; 204 pub const NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL: _bindgen_ty_2 = 149; 205 pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE: _bindgen_ty_2 = 150; 206 pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS: _bindgen_ty_2 = 151; 207 pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL: _bindgen_ty_2 = 152; 208 pub const NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM: _bindgen_ty_2 = 153; 209 pub const NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ: _bindgen_ty_2 = 154; 210 pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB: _bindgen_ty_2 = 155; 211 pub const NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO: _bindgen_ty_2 = 156; 212 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP: _bindgen_ty_2 = 157; 213 pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE: _bindgen_ty_2 = 158; 214 pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE: _bindgen_ty_2 = 159; 215 pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE: _bindgen_ty_2 = 160; 216 pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY: _bindgen_ty_2 = 161; 217 pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP: _bindgen_ty_2 = 162; 218 pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP: _bindgen_ty_2 = 163; 219 pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM: _bindgen_ty_2 = 164; 220 pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES: _bindgen_ty_2 = 165; 221 pub const NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION: _bindgen_ty_2 = 166; 222 pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL: _bindgen_ty_2 = 167; 223 pub const NV_VGPU_MSG_FUNCTION_DCE_RM_INIT: _bindgen_ty_2 = 168; 224 pub const NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER: _bindgen_ty_2 = 169; 225 pub const NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET: _bindgen_ty_2 = 170; 226 pub const NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND: _bindgen_ty_2 = 171; 227 pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2: _bindgen_ty_2 = 172; 228 pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM: _bindgen_ty_2 = 173; 229 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE: _bindgen_ty_2 = 174; 230 pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS: _bindgen_ty_2 = 175; 231 pub const NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE: _bindgen_ty_2 = 176; 232 pub const NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO: _bindgen_ty_2 = 177; 233 pub const NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS: _bindgen_ty_2 = 178; 234 pub const NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE: _bindgen_ty_2 = 179; 235 pub const NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS: _bindgen_ty_2 = 180; 236 pub const NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA: _bindgen_ty_2 = 181; 237 pub const NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA: _bindgen_ty_2 = 182; 238 pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED: _bindgen_ty_2 = 183; 239 pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE: _bindgen_ty_2 = 184; 240 pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE: _bindgen_ty_2 = 185; 241 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN: _bindgen_ty_2 = 186; 242 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX: _bindgen_ty_2 = 187; 243 pub const NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION: _bindgen_ty_2 = 244 188; 245 pub const NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK: 246 _bindgen_ty_2 = 189; 247 pub const NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER: _bindgen_ty_2 = 190; 248 pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS: _bindgen_ty_2 = 191; 249 pub const NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING: _bindgen_ty_2 = 192; 250 pub const NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING: _bindgen_ty_2 = 193; 251 pub const NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK: _bindgen_ty_2 = 194; 252 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS: _bindgen_ty_2 = 195; 253 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS: _bindgen_ty_2 = 196; 254 pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS: _bindgen_ty_2 = 197; 255 pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS: _bindgen_ty_2 = 198; 256 pub const NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER: _bindgen_ty_2 = 199; 257 pub const NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB: _bindgen_ty_2 = 200; 258 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS: _bindgen_ty_2 = 201; 259 pub const NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK: _bindgen_ty_2 = 202; 260 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG: _bindgen_ty_2 = 203; 261 pub const NV_VGPU_MSG_FUNCTION_RM_API_CONTROL: _bindgen_ty_2 = 204; 262 pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE: _bindgen_ty_2 = 205; 263 pub const NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA: _bindgen_ty_2 = 206; 264 pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA: _bindgen_ty_2 = 207; 265 pub const NV_VGPU_MSG_FUNCTION_RESERVED_208: _bindgen_ty_2 = 208; 266 pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2: _bindgen_ty_2 = 209; 267 pub const NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS: _bindgen_ty_2 = 210; 268 pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA: _bindgen_ty_2 = 211; 269 pub const NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO: _bindgen_ty_2 = 212; 270 pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE: _bindgen_ty_2 = 213; 271 pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR: _bindgen_ty_2 = 214; 272 pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS: _bindgen_ty_2 = 215; 273 pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS: _bindgen_ty_2 = 216; 274 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG: _bindgen_ty_2 = 217; 275 pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG: _bindgen_ty_2 = 218; 276 pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES: _bindgen_ty_2 = 219; 277 pub const NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES: _bindgen_ty_2 = 220; 278 pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF: _bindgen_ty_2 = 221; 279 pub const NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF: _bindgen_ty_2 = 222; 280 pub const NV_VGPU_MSG_FUNCTION_RESERVED: _bindgen_ty_2 = 223; 281 pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL: _bindgen_ty_2 = 224; 282 pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_GET_HS_CREDITS_MAPPING: _bindgen_ty_2 = 225; 283 pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_EXPORT: _bindgen_ty_2 = 226; 284 pub const NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS: _bindgen_ty_2 = 227; 285 pub type _bindgen_ty_2 = ffi::c_uint; 286 pub const NV_VGPU_MSG_EVENT_FIRST_EVENT: _bindgen_ty_3 = 4096; 287 pub const NV_VGPU_MSG_EVENT_GSP_INIT_DONE: _bindgen_ty_3 = 4097; 288 pub const NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: _bindgen_ty_3 = 4098; 289 pub const NV_VGPU_MSG_EVENT_POST_EVENT: _bindgen_ty_3 = 4099; 290 pub const NV_VGPU_MSG_EVENT_RC_TRIGGERED: _bindgen_ty_3 = 4100; 291 pub const NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED: _bindgen_ty_3 = 4101; 292 pub const NV_VGPU_MSG_EVENT_OS_ERROR_LOG: _bindgen_ty_3 = 4102; 293 pub const NV_VGPU_MSG_EVENT_RG_LINE_INTR: _bindgen_ty_3 = 4103; 294 pub const NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES: _bindgen_ty_3 = 4104; 295 pub const NV_VGPU_MSG_EVENT_SIM_READ: _bindgen_ty_3 = 4105; 296 pub const NV_VGPU_MSG_EVENT_SIM_WRITE: _bindgen_ty_3 = 4106; 297 pub const NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK: _bindgen_ty_3 = 4107; 298 pub const NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT: _bindgen_ty_3 = 4108; 299 pub const NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED: _bindgen_ty_3 = 4109; 300 pub const NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK: _bindgen_ty_3 = 4110; 301 pub const NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE: _bindgen_ty_3 = 4111; 302 pub const NV_VGPU_MSG_EVENT_VGPU_CONFIG: _bindgen_ty_3 = 4112; 303 pub const NV_VGPU_MSG_EVENT_DISPLAY_MODESET: _bindgen_ty_3 = 4113; 304 pub const NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE: _bindgen_ty_3 = 4114; 305 pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256: _bindgen_ty_3 = 4115; 306 pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512: _bindgen_ty_3 = 4116; 307 pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024: _bindgen_ty_3 = 4117; 308 pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048: _bindgen_ty_3 = 4118; 309 pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096: _bindgen_ty_3 = 4119; 310 pub const NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE: _bindgen_ty_3 = 4120; 311 pub const NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED: _bindgen_ty_3 = 4121; 312 pub const NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK: _bindgen_ty_3 = 4122; 313 pub const NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP: _bindgen_ty_3 = 4123; 314 pub const NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: _bindgen_ty_3 = 4124; 315 pub const NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE: _bindgen_ty_3 = 4125; 316 pub const NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE: _bindgen_ty_3 = 4126; 317 pub const NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY: _bindgen_ty_3 = 4127; 318 pub const NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD: _bindgen_ty_3 = 4128; 319 pub const NV_VGPU_MSG_EVENT_FECS_ERROR: _bindgen_ty_3 = 4129; 320 pub const NV_VGPU_MSG_EVENT_RECOVERY_ACTION: _bindgen_ty_3 = 4130; 321 pub const NV_VGPU_MSG_EVENT_NUM_EVENTS: _bindgen_ty_3 = 4131; 322 pub type _bindgen_ty_3 = ffi::c_uint; 323 #[repr(C)] 324 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 325 pub struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS { 326 pub totalVFs: u32_, 327 pub firstVfOffset: u32_, 328 pub vfFeatureMask: u32_, 329 pub __bindgen_padding_0: [u8; 4usize], 330 pub FirstVFBar0Address: u64_, 331 pub FirstVFBar1Address: u64_, 332 pub FirstVFBar2Address: u64_, 333 pub bar0Size: u64_, 334 pub bar1Size: u64_, 335 pub bar2Size: u64_, 336 pub b64bitBar0: u8_, 337 pub b64bitBar1: u8_, 338 pub b64bitBar2: u8_, 339 pub bSriovEnabled: u8_, 340 pub bSriovHeavyEnabled: u8_, 341 pub bEmulateVFBar0TlbInvalidationRegister: u8_, 342 pub bClientRmAllocatedCtxBuffer: u8_, 343 pub bNonPowerOf2ChannelCountSupported: u8_, 344 pub bVfResizableBAR1Supported: u8_, 345 pub __bindgen_padding_1: [u8; 7usize], 346 } 347 #[repr(C)] 348 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 349 pub struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS { 350 pub BoardID: u32_, 351 pub chipSKU: [ffi::c_char; 9usize], 352 pub chipSKUMod: [ffi::c_char; 5usize], 353 pub __bindgen_padding_0: [u8; 2usize], 354 pub skuConfigVersion: u32_, 355 pub project: [ffi::c_char; 5usize], 356 pub projectSKU: [ffi::c_char; 5usize], 357 pub CDP: [ffi::c_char; 6usize], 358 pub projectSKUMod: [ffi::c_char; 2usize], 359 pub __bindgen_padding_1: [u8; 2usize], 360 pub businessCycle: u32_, 361 } 362 pub type NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG = [u8_; 17usize]; 363 #[repr(C)] 364 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 365 pub struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO { 366 pub base: u64_, 367 pub limit: u64_, 368 pub reserved: u64_, 369 pub performance: u32_, 370 pub supportCompressed: u8_, 371 pub supportISO: u8_, 372 pub bProtected: u8_, 373 pub blackList: NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG, 374 } 375 #[repr(C)] 376 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 377 pub struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS { 378 pub numFBRegions: u32_, 379 pub __bindgen_padding_0: [u8; 4usize], 380 pub fbRegion: [NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO; 16usize], 381 } 382 #[repr(C)] 383 #[derive(Debug, Copy, Clone, MaybeZeroable)] 384 pub struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { 385 pub index: u32_, 386 pub flags: u32_, 387 pub length: u32_, 388 pub data: [u8_; 256usize], 389 } 390 impl Default for NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { 391 fn default() -> Self { 392 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 393 unsafe { 394 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 395 s.assume_init() 396 } 397 } 398 } 399 #[repr(C)] 400 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 401 pub struct DOD_METHOD_DATA { 402 pub status: u32_, 403 pub acpiIdListLen: u32_, 404 pub acpiIdList: [u32_; 16usize], 405 } 406 #[repr(C)] 407 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 408 pub struct JT_METHOD_DATA { 409 pub status: u32_, 410 pub jtCaps: u32_, 411 pub jtRevId: u16_, 412 pub bSBIOSCaps: u8_, 413 pub __bindgen_padding_0: u8, 414 } 415 #[repr(C)] 416 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 417 pub struct MUX_METHOD_DATA_ELEMENT { 418 pub acpiId: u32_, 419 pub mode: u32_, 420 pub status: u32_, 421 } 422 #[repr(C)] 423 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 424 pub struct MUX_METHOD_DATA { 425 pub tableLen: u32_, 426 pub acpiIdMuxModeTable: [MUX_METHOD_DATA_ELEMENT; 16usize], 427 pub acpiIdMuxPartTable: [MUX_METHOD_DATA_ELEMENT; 16usize], 428 pub acpiIdMuxStateTable: [MUX_METHOD_DATA_ELEMENT; 16usize], 429 } 430 #[repr(C)] 431 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 432 pub struct CAPS_METHOD_DATA { 433 pub status: u32_, 434 pub optimusCaps: u32_, 435 } 436 #[repr(C)] 437 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 438 pub struct ACPI_METHOD_DATA { 439 pub bValid: u8_, 440 pub __bindgen_padding_0: [u8; 3usize], 441 pub dodMethodData: DOD_METHOD_DATA, 442 pub jtMethodData: JT_METHOD_DATA, 443 pub muxMethodData: MUX_METHOD_DATA, 444 pub capsMethodData: CAPS_METHOD_DATA, 445 } 446 #[repr(C)] 447 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 448 pub struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS { 449 pub headIndex: u32_, 450 pub maxHResolution: u32_, 451 pub maxVResolution: u32_, 452 } 453 #[repr(C)] 454 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 455 pub struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS { 456 pub numHeads: u32_, 457 pub maxNumHeads: u32_, 458 } 459 #[repr(C)] 460 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 461 pub struct BUSINFO { 462 pub deviceID: u16_, 463 pub vendorID: u16_, 464 pub subdeviceID: u16_, 465 pub subvendorID: u16_, 466 pub revisionID: u8_, 467 pub __bindgen_padding_0: u8, 468 } 469 #[repr(C)] 470 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 471 pub struct GSP_VF_INFO { 472 pub totalVFs: u32_, 473 pub firstVFOffset: u32_, 474 pub FirstVFBar0Address: u64_, 475 pub FirstVFBar1Address: u64_, 476 pub FirstVFBar2Address: u64_, 477 pub b64bitBar0: u8_, 478 pub b64bitBar1: u8_, 479 pub b64bitBar2: u8_, 480 pub __bindgen_padding_0: [u8; 5usize], 481 } 482 #[repr(C)] 483 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 484 pub struct GSP_PCIE_CONFIG_REG { 485 pub linkCap: u32_, 486 } 487 #[repr(C)] 488 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 489 pub struct EcidManufacturingInfo { 490 pub ecidLow: u32_, 491 pub ecidHigh: u32_, 492 pub ecidExtended: u32_, 493 } 494 #[repr(C)] 495 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 496 pub struct FW_WPR_LAYOUT_OFFSET { 497 pub nonWprHeapOffset: u64_, 498 pub frtsOffset: u64_, 499 } 500 #[repr(C)] 501 #[derive(Debug, Copy, Clone, MaybeZeroable)] 502 pub struct GspStaticConfigInfo_t { 503 pub grCapsBits: [u8_; 23usize], 504 pub __bindgen_padding_0: u8, 505 pub gidInfo: NV2080_CTRL_GPU_GET_GID_INFO_PARAMS, 506 pub SKUInfo: NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS, 507 pub __bindgen_padding_1: [u8; 4usize], 508 pub fbRegionInfoParams: NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS, 509 pub sriovCaps: NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS, 510 pub sriovMaxGfid: u32_, 511 pub engineCaps: [u32_; 3usize], 512 pub poisonFuseEnabled: u8_, 513 pub __bindgen_padding_2: [u8; 7usize], 514 pub fb_length: u64_, 515 pub fbio_mask: u64_, 516 pub fb_bus_width: u32_, 517 pub fb_ram_type: u32_, 518 pub fbp_mask: u64_, 519 pub l2_cache_size: u32_, 520 pub gpuNameString: [u8_; 64usize], 521 pub gpuShortNameString: [u8_; 64usize], 522 pub gpuNameString_Unicode: [u16_; 64usize], 523 pub bGpuInternalSku: u8_, 524 pub bIsQuadroGeneric: u8_, 525 pub bIsQuadroAd: u8_, 526 pub bIsNvidiaNvs: u8_, 527 pub bIsVgx: u8_, 528 pub bGeforceSmb: u8_, 529 pub bIsTitan: u8_, 530 pub bIsTesla: u8_, 531 pub bIsMobile: u8_, 532 pub bIsGc6Rtd3Allowed: u8_, 533 pub bIsGc8Rtd3Allowed: u8_, 534 pub bIsGcOffRtd3Allowed: u8_, 535 pub bIsGcoffLegacyAllowed: u8_, 536 pub bIsMigSupported: u8_, 537 pub RTD3GC6TotalBoardPower: u16_, 538 pub RTD3GC6PerstDelay: u16_, 539 pub __bindgen_padding_3: [u8; 2usize], 540 pub bar1PdeBase: u64_, 541 pub bar2PdeBase: u64_, 542 pub bVbiosValid: u8_, 543 pub __bindgen_padding_4: [u8; 3usize], 544 pub vbiosSubVendor: u32_, 545 pub vbiosSubDevice: u32_, 546 pub bPageRetirementSupported: u8_, 547 pub bSplitVasBetweenServerClientRm: u8_, 548 pub bClRootportNeedsNosnoopWAR: u8_, 549 pub __bindgen_padding_5: u8, 550 pub displaylessMaxHeads: VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS, 551 pub displaylessMaxResolution: VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS, 552 pub __bindgen_padding_6: [u8; 4usize], 553 pub displaylessMaxPixels: u64_, 554 pub hInternalClient: u32_, 555 pub hInternalDevice: u32_, 556 pub hInternalSubdevice: u32_, 557 pub bSelfHostedMode: u8_, 558 pub bAtsSupported: u8_, 559 pub bIsGpuUefi: u8_, 560 pub bIsEfiInit: u8_, 561 pub ecidInfo: [EcidManufacturingInfo; 2usize], 562 pub fwWprLayoutOffset: FW_WPR_LAYOUT_OFFSET, 563 } 564 impl Default for GspStaticConfigInfo_t { 565 fn default() -> Self { 566 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 567 unsafe { 568 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 569 s.assume_init() 570 } 571 } 572 } 573 #[repr(C)] 574 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 575 pub struct GspSystemInfo { 576 pub gpuPhysAddr: u64_, 577 pub gpuPhysFbAddr: u64_, 578 pub gpuPhysInstAddr: u64_, 579 pub gpuPhysIoAddr: u64_, 580 pub nvDomainBusDeviceFunc: u64_, 581 pub simAccessBufPhysAddr: u64_, 582 pub notifyOpSharedSurfacePhysAddr: u64_, 583 pub pcieAtomicsOpMask: u64_, 584 pub consoleMemSize: u64_, 585 pub maxUserVa: u64_, 586 pub pciConfigMirrorBase: u32_, 587 pub pciConfigMirrorSize: u32_, 588 pub PCIDeviceID: u32_, 589 pub PCISubDeviceID: u32_, 590 pub PCIRevisionID: u32_, 591 pub pcieAtomicsCplDeviceCapMask: u32_, 592 pub oorArch: u8_, 593 pub __bindgen_padding_0: [u8; 7usize], 594 pub clPdbProperties: u64_, 595 pub Chipset: u32_, 596 pub bGpuBehindBridge: u8_, 597 pub bFlrSupported: u8_, 598 pub b64bBar0Supported: u8_, 599 pub bMnocAvailable: u8_, 600 pub chipsetL1ssEnable: u32_, 601 pub bUpstreamL0sUnsupported: u8_, 602 pub bUpstreamL1Unsupported: u8_, 603 pub bUpstreamL1PorSupported: u8_, 604 pub bUpstreamL1PorMobileOnly: u8_, 605 pub bSystemHasMux: u8_, 606 pub upstreamAddressValid: u8_, 607 pub FHBBusInfo: BUSINFO, 608 pub chipsetIDInfo: BUSINFO, 609 pub __bindgen_padding_1: [u8; 2usize], 610 pub acpiMethodData: ACPI_METHOD_DATA, 611 pub hypervisorType: u32_, 612 pub bIsPassthru: u8_, 613 pub __bindgen_padding_2: [u8; 7usize], 614 pub sysTimerOffsetNs: u64_, 615 pub gspVFInfo: GSP_VF_INFO, 616 pub bIsPrimary: u8_, 617 pub isGridBuild: u8_, 618 pub __bindgen_padding_3: [u8; 2usize], 619 pub pcieConfigReg: GSP_PCIE_CONFIG_REG, 620 pub gridBuildCsp: u32_, 621 pub bPreserveVideoMemoryAllocations: u8_, 622 pub bTdrEventSupported: u8_, 623 pub bFeatureStretchVblankCapable: u8_, 624 pub bEnableDynamicGranularityPageArrays: u8_, 625 pub bClockBoostSupported: u8_, 626 pub bRouteDispIntrsToCPU: u8_, 627 pub __bindgen_padding_4: [u8; 6usize], 628 pub hostPageSize: u64_, 629 } 630 #[repr(C)] 631 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 632 pub struct MESSAGE_QUEUE_INIT_ARGUMENTS { 633 pub sharedMemPhysAddr: u64_, 634 pub pageTableEntryCount: u32_, 635 pub __bindgen_padding_0: [u8; 4usize], 636 pub cmdQueueOffset: u64_, 637 pub statQueueOffset: u64_, 638 } 639 #[repr(C)] 640 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 641 pub struct GSP_SR_INIT_ARGUMENTS { 642 pub oldLevel: u32_, 643 pub flags: u32_, 644 pub bInPMTransition: u8_, 645 pub __bindgen_padding_0: [u8; 3usize], 646 } 647 #[repr(C)] 648 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 649 pub struct GSP_ARGUMENTS_CACHED { 650 pub messageQueueInitArguments: MESSAGE_QUEUE_INIT_ARGUMENTS, 651 pub srInitArguments: GSP_SR_INIT_ARGUMENTS, 652 pub gpuInstance: u32_, 653 pub bDmemStack: u8_, 654 pub __bindgen_padding_0: [u8; 7usize], 655 pub profilerArgs: GSP_ARGUMENTS_CACHED__bindgen_ty_1, 656 } 657 #[repr(C)] 658 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 659 pub struct GSP_ARGUMENTS_CACHED__bindgen_ty_1 { 660 pub pa: u64_, 661 pub size: u64_, 662 } 663 #[repr(C)] 664 #[derive(Copy, Clone, MaybeZeroable)] 665 pub union rpc_message_rpc_union_field_v03_00 { 666 pub spare: u32_, 667 pub cpuRmGfid: u32_, 668 } 669 impl Default for rpc_message_rpc_union_field_v03_00 { 670 fn default() -> Self { 671 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 672 unsafe { 673 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 674 s.assume_init() 675 } 676 } 677 } 678 pub type rpc_message_rpc_union_field_v = rpc_message_rpc_union_field_v03_00; 679 #[repr(C)] 680 #[derive(MaybeZeroable)] 681 pub struct rpc_message_header_v03_00 { 682 pub header_version: u32_, 683 pub signature: u32_, 684 pub length: u32_, 685 pub function: u32_, 686 pub rpc_result: u32_, 687 pub rpc_result_private: u32_, 688 pub sequence: u32_, 689 pub u: rpc_message_rpc_union_field_v, 690 pub rpc_message_data: __IncompleteArrayField<u8_>, 691 } 692 impl Default for rpc_message_header_v03_00 { 693 fn default() -> Self { 694 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 695 unsafe { 696 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 697 s.assume_init() 698 } 699 } 700 } 701 pub type rpc_message_header_v = rpc_message_header_v03_00; 702 #[repr(C)] 703 #[derive(Copy, Clone, MaybeZeroable)] 704 pub struct GspFwWprMeta { 705 pub magic: u64_, 706 pub revision: u64_, 707 pub sysmemAddrOfRadix3Elf: u64_, 708 pub sizeOfRadix3Elf: u64_, 709 pub sysmemAddrOfBootloader: u64_, 710 pub sizeOfBootloader: u64_, 711 pub bootloaderCodeOffset: u64_, 712 pub bootloaderDataOffset: u64_, 713 pub bootloaderManifestOffset: u64_, 714 pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_1, 715 pub gspFwRsvdStart: u64_, 716 pub nonWprHeapOffset: u64_, 717 pub nonWprHeapSize: u64_, 718 pub gspFwWprStart: u64_, 719 pub gspFwHeapOffset: u64_, 720 pub gspFwHeapSize: u64_, 721 pub gspFwOffset: u64_, 722 pub bootBinOffset: u64_, 723 pub frtsOffset: u64_, 724 pub frtsSize: u64_, 725 pub gspFwWprEnd: u64_, 726 pub fbSize: u64_, 727 pub vgaWorkspaceOffset: u64_, 728 pub vgaWorkspaceSize: u64_, 729 pub bootCount: u64_, 730 pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_2, 731 pub gspFwHeapVfPartitionCount: u8_, 732 pub flags: u8_, 733 pub padding: [u8_; 2usize], 734 pub pmuReservedSize: u32_, 735 pub verified: u64_, 736 } 737 #[repr(C)] 738 #[derive(Copy, Clone, MaybeZeroable)] 739 pub union GspFwWprMeta__bindgen_ty_1 { 740 pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_1__bindgen_ty_1, 741 pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_1__bindgen_ty_2, 742 } 743 #[repr(C)] 744 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 745 pub struct GspFwWprMeta__bindgen_ty_1__bindgen_ty_1 { 746 pub sysmemAddrOfSignature: u64_, 747 pub sizeOfSignature: u64_, 748 } 749 #[repr(C)] 750 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 751 pub struct GspFwWprMeta__bindgen_ty_1__bindgen_ty_2 { 752 pub gspFwHeapFreeListWprOffset: u32_, 753 pub unused0: u32_, 754 pub unused1: u64_, 755 } 756 impl Default for GspFwWprMeta__bindgen_ty_1 { 757 fn default() -> Self { 758 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 759 unsafe { 760 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 761 s.assume_init() 762 } 763 } 764 } 765 #[repr(C)] 766 #[derive(Copy, Clone, MaybeZeroable)] 767 pub union GspFwWprMeta__bindgen_ty_2 { 768 pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_2__bindgen_ty_1, 769 pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_2__bindgen_ty_2, 770 } 771 #[repr(C)] 772 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 773 pub struct GspFwWprMeta__bindgen_ty_2__bindgen_ty_1 { 774 pub partitionRpcAddr: u64_, 775 pub partitionRpcRequestOffset: u16_, 776 pub partitionRpcReplyOffset: u16_, 777 pub elfCodeOffset: u32_, 778 pub elfDataOffset: u32_, 779 pub elfCodeSize: u32_, 780 pub elfDataSize: u32_, 781 pub lsUcodeVersion: u32_, 782 } 783 #[repr(C)] 784 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 785 pub struct GspFwWprMeta__bindgen_ty_2__bindgen_ty_2 { 786 pub partitionRpcPadding: [u32_; 4usize], 787 pub sysmemAddrOfCrashReportQueue: u64_, 788 pub sizeOfCrashReportQueue: u32_, 789 pub lsUcodeVersionPadding: [u32_; 1usize], 790 } 791 impl Default for GspFwWprMeta__bindgen_ty_2 { 792 fn default() -> Self { 793 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 794 unsafe { 795 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 796 s.assume_init() 797 } 798 } 799 } 800 impl Default for GspFwWprMeta { 801 fn default() -> Self { 802 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 803 unsafe { 804 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 805 s.assume_init() 806 } 807 } 808 } 809 pub type LibosAddress = u64_; 810 pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_NONE: LibosMemoryRegionKind = 0; 811 pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_CONTIGUOUS: LibosMemoryRegionKind = 1; 812 pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_RADIX3: LibosMemoryRegionKind = 2; 813 pub type LibosMemoryRegionKind = ffi::c_uint; 814 pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_NONE: LibosMemoryRegionLoc = 0; 815 pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_SYSMEM: LibosMemoryRegionLoc = 1; 816 pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_FB: LibosMemoryRegionLoc = 2; 817 pub type LibosMemoryRegionLoc = ffi::c_uint; 818 #[repr(C)] 819 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 820 pub struct LibosMemoryRegionInitArgument { 821 pub id8: LibosAddress, 822 pub pa: LibosAddress, 823 pub size: LibosAddress, 824 pub kind: u8_, 825 pub loc: u8_, 826 pub __bindgen_padding_0: [u8; 6usize], 827 } 828 #[repr(C)] 829 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 830 pub struct PACKED_REGISTRY_ENTRY { 831 pub nameOffset: u32_, 832 pub type_: u8_, 833 pub __bindgen_padding_0: [u8; 3usize], 834 pub data: u32_, 835 pub length: u32_, 836 } 837 #[repr(C)] 838 #[derive(Debug, Default, MaybeZeroable)] 839 pub struct PACKED_REGISTRY_TABLE { 840 pub size: u32_, 841 pub numEntries: u32_, 842 pub entries: __IncompleteArrayField<PACKED_REGISTRY_ENTRY>, 843 } 844 #[repr(C)] 845 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 846 pub struct msgqTxHeader { 847 pub version: u32_, 848 pub size: u32_, 849 pub msgSize: u32_, 850 pub msgCount: u32_, 851 pub writePtr: u32_, 852 pub flags: u32_, 853 pub rxHdrOff: u32_, 854 pub entryOff: u32_, 855 } 856 #[repr(C)] 857 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 858 pub struct msgqRxHeader { 859 pub readPtr: u32_, 860 } 861 #[repr(C)] 862 #[repr(align(8))] 863 #[derive(MaybeZeroable)] 864 pub struct GSP_MSG_QUEUE_ELEMENT { 865 pub authTagBuffer: [u8_; 16usize], 866 pub aadBuffer: [u8_; 16usize], 867 pub checkSum: u32_, 868 pub seqNum: u32_, 869 pub elemCount: u32_, 870 pub __bindgen_padding_0: [u8; 4usize], 871 pub rpc: rpc_message_header_v, 872 } 873 impl Default for GSP_MSG_QUEUE_ELEMENT { 874 fn default() -> Self { 875 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 876 unsafe { 877 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 878 s.assume_init() 879 } 880 } 881 } 882 #[repr(C)] 883 #[derive(Debug, Default, MaybeZeroable)] 884 pub struct rpc_run_cpu_sequencer_v17_00 { 885 pub bufferSizeDWord: u32_, 886 pub cmdIndex: u32_, 887 pub regSaveArea: [u32_; 8usize], 888 pub commandBuffer: __IncompleteArrayField<u32_>, 889 } 890 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_REG_WRITE: GSP_SEQ_BUF_OPCODE = 0; 891 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_REG_MODIFY: GSP_SEQ_BUF_OPCODE = 1; 892 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_REG_POLL: GSP_SEQ_BUF_OPCODE = 2; 893 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_DELAY_US: GSP_SEQ_BUF_OPCODE = 3; 894 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_REG_STORE: GSP_SEQ_BUF_OPCODE = 4; 895 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_RESET: GSP_SEQ_BUF_OPCODE = 5; 896 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_START: GSP_SEQ_BUF_OPCODE = 6; 897 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT: GSP_SEQ_BUF_OPCODE = 7; 898 pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_RESUME: GSP_SEQ_BUF_OPCODE = 8; 899 pub type GSP_SEQ_BUF_OPCODE = ffi::c_uint; 900 #[repr(C)] 901 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 902 pub struct GSP_SEQ_BUF_PAYLOAD_REG_WRITE { 903 pub addr: u32_, 904 pub val: u32_, 905 } 906 #[repr(C)] 907 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 908 pub struct GSP_SEQ_BUF_PAYLOAD_REG_MODIFY { 909 pub addr: u32_, 910 pub mask: u32_, 911 pub val: u32_, 912 } 913 #[repr(C)] 914 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 915 pub struct GSP_SEQ_BUF_PAYLOAD_REG_POLL { 916 pub addr: u32_, 917 pub mask: u32_, 918 pub val: u32_, 919 pub timeout: u32_, 920 pub error: u32_, 921 } 922 #[repr(C)] 923 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 924 pub struct GSP_SEQ_BUF_PAYLOAD_DELAY_US { 925 pub val: u32_, 926 } 927 #[repr(C)] 928 #[derive(Debug, Default, Copy, Clone, MaybeZeroable)] 929 pub struct GSP_SEQ_BUF_PAYLOAD_REG_STORE { 930 pub addr: u32_, 931 pub index: u32_, 932 } 933 #[repr(C)] 934 #[derive(Copy, Clone, MaybeZeroable)] 935 pub struct GSP_SEQUENCER_BUFFER_CMD { 936 pub opCode: GSP_SEQ_BUF_OPCODE, 937 pub payload: GSP_SEQUENCER_BUFFER_CMD__bindgen_ty_1, 938 } 939 #[repr(C)] 940 #[derive(Copy, Clone, MaybeZeroable)] 941 pub union GSP_SEQUENCER_BUFFER_CMD__bindgen_ty_1 { 942 pub regWrite: GSP_SEQ_BUF_PAYLOAD_REG_WRITE, 943 pub regModify: GSP_SEQ_BUF_PAYLOAD_REG_MODIFY, 944 pub regPoll: GSP_SEQ_BUF_PAYLOAD_REG_POLL, 945 pub delayUs: GSP_SEQ_BUF_PAYLOAD_DELAY_US, 946 pub regStore: GSP_SEQ_BUF_PAYLOAD_REG_STORE, 947 } 948 impl Default for GSP_SEQUENCER_BUFFER_CMD__bindgen_ty_1 { 949 fn default() -> Self { 950 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 951 unsafe { 952 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 953 s.assume_init() 954 } 955 } 956 } 957 impl Default for GSP_SEQUENCER_BUFFER_CMD { 958 fn default() -> Self { 959 let mut s = ::core::mem::MaybeUninit::<Self>::uninit(); 960 unsafe { 961 ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); 962 s.assume_init() 963 } 964 } 965 } 966