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Searched refs:NUM_LINK_LEVELS (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu9_driver_if.h44 #define NUM_LINK_LEVELS 2 macro
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
237 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
238 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
239 …uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
H A Dsmu11_driver_if.h48 #define NUM_LINK_LEVELS 2 macro
63 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
453 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
454 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
455 uint16_t LclkFreq[NUM_LINK_LEVELS];
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h46 #define NUM_LINK_LEVELS 2 macro
59 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
341 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
342 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
343 uint16_t LclkFreq[NUM_LINK_LEVELS];
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h47 #define NUM_LINK_LEVELS 2 macro
66 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
756 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
757 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
758 uint16_t LclkFreq[NUM_LINK_LEVELS];
1116 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
1117 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1118 uint16_t LclkFreq[NUM_LINK_LEVELS];
H A Dsmu11_driver_if_navi10.h47 #define NUM_LINK_LEVELS 2 macro
62 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
626 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
627 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
628 uint16_t LclkFreq[NUM_LINK_LEVELS];
H A Dsmu13_driver_if_v13_0_0.h43 #define NUM_LINK_LEVELS 3 macro
1136 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
1137 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1138 uint16_t LclkFreq[NUM_LINK_LEVELS];
H A Dsmu13_driver_if_v13_0_7.h44 #define NUM_LINK_LEVELS 3 macro
1138 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
1139 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1140 uint16_t LclkFreq[NUM_LINK_LEVELS];
H A Dsmu14_driver_if_v14_0.h41 #define NUM_LINK_LEVELS 3 macro
1231 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:…
1232 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1233 uint16_t LclkFreq[NUM_LINK_LEVELS];
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_hwmgr.c876 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_override_pcie_parameters()
900 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_override_pcie_parameters()
2710 if (soft_min_level >= NUM_LINK_LEVELS || in vega20_force_clock_level()
2711 soft_max_level >= NUM_LINK_LEVELS) in vega20_force_clock_level()
3493 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_emit_clock_levels()
H A Dvega10_hwmgr.c1271 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_setup_default_pcie_table()
1293 pcie_table->count = NUM_LINK_LEVELS; in vega10_setup_default_pcie_table()
1547 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_override_pcie_parameters()
1556 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_override_pcie_parameters()
1587 while (i < NUM_LINK_LEVELS) { in vega10_populate_smc_link_levels()
4762 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_emit_clock_levels()
H A Dvega12_hwmgr.c530 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega12_override_pcie_parameters()
554 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega12_override_pcie_parameters()