Searched refs:NUM_CHANNELS (Results 1 – 10 of 10) sorted by relevance
92 #define NUM_CHANNELS 4 macro93 #define BYTES_PER_FRAME (NUM_CHANNELS * BYTES_PER_SAMPLE)
236 (f * NUM_CHANNELS); in tascam_capture_work_handler() 239 for (c = 0; c < NUM_CHANNELS; c++) { in tascam_capture_work_handler()
46 .channels_min = NUM_CHANNELS,47 .channels_max = NUM_CHANNELS,
44 #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) macro182 } chan[NUM_CHANNELS];
46 #define NUM_CHANNELS 2 /* Max channels */ macro161 u64 dimm_s_size[NUM_CHANNELS];162 u64 dimm_l_size[NUM_CHANNELS];163 int dimm_l_map[NUM_CHANNELS];1103 for (i = 0; i < NUM_CHANNELS; i++) { in igen6_get_dimm_config()1170 for (i = 0; i < NUM_CHANNELS; i++) { in igen6_reg_dump()1309 layers[0].size = NUM_CHANNELS; in igen6_register_mci()
288 #define NUM_CHANNELS 6 /* Max channels per MC */ macro391 struct pci_dev *pci_tad[NUM_CHANNELS];396 struct sbridge_channel channel[NUM_CHANNELS];1593 : NUM_CHANNELS; in __populate_dimms()1869 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout()1889 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout()2380 if (channel >= NUM_CHANNELS) { in get_memory_error_data_from_mce()3202 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); in sbridge_mce_output_error()3358 KNL_MAX_CHANNELS : NUM_CHANNELS; in sbridge_register_mci()
54 #define NUM_CHANNELS 2 macro85 static struct uart_ip22zilog_port ip22zilog_port_table[NUM_CHANNELS];1022 .nr = NUM_CHANNELS,1099 for (i = 0; i < NUM_CHANNELS; i++) in ip22zilog_probe()1110 for (i = 0; i < NUM_CHANNELS; i++) { in ip22zilog_remove()
29 #define NUM_CHANNELS 8 macro
52 #define NUM_CHANNELS ARRAY_SIZE(channel_freq) macro315 i < NUM_CHANNELS && chs < IW_MAX_FREQUENCIES; i++) in gelic_wl_get_range()
109 #define NUM_CHANNELS GENMASK(14, 12) macro