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Searched refs:MTL_GSC_HECI2_BASE (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_proxy.c284 intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE), in intel_gsc_proxy_request_handler()
320 intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE), in i915_gsc_proxy_component_bind()
346 intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE), in i915_gsc_proxy_component_unbind()
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gsc_regs.h19 #define MTL_GSC_HECI2_BASE 0x00117000 macro
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_reset.c740 HECI_H_GS1(MTL_GSC_HECI2_BASE), in wa_14015076503_start()
745 HECI_H_CSR(MTL_GSC_HECI2_BASE), in wa_14015076503_start()
760 HECI_H_GS1(MTL_GSC_HECI2_BASE), in wa_14015076503_end()
/linux/drivers/gpu/drm/xe/
H A Dxe_gsc_proxy.c93 xe_mmio_rmw32(&gt->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set); in __gsc_proxy_irq_rmw()
/linux/drivers/gpu/drm/i915/
H A Di915_reg.h279 #define MTL_GSC_HECI2_BASE 0x00117000 macro