1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_H 7 #define __MT7996_H 8 9 #include <linux/interrupt.h> 10 #include <linux/ktime.h> 11 #include "../mt76_connac.h" 12 #include "regs.h" 13 14 #define MT7996_MAX_RADIOS 3 15 #define MT7996_MAX_INTERFACES 19 /* per-band */ 16 #define MT7996_MAX_WMM_SETS 4 17 #define MT7996_WTBL_BMC_SIZE (is_mt7996(&dev->mt76) ? 64 : 32) 18 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1) 19 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ 20 mt7996_max_interface_num(dev)) 21 22 #define MT7996_WATCHDOG_TIME (HZ / 10) 23 #define MT7996_RESET_TIMEOUT (30 * HZ) 24 25 #define MT7996_TX_RING_SIZE 2048 26 #define MT7996_TX_MCU_RING_SIZE 256 27 #define MT7996_TX_FWDL_RING_SIZE 128 28 29 #define MT7996_RX_RING_SIZE 1536 30 #define MT7996_RX_MCU_RING_SIZE 512 31 #define MT7996_RX_MCU_RING_SIZE_WA 1024 32 #define MT7996_NPU_TX_RING_SIZE 1024 33 #define MT7996_NPU_RX_RING_SIZE 1024 34 #define MT7996_NPU_TXD_SIZE 3 35 36 /* scatter-gather of mcu event is not supported in connac3 */ 37 #define MT7996_RX_MCU_BUF_SIZE (2048 + \ 38 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 39 40 #define MT7996_DEVICE_ID 0x7990 41 #define MT7996_DEVICE_ID_2 0x7991 42 #define MT7992_DEVICE_ID 0x7992 43 #define MT7992_DEVICE_ID_2 0x799a 44 #define MT7990_DEVICE_ID 0x7993 45 #define MT7990_DEVICE_ID_2 0x799b 46 47 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" 48 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" 49 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin" 50 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" 51 52 #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin" 53 #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin" 54 #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP 55 #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin" 56 57 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin" 58 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin" 59 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin" 60 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin" 61 62 #define MT7992_FIRMWARE_WA_23 "mediatek/mt7996/mt7992_wa_23.bin" 63 #define MT7992_FIRMWARE_WM_23 "mediatek/mt7996/mt7992_wm_23.bin" 64 #define MT7992_FIRMWARE_DSP_23 "mediatek/mt7996/mt7992_dsp_23.bin" 65 #define MT7992_ROM_PATCH_23 "mediatek/mt7996/mt7992_rom_patch_23.bin" 66 67 #define MT7992_FIRMWARE_WA_24 "mediatek/mt7996/mt7992_wa_24.bin" 68 #define MT7992_FIRMWARE_WM_24 "mediatek/mt7996/mt7992_wm_24.bin" 69 #define MT7992_FIRMWARE_DSP_24 "mediatek/mt7996/mt7992_dsp_24.bin" 70 #define MT7992_ROM_PATCH_24 "mediatek/mt7996/mt7992_rom_patch_24.bin" 71 72 #define MT7990_FIRMWARE_WA "" 73 #define MT7990_FIRMWARE_WM "mediatek/mt7996/mt7990_wm.bin" 74 #define MT7990_FIRMWARE_DSP "" 75 #define MT7990_ROM_PATCH "mediatek/mt7996/mt7990_rom_patch.bin" 76 77 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" 78 #define MT7996_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7996_eeprom_2i5i6i.bin" 79 #define MT7996_EEPROM_DEFAULT_233 "mediatek/mt7996/mt7996_eeprom_233.bin" 80 #define MT7996_EEPROM_DEFAULT_233_INT "mediatek/mt7996/mt7996_eeprom_233_2i5i6i.bin" 81 82 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin" 83 #define MT7992_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7992_eeprom_2i5i.bin" 84 #define MT7992_EEPROM_DEFAULT_MIX "mediatek/mt7996/mt7992_eeprom_2i5e.bin" 85 #define MT7992_EEPROM_DEFAULT_23 "mediatek/mt7996/mt7992_eeprom_23.bin" 86 #define MT7992_EEPROM_DEFAULT_23_INT "mediatek/mt7996/mt7992_eeprom_23_2i5i.bin" 87 #define MT7992_EEPROM_DEFAULT_24 "mediatek/mt7996/mt7992_eeprom_24_2i5i.bin" 88 89 #define MT7990_EEPROM_DEFAULT "mediatek/mt7996/mt7990_eeprom.bin" 90 #define MT7990_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7990_eeprom_2i5i.bin" 91 92 #define MT7996_EEPROM_SIZE 7680 93 #define MT7996_EEPROM_BLOCK_SIZE 16 94 #define MT7996_EXT_EEPROM_BLOCK_SIZE 1024 95 #define MT7996_TOKEN_SIZE 16384 96 #define MT7996_HW_TOKEN_SIZE 8192 97 98 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 99 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 100 #define MT7996_IBF_MAX_NC 2 101 #define MT7996_IBF_TIMEOUT 0x18 102 #define MT7996_IBF_TIMEOUT_LEGACY 0x48 103 104 #define MT7992_CFEND_RATE_DEFAULT 0x4b /* OFDM 6M */ 105 #define MT7992_IBF_TIMEOUT 0xff 106 107 #define MT7996_SKU_RATE_NUM 417 108 #define MT7996_SKU_PATH_NUM 494 109 110 #define MT7996_MAX_TWT_AGRT 16 111 #define MT7996_MAX_STA_TWT_AGRT 8 112 #define MT7996_MIN_TWT_DUR 64 113 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) 114 115 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */ 116 #define MT7996_BASIC_RATES_TBL 31 117 #define MT7996_BEACON_RATES_TBL 25 118 119 #define MT7996_THERMAL_THROTTLE_MAX 100 120 #define MT7996_CDEV_THROTTLE_MAX 99 121 #define MT7996_CRIT_TEMP_IDX 0 122 #define MT7996_MAX_TEMP_IDX 1 123 #define MT7996_CRIT_TEMP 110 124 #define MT7996_MAX_TEMP 120 125 126 #define MT7996_MAX_HIF_RXD_IN_PG 5 127 #define MT7996_RRO_MSDU_PG_HASH_SIZE 127 128 #define MT7996_RRO_MAX_SESSION 1024 129 #define MT7996_RRO_WINDOW_MAX_LEN 1024 130 #define MT7996_RRO_ADDR_ELEM_LEN 128 131 #define MT7996_RRO_BA_BITMAP_LEN 2 132 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \ 133 MT7996_RRO_BA_BITMAP_LEN) 134 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \ 135 MT7996_RRO_ADDR_ELEM_LEN) 136 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \ 137 MT7996_RRO_BA_BITMAP_SESSION_SIZE) 138 139 #define MT7996_RX_BUF_SIZE (1800 + \ 140 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 141 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \ 142 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 143 144 /* RRO 3.1 */ 145 #define MT7996_RRO_MSDU_PG_CR_CNT 8 146 #define MT7996_RRO_MSDU_PG_SIZE_PER_CR 0x10000 147 148 struct mt7996_vif; 149 struct mt7996_sta; 150 struct mt7996_dfs_pulse; 151 struct mt7996_dfs_pattern; 152 153 enum mt7996_ram_type { 154 MT7996_RAM_TYPE_WM, 155 MT7996_RAM_TYPE_WA, 156 MT7996_RAM_TYPE_DSP, 157 }; 158 159 enum mt7996_var_type { 160 MT7996_VAR_TYPE_444, 161 MT7996_VAR_TYPE_233, 162 }; 163 164 enum mt7992_var_type { 165 MT7992_VAR_TYPE_44, 166 MT7992_VAR_TYPE_23, 167 MT7992_VAR_TYPE_24, 168 }; 169 170 enum mt7990_var_type { 171 MT7990_VAR_TYPE_23, 172 }; 173 174 enum mt7996_fem_type { 175 MT7996_FEM_EXT, 176 MT7996_FEM_INT, 177 MT7996_FEM_MIX, 178 }; 179 180 enum mt7996_eeprom_mode { 181 EEPROM_MODE_DEFAULT_BIN, 182 EEPROM_MODE_EFUSE, 183 EEPROM_MODE_FLASH, 184 EEPROM_MODE_EXT, 185 }; 186 187 #define MT7996_EFUSE_BASE_OFFS_ADIE0 0x400 188 #define MT7996_EFUSE_BASE_OFFS_ADIE1 0x1e00 189 #define MT7996_EFUSE_BASE_OFFS_ADIE2 0x1200 190 #define MT7992_EFUSE_BASE_OFFS_ADIE1 0x1200 191 192 enum mt7996_txq_id { 193 MT7996_TXQ_FWDL = 16, 194 MT7996_TXQ_MCU_WM, 195 MT7996_TXQ_BAND0, 196 MT7996_TXQ_BAND1, 197 MT7996_TXQ_MCU_WA, 198 MT7996_TXQ_BAND2, 199 }; 200 201 enum mt7996_rxq_id { 202 MT7996_RXQ_MCU_WM = 0, 203 MT7996_RXQ_MCU_WA, 204 MT7996_RXQ_MCU_WA_MAIN = 2, 205 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */ 206 MT7996_RXQ_MCU_WA_TRI = 3, 207 MT7996_RXQ_BAND0 = 4, 208 MT7996_RXQ_BAND1 = 5, /* for mt7992 */ 209 MT7996_RXQ_BAND2 = 5, 210 MT7996_RXQ_RRO_BAND0 = 8, 211 MT7996_RXQ_RRO_BAND1 = 9, 212 MT7996_RXQ_RRO_BAND2 = 6, 213 MT7996_RXQ_MSDU_PG_BAND0 = 10, 214 MT7996_RXQ_MSDU_PG_BAND1 = 11, 215 MT7996_RXQ_MSDU_PG_BAND2 = 12, 216 MT7996_RXQ_TXFREE0 = 9, 217 MT7996_RXQ_TXFREE1 = 9, 218 MT7996_RXQ_TXFREE2 = 7, 219 MT7996_RXQ_RRO_IND = 0, 220 MT7996_RXQ_RRO_RXDMAD_C = 0, 221 MT7990_RXQ_TXFREE0 = 6, 222 MT7990_RXQ_TXFREE1 = 7, 223 }; 224 225 struct mt7996_twt_flow { 226 struct list_head list; 227 u64 start_tsf; 228 u64 tsf; 229 u32 duration; 230 u16 wcid; 231 __le16 mantissa; 232 u8 exp; 233 u8 table_id; 234 u8 id; 235 u8 protection:1; 236 u8 flowtype:1; 237 u8 trigger:1; 238 u8 sched:1; 239 }; 240 241 DECLARE_EWMA(avg_signal, 10, 8) 242 243 struct mt7996_sta_link { 244 struct mt76_wcid wcid; /* must be first */ 245 246 struct mt7996_sta *sta; 247 248 struct list_head rc_list; 249 u32 airtime_ac[8]; 250 251 int ack_signal; 252 struct ewma_avg_signal avg_ack_signal; 253 254 unsigned long changed; 255 256 struct mt76_connac_sta_key_conf bip; 257 258 struct { 259 u8 flowid_mask; 260 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; 261 } twt; 262 263 struct rcu_head rcu_head; 264 }; 265 266 struct mt7996_sta { 267 struct mt7996_sta_link deflink; /* must be first */ 268 struct mt7996_sta_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 269 u8 deflink_id; 270 u8 seclink_id; 271 272 struct mt7996_vif *vif; 273 }; 274 275 struct mt7996_vif_link { 276 struct mt76_vif_link mt76; /* must be first */ 277 278 struct mt7996_sta_link msta_link; 279 struct cfg80211_bitrate_mask bitrate_mask; 280 281 u8 mld_idx; 282 }; 283 284 struct mt7996_vif_link_info { 285 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 286 }; 287 288 struct mt7996_vif { 289 struct mt7996_vif_link deflink; /* must be first */ 290 struct mt76_vif_data mt76; 291 292 struct mt7996_vif_link_info link_info[IEEE80211_MLD_MAX_NUM_LINKS]; 293 294 u8 mld_group_idx; 295 u8 mld_remap_idx; 296 }; 297 298 /* crash-dump */ 299 struct mt7996_crash_data { 300 guid_t guid; 301 struct timespec64 timestamp; 302 303 u8 *memdump_buf; 304 size_t memdump_buf_len; 305 }; 306 307 struct mt7996_hif { 308 struct list_head list; 309 310 struct device *dev; 311 void __iomem *regs; 312 int irq; 313 314 enum pci_bus_speed speed; 315 enum pcie_link_width width; 316 }; 317 318 #define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24) 319 #define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4) 320 #define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0) 321 struct mt7996_wed_rro_addr { 322 __le32 head_low; 323 __le32 data; 324 }; 325 326 struct mt7996_wed_rro_session_id { 327 struct list_head list; 328 u16 id; 329 }; 330 331 struct mt7996_msdu_page { 332 struct list_head list; 333 334 struct mt76_queue *q; 335 dma_addr_t dma_addr; 336 void *buf; 337 }; 338 339 /* data1 */ 340 #define RRO_HIF_DATA1_LS_MASK BIT(30) 341 #define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16) 342 /* data4 */ 343 #define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0) 344 struct mt7996_rro_hif { 345 __le32 data0; 346 __le32 data1; 347 __le32 data2; 348 __le32 data3; 349 __le32 data4; 350 __le32 data5; 351 }; 352 353 #define MSDU_PAGE_INFO_OWNER_MASK BIT(31) 354 #define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0) 355 struct mt7996_msdu_page_info { 356 struct mt7996_rro_hif rxd[MT7996_MAX_HIF_RXD_IN_PG]; 357 __le32 pg_low; 358 __le32 data; 359 }; 360 361 #define MT7996_MAX_RRO_RRS_RING 4 362 struct mt7996_rro_queue_regs_emi { 363 struct { 364 __le16 idx; 365 __le16 rsv; 366 } ring[MT7996_MAX_RRO_RRS_RING]; 367 }; 368 369 struct mt7996_phy { 370 struct mt76_phy *mt76; 371 struct mt7996_dev *dev; 372 373 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 374 375 struct thermal_cooling_device *cdev; 376 u8 cdev_state; 377 u8 throttle_state; 378 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */ 379 380 u32 rxfilter; 381 u64 omac_mask; 382 383 u16 noise; 384 385 s16 coverage_class; 386 u8 slottime; 387 388 u16 beacon_rate; 389 390 u32 rx_ampdu_ts; 391 u32 ampdu_ref; 392 int txpower; 393 394 struct mt76_mib_stats mib; 395 struct mt76_channel_state state_ts; 396 397 u16 orig_chainmask; 398 u16 orig_antenna_mask; 399 400 bool has_aux_rx; 401 bool counter_reset; 402 bool rdd_tx_paused; 403 }; 404 405 struct mt7996_dev { 406 union { /* must be first */ 407 struct mt76_dev mt76; 408 struct mt76_phy mphy; 409 }; 410 411 struct mt7996_phy *radio_phy[MT7996_MAX_RADIOS]; 412 struct wiphy_radio radios[MT7996_MAX_RADIOS]; 413 struct wiphy_radio_freq_range radio_freqs[MT7996_MAX_RADIOS]; 414 415 struct mt7996_hif *hif2; 416 struct mt7996_reg_desc reg; 417 u8 q_id[MT7996_MAX_QUEUE]; 418 u32 q_int_mask[MT7996_MAX_QUEUE]; 419 u32 q_wfdma_mask; 420 421 u64 mld_idx_mask; 422 u64 mld_remap_idx_mask; 423 424 const struct mt76_bus_ops *bus_ops; 425 struct mt7996_phy phy; 426 427 /* monitor rx chain configured channel */ 428 struct cfg80211_chan_def rdd2_chandef; 429 struct mt7996_phy *rdd2_phy; 430 431 u16 chainmask; 432 u8 chainshift[__MT_MAX_BAND]; 433 u32 hif_idx; 434 435 struct work_struct init_work; 436 struct work_struct rc_work; 437 struct work_struct dump_work; 438 struct work_struct reset_work; 439 wait_queue_head_t reset_wait; 440 struct { 441 u32 state; 442 u32 wa_reset_count; 443 u32 wm_reset_count; 444 bool hw_full_reset:1; 445 bool hw_init_done:1; 446 bool restart:1; 447 } recovery; 448 449 /* protects coredump data */ 450 struct mutex dump_mutex; 451 #ifdef CONFIG_DEV_COREDUMP 452 struct { 453 struct mt7996_crash_data *crash_data; 454 } coredump; 455 #endif 456 457 struct list_head sta_rc_list; 458 struct list_head twt_list; 459 460 u32 hw_pattern; 461 462 u8 eeprom_mode; 463 bool has_eht:1; 464 465 struct { 466 struct { 467 void *ptr; 468 dma_addr_t phy_addr; 469 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN]; 470 struct { 471 void *ptr; 472 dma_addr_t phy_addr; 473 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN]; 474 struct { 475 void *ptr; 476 dma_addr_t phy_addr; 477 } session; 478 struct { 479 void *ptr; 480 dma_addr_t phy_addr; 481 } msdu_pg[MT7996_RRO_MSDU_PG_CR_CNT]; 482 struct { 483 struct mt7996_rro_queue_regs_emi *ptr; 484 dma_addr_t phy_addr; 485 } emi_rings_cpu; 486 struct { 487 struct mt7996_rro_queue_regs_emi *ptr; 488 dma_addr_t phy_addr; 489 } emi_rings_dma; 490 491 struct work_struct work; 492 struct list_head poll_list; 493 spinlock_t lock; 494 495 struct list_head page_cache; 496 struct list_head page_map[MT7996_RRO_MSDU_PG_HASH_SIZE]; 497 } wed_rro; 498 499 dma_addr_t npu_txd_addr[2 * MT7996_NPU_TXD_SIZE]; 500 501 bool ibf; 502 u8 fw_debug_wm; 503 u8 fw_debug_wa; 504 u8 fw_debug_bin; 505 u16 fw_debug_seq; 506 507 struct dentry *debugfs_dir; 508 struct rchan *relay_fwlog; 509 510 struct { 511 u16 table_mask; 512 u8 n_agrt; 513 } twt; 514 515 spinlock_t reg_lock; 516 517 u8 wtbl_size_group; 518 struct { 519 u8 type:4; 520 u8 fem:4; 521 } var; 522 }; 523 524 enum { 525 WFDMA0 = 0x0, 526 WFDMA1, 527 WFDMA_EXT, 528 __MT_WFDMA_MAX, 529 }; 530 531 enum rdd_idx { 532 MT_RDD_IDX_BAND2, /* RDD idx for band idx 2 */ 533 MT_RDD_IDX_BAND1, /* RDD idx for band idx 1 */ 534 MT_RDD_IDX_BACKGROUND, /* RDD idx for background chain */ 535 }; 536 537 enum mt7996_rdd_cmd { 538 RDD_STOP, 539 RDD_START, 540 RDD_DET_MODE, 541 RDD_RADAR_EMULATE, 542 RDD_START_TXQ = 20, 543 RDD_CAC_START = 50, 544 RDD_CAC_END, 545 RDD_NORMAL_START, 546 RDD_DISABLE_DFS_CAL, 547 RDD_PULSE_DBG, 548 RDD_READ_PULSE, 549 RDD_RESUME_BF, 550 RDD_IRQ_OFF, 551 }; 552 553 static inline int 554 mt7996_get_rdd_idx(struct mt7996_phy *phy, bool is_background) 555 { 556 if (!phy->mt76->cap.has_5ghz) 557 return -1; 558 559 if (is_background) 560 return MT_RDD_IDX_BACKGROUND; 561 562 if (phy->mt76->band_idx == MT_BAND2) 563 return MT_RDD_IDX_BAND2; 564 565 return MT_RDD_IDX_BAND1; 566 } 567 568 static inline struct mt7996_dev * 569 mt7996_hw_dev(struct ieee80211_hw *hw) 570 { 571 struct mt76_phy *phy = hw->priv; 572 573 return container_of(phy->dev, struct mt7996_dev, mt76); 574 } 575 576 static inline struct mt7996_phy * 577 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) 578 { 579 struct mt76_phy *phy = dev->mt76.phys[band]; 580 581 if (!phy) 582 return NULL; 583 584 return phy->priv; 585 } 586 587 static inline struct mt7996_phy * 588 mt7996_phy2(struct mt7996_dev *dev) 589 { 590 return __mt7996_phy(dev, MT_BAND1); 591 } 592 593 static inline struct mt7996_phy * 594 mt7996_phy3(struct mt7996_dev *dev) 595 { 596 return __mt7996_phy(dev, MT_BAND2); 597 } 598 599 static inline bool 600 mt7996_band_valid(struct mt7996_dev *dev, u8 band) 601 { 602 if (!is_mt7996(&dev->mt76)) 603 return band <= MT_BAND1; 604 605 return band <= MT_BAND2; 606 } 607 608 static inline struct mt7996_phy * 609 mt7996_band_phy(struct mt7996_dev *dev, enum nl80211_band band) 610 { 611 struct mt76_phy *mphy; 612 613 mphy = dev->mt76.band_phys[band]; 614 if (!mphy) 615 return NULL; 616 617 return mphy->priv; 618 } 619 620 static inline struct mt7996_vif_link * 621 mt7996_vif_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, int link_id) 622 { 623 return (struct mt7996_vif_link *)mt76_vif_link(&dev->mt76, vif, link_id); 624 } 625 626 static inline struct mt7996_phy * 627 mt7996_vif_link_phy(struct mt7996_vif_link *link) 628 { 629 struct mt76_phy *mphy = mt76_vif_link_phy(&link->mt76); 630 631 if (!mphy) 632 return NULL; 633 634 return mphy->priv; 635 } 636 637 static inline struct mt7996_vif_link * 638 mt7996_vif_conf_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, 639 struct ieee80211_bss_conf *link_conf) 640 { 641 return (struct mt7996_vif_link *)mt76_vif_conf_link(&dev->mt76, vif, 642 link_conf); 643 } 644 645 #define mt7996_for_each_phy(dev, phy) \ 646 for (int __i = 0; __i < ARRAY_SIZE((dev)->radio_phy); __i++) \ 647 if (((phy) = (dev)->radio_phy[__i]) != NULL) 648 649 extern const struct ieee80211_ops mt7996_ops; 650 extern struct pci_driver mt7996_pci_driver; 651 extern struct pci_driver mt7996_hif_driver; 652 653 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 654 void __iomem *mem_base, u32 device_id); 655 void mt7996_rro_hw_init(struct mt7996_dev *dev); 656 void mt7996_wfsys_reset(struct mt7996_dev *dev); 657 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 658 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif_link *link); 659 int mt7996_register_device(struct mt7996_dev *dev); 660 void mt7996_unregister_device(struct mt7996_dev *dev); 661 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif, 662 struct ieee80211_bss_conf *link_conf, 663 struct mt76_vif_link *mlink); 664 void mt7996_vif_link_remove(struct mt76_phy *mphy, struct ieee80211_vif *vif, 665 struct ieee80211_bss_conf *link_conf, 666 struct mt76_vif_link *mlink); 667 int mt7996_eeprom_init(struct mt7996_dev *dev); 668 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); 669 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, 670 struct ieee80211_channel *chan); 671 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); 672 bool mt7996_eeprom_has_background_radar(struct mt7996_dev *dev); 673 int mt7996_dma_init(struct mt7996_dev *dev); 674 void mt7996_dma_reset(struct mt7996_dev *dev, bool force); 675 void mt7996_dma_prefetch(struct mt7996_dev *dev); 676 void mt7996_dma_cleanup(struct mt7996_dev *dev); 677 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset); 678 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx, 679 int n_desc, int ring_base, struct mtk_wed_device *wed); 680 void mt7996_init_txpower(struct mt7996_phy *phy); 681 int mt7996_txbf_init(struct mt7996_dev *dev); 682 void mt7996_reset(struct mt7996_dev *dev); 683 int mt7996_run(struct mt7996_phy *phy); 684 int mt7996_mcu_init(struct mt7996_dev *dev); 685 int mt7996_mcu_init_firmware(struct mt7996_dev *dev); 686 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, 687 struct mt7996_vif_link *link, 688 struct mt7996_twt_flow *flow, 689 int cmd); 690 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, 691 struct ieee80211_bss_conf *link_conf, 692 struct mt76_vif_link *mlink, bool enable); 693 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, 694 struct ieee80211_bss_conf *link_conf, 695 struct mt76_vif_link *mlink, 696 struct mt7996_sta_link *msta_link, int enable); 697 int mt7996_mcu_update_bss_rfch(struct mt7996_phy *phy, 698 struct mt7996_vif_link *link); 699 int mt7996_mcu_add_sta(struct mt7996_dev *dev, 700 struct ieee80211_bss_conf *link_conf, 701 struct ieee80211_link_sta *link_sta, 702 struct mt7996_vif_link *link, 703 struct mt7996_sta_link *msta_link, 704 int conn_state, bool newly); 705 int mt7996_mcu_teardown_mld_sta(struct mt7996_dev *dev, 706 struct mt7996_vif_link *link, 707 struct mt7996_sta_link *msta_link); 708 void mt7996_mcu_update_sta_rec_bw(void *data, struct ieee80211_sta *sta); 709 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 710 struct ieee80211_ampdu_params *params, 711 struct ieee80211_vif *vif, bool enable); 712 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 713 struct ieee80211_ampdu_params *params, 714 struct ieee80211_vif *vif, bool enable); 715 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, 716 struct mt76_vif_link *mlink, 717 struct cfg80211_he_bss_color *he_bss_color); 718 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 719 struct ieee80211_bss_conf *link_conf, bool enabled); 720 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 721 struct ieee80211_bss_conf *link_conf, 722 struct mt7996_vif_link *link, u32 changed); 723 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, 724 struct mt7996_vif_link *link, 725 struct ieee80211_he_obss_pd *he_obss_pd); 726 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct mt7996_sta *msta, 727 struct ieee80211_vif *vif, u8 link_id, 728 bool changed); 729 int mt7996_set_channel(struct mt76_phy *mphy); 730 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); 731 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif, 732 struct ieee80211_bss_conf *link_conf); 733 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 734 void *data, u16 version); 735 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct mt7996_sta *msta, 736 void *data, u8 link_id, u32 field); 737 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); 738 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset, u8 *buf, u32 buf_len, 739 enum mt7996_eeprom_mode mode); 740 int mt7996_mcu_get_efuse_free_block(struct mt7996_dev *dev, u8 *block_num); 741 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap); 742 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); 743 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); 744 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); 745 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, 746 const struct mt7996_dfs_pulse *pulse); 747 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, 748 const struct mt7996_dfs_pattern *pattern); 749 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); 750 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); 751 int mt7996_mcu_set_protection(struct mt7996_phy *phy, struct mt7996_vif_link *link, 752 u8 ht_mode, bool use_cts_prot); 753 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif, 754 struct ieee80211_bss_conf *link_conf); 755 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); 756 int mt7996_mcu_get_temperature(struct mt7996_phy *phy); 757 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state); 758 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable); 759 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy); 760 int mt7996_mcu_rdd_resume_tx(struct mt7996_phy *phy); 761 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 rdd_idx, u8 val); 762 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, 763 struct cfg80211_chan_def *chandef); 764 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx, 765 u16 rate_idx, bool beacon); 766 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); 767 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); 768 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val); 769 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 770 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); 771 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); 772 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev); 773 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); 774 void mt7996_mcu_exit(struct mt7996_dev *dev); 775 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag); 776 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id); 777 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled); 778 int mt7996_mcu_set_dup_wtbl(struct mt7996_dev *dev); 779 int mt7996_mcu_mld_reconf_stop_link(struct mt7996_dev *dev, 780 struct ieee80211_vif *vif, 781 u16 removed_links); 782 int mt7996_mcu_mld_link_oper(struct mt7996_dev *dev, 783 struct ieee80211_bss_conf *link_conf, 784 struct mt7996_vif_link *link, bool add); 785 786 static inline bool mt7996_has_hwrro(struct mt7996_dev *dev) 787 { 788 return dev->mt76.hwrro_mode != MT76_HWRRO_OFF; 789 } 790 791 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 792 { 793 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) + 794 mt7996_band_valid(dev, MT_BAND2)), 795 MT7996_WTBL_BMC_SIZE); 796 } 797 798 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev) 799 { 800 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE; 801 } 802 803 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 804 u32 clear, u32 set); 805 806 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) 807 { 808 if (dev->hif2) 809 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); 810 else 811 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 812 813 tasklet_schedule(&dev->mt76.irq_tasklet); 814 } 815 816 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) 817 { 818 if (dev->hif2) 819 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); 820 else 821 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 822 } 823 824 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 825 size_t len); 826 827 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy) 828 { 829 int max_nss = hweight16(phy->orig_antenna_mask); 830 int cur_nss = hweight8(phy->mt76->antenna_mask); 831 u16 tx_chainmask = phy->mt76->chainmask; 832 833 if (cur_nss != max_nss) 834 return tx_chainmask; 835 836 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx); 837 } 838 839 static inline bool mt7996_has_wa(struct mt7996_dev *dev) 840 { 841 return !is_mt7990(&dev->mt76); 842 } 843 844 static inline bool mt7996_has_ext_eeprom(struct mt7996_dev *dev) 845 { 846 return !is_mt7996(&dev->mt76); 847 } 848 849 void mt7996_mac_init(struct mt7996_dev *dev); 850 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); 851 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); 852 void mt7996_mac_reset_counters(struct mt7996_phy *phy); 853 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); 854 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); 855 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 856 struct sk_buff *skb, struct mt76_wcid *wcid, 857 struct ieee80211_key_conf *key, int pid, 858 enum mt76_txq_id qid, u32 changed); 859 void mt7996_mac_update_beacons(struct mt7996_phy *phy); 860 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy); 861 void mt7996_mac_work(struct work_struct *work); 862 void mt7996_mac_reset_work(struct work_struct *work); 863 void mt7996_mac_dump_work(struct work_struct *work); 864 void mt7996_mac_sta_rc_work(struct work_struct *work); 865 void mt7996_mac_update_stats(struct mt7996_phy *phy); 866 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 867 struct mt7996_vif_link *link, 868 struct mt7996_sta_link *msta_link, 869 u8 flowid); 870 void mt7996_mac_sta_remove_link(struct mt7996_dev *dev, 871 struct ieee80211_sta *sta, 872 unsigned int link_id, bool flush); 873 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 874 struct ieee80211_sta *sta, 875 struct ieee80211_twt_setup *twt); 876 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 877 enum mt76_txq_id qid, struct mt76_wcid *wcid, 878 struct ieee80211_sta *sta, 879 struct mt76_tx_info *tx_info); 880 void mt7996_tx_token_put(struct mt7996_dev *dev); 881 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 882 struct sk_buff *skb, u32 *info); 883 void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev); 884 int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q, 885 dma_addr_t dma_addr, void *data); 886 void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data); 887 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 888 void mt7996_stats_work(struct work_struct *work); 889 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); 890 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); 891 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy); 892 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); 893 void mt7996_update_channel(struct mt76_phy *mphy); 894 int mt7996_init_debugfs(struct mt7996_dev *dev); 895 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); 896 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); 897 int mt7996_mcu_add_key(struct mt76_dev *dev, struct mt7996_vif_link *link, 898 struct ieee80211_key_conf *key, int mcu_cmd, 899 struct mt76_wcid *wcid, enum set_key_cmd cmd); 900 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, 901 struct mt7996_vif_link *link, 902 struct mt7996_sta_link *msta_link, 903 struct ieee80211_key_conf *key); 904 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, 905 struct ieee80211_vif *vif, 906 struct mt7996_vif_link *link, 907 struct mt7996_sta_link *msta_link); 908 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode); 909 int mt7996_mcu_set_emlsr_mode(struct mt7996_dev *dev, 910 struct ieee80211_vif *vif, 911 struct ieee80211_sta *sta, 912 struct ieee80211_eml_params *eml_params); 913 #ifdef CONFIG_MAC80211_DEBUGFS 914 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 915 struct ieee80211_sta *sta, struct dentry *dir); 916 void mt7996_link_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 917 struct ieee80211_link_sta *link_sta, 918 struct dentry *dir); 919 #endif 920 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, 921 bool hif2, int *irq); 922 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); 923 924 #ifdef CONFIG_MTK_DEBUG 925 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir); 926 #endif 927 928 int mt7996_dma_rro_init(struct mt7996_dev *dev); 929 void mt7996_dma_rro_start(struct mt7996_dev *dev); 930 931 #ifdef CONFIG_MT7996_NPU 932 int __mt7996_npu_hw_init(struct mt7996_dev *dev); 933 int mt7996_npu_hw_init(struct mt7996_dev *dev); 934 int mt7996_npu_hw_stop(struct mt7996_dev *dev); 935 int mt7996_npu_rx_queues_init(struct mt7996_dev *dev); 936 #else 937 static inline int __mt7996_npu_hw_init(struct mt7996_dev *dev) 938 { 939 return 0; 940 } 941 942 static inline int mt7996_npu_hw_init(struct mt7996_dev *dev) 943 { 944 return 0; 945 } 946 947 static inline int mt7996_npu_hw_stop(struct mt7996_dev *dev) 948 { 949 return 0; 950 } 951 952 static inline int mt7996_npu_rx_queues_init(struct mt7996_dev *dev) 953 { 954 return 0; 955 } 956 #endif /* CONFIG_MT7996_NPU */ 957 958 #endif 959