1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_HW_TYPES_H 27 #define DC_HW_TYPES_H 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "signal_types.h" 32 33 /****************************************************************************** 34 * Data types for Virtual HW Layer of DAL3. 35 * (see DAL3 design documents for HW Layer definition) 36 * 37 * The intended uses are: 38 * 1. Generation pseudocode sequences for HW programming. 39 * 2. Implementation of real HW programming by HW Sequencer of DAL3. 40 * 41 * Note: do *not* add any types which are *not* used for HW programming - this 42 * will ensure separation of Logic layer from HW layer. 43 ******************************************************************************/ 44 45 union large_integer { 46 struct { 47 uint32_t low_part; 48 int32_t high_part; 49 }; 50 51 struct { 52 uint32_t low_part; 53 int32_t high_part; 54 } u; 55 56 int64_t quad_part; 57 }; 58 59 #define PHYSICAL_ADDRESS_LOC union large_integer 60 61 enum dc_plane_addr_type { 62 PLN_ADDR_TYPE_GRAPHICS = 0, 63 PLN_ADDR_TYPE_3DLUT, 64 PLN_ADDR_TYPE_GRPH_STEREO, 65 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, 66 PLN_ADDR_TYPE_RGBEA 67 }; 68 69 struct dc_plane_address { 70 enum dc_plane_addr_type type; 71 uint8_t tmz_surface; 72 union { 73 struct{ 74 PHYSICAL_ADDRESS_LOC addr; 75 PHYSICAL_ADDRESS_LOC cursor_cache_addr; 76 PHYSICAL_ADDRESS_LOC meta_addr; 77 union large_integer dcc_const_color; 78 } grph; 79 80 struct { 81 PHYSICAL_ADDRESS_LOC addr; 82 } lut3d; 83 84 /*stereo*/ 85 struct { 86 PHYSICAL_ADDRESS_LOC left_addr; 87 PHYSICAL_ADDRESS_LOC left_meta_addr; 88 union large_integer left_dcc_const_color; 89 90 PHYSICAL_ADDRESS_LOC right_addr; 91 PHYSICAL_ADDRESS_LOC right_meta_addr; 92 union large_integer right_dcc_const_color; 93 94 PHYSICAL_ADDRESS_LOC left_alpha_addr; 95 PHYSICAL_ADDRESS_LOC left_alpha_meta_addr; 96 union large_integer left_alpha_dcc_const_color; 97 98 PHYSICAL_ADDRESS_LOC right_alpha_addr; 99 PHYSICAL_ADDRESS_LOC right_alpha_meta_addr; 100 union large_integer right_alpha_dcc_const_color; 101 } grph_stereo; 102 103 /*video progressive*/ 104 struct { 105 PHYSICAL_ADDRESS_LOC luma_addr; 106 PHYSICAL_ADDRESS_LOC luma_meta_addr; 107 union large_integer luma_dcc_const_color; 108 109 PHYSICAL_ADDRESS_LOC chroma_addr; 110 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 111 union large_integer chroma_dcc_const_color; 112 } video_progressive; 113 114 struct { 115 PHYSICAL_ADDRESS_LOC addr; 116 PHYSICAL_ADDRESS_LOC meta_addr; 117 union large_integer dcc_const_color; 118 119 PHYSICAL_ADDRESS_LOC alpha_addr; 120 PHYSICAL_ADDRESS_LOC alpha_meta_addr; 121 union large_integer alpha_dcc_const_color; 122 } rgbea; 123 }; 124 125 union large_integer page_table_base; 126 127 uint8_t vmid; 128 }; 129 130 struct dc_size { 131 int width; 132 int height; 133 }; 134 135 struct rect { 136 int x; 137 int y; 138 int width; 139 int height; 140 }; 141 142 struct plane_size { 143 /* Graphic surface pitch in pixels. 144 * In LINEAR_GENERAL mode, pitch 145 * is 32 pixel aligned. 146 */ 147 int surface_pitch; 148 int chroma_pitch; 149 struct rect surface_size; 150 struct rect chroma_size; 151 }; 152 153 struct dc_plane_dcc_param { 154 bool enable; 155 156 int meta_pitch; 157 bool independent_64b_blks; 158 uint8_t dcc_ind_blk; 159 160 int meta_pitch_c; 161 bool independent_64b_blks_c; 162 uint8_t dcc_ind_blk_c; 163 }; 164 165 /*Displayable pixel format in fb*/ 166 enum surface_pixel_format { 167 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 168 /*TOBE REMOVED paletta 256 colors*/ 169 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = 170 SURFACE_PIXEL_FORMAT_GRPH_BEGIN, 171 /*16 bpp*/ 172 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 173 /*16 bpp*/ 174 SURFACE_PIXEL_FORMAT_GRPH_RGB565, 175 /*32 bpp*/ 176 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 177 /*32 bpp swaped*/ 178 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 179 180 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 181 /*swaped*/ 182 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 183 /*TOBE REMOVED swaped, XR_BIAS has no differance 184 * for pixel layout than previous and we can 185 * delete this after discusion*/ 186 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, 187 /*64 bpp */ 188 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 189 /*swapped*/ 190 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, 191 /*float*/ 192 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 193 /*swaped & float*/ 194 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 195 /*grow graphics here if necessary */ 196 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 197 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 198 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 199 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 200 SURFACE_PIXEL_FORMAT_GRPH_RGBE, 201 SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, 202 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 203 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = 204 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 205 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 206 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 207 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 208 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 209 SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010 = 210 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 211 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 212 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 213 SURFACE_PIXEL_FORMAT_INVALID 214 215 /*grow 444 video here if necessary */ 216 }; 217 218 219 220 /* Pixel format */ 221 enum dc_pixel_format { 222 /*graph*/ 223 PIXEL_FORMAT_UNINITIALIZED, 224 PIXEL_FORMAT_INDEX8, 225 PIXEL_FORMAT_RGB565, 226 PIXEL_FORMAT_ARGB8888, 227 PIXEL_FORMAT_ARGB2101010, 228 PIXEL_FORMAT_ARGB2101010_XRBIAS, 229 PIXEL_FORMAT_FP16, 230 /*video*/ 231 PIXEL_FORMAT_420BPP8, 232 PIXEL_FORMAT_420BPP10, 233 /*end of pixel format definition*/ 234 PIXEL_FORMAT_INVALID, 235 236 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, 237 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, 238 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, 239 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, 240 PIXEL_FORMAT_UNKNOWN 241 }; 242 243 /* 244 * This structure holds a surface address. There could be multiple addresses 245 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 246 * as frame durations and DCC format can also be set. 247 */ 248 #define DC_MAX_DIRTY_RECTS 3 249 struct dc_flip_addrs { 250 struct dc_plane_address address; 251 unsigned long long flip_timestamp_in_us; 252 bool flip_immediate; 253 /* TODO: add flip duration for FreeSync */ 254 bool triplebuffer_flips; 255 unsigned int dirty_rect_count; 256 struct rect dirty_rects[DC_MAX_DIRTY_RECTS]; 257 }; 258 259 enum tile_split_values { 260 DC_DISPLAY_MICRO_TILING = 0x0, 261 DC_THIN_MICRO_TILING = 0x1, 262 DC_DEPTH_MICRO_TILING = 0x2, 263 DC_ROTATED_MICRO_TILING = 0x3, 264 }; 265 266 enum tripleBuffer_enable { 267 DC_TRIPLEBUFFER_DISABLE = 0x0, 268 DC_TRIPLEBUFFER_ENABLE = 0x1, 269 }; 270 enum tile_split_values_new { 271 DC_SURF_TILE_SPLIT_1KB = 0x4, 272 }; 273 274 enum otg_pwa_sync_mode { 275 DC_OTG_PWA_FRAME_SYNC_MODE_VSYNC = 0x0, 276 DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP = 0x1, 277 }; 278 struct otc_pwa_frame_sync { 279 enum otg_pwa_sync_mode pwa_sync_mode; 280 uint32_t pwa_frame_sync_line_offset; 281 }; 282 283 /* TODO: These values come from hardware spec. We need to readdress this 284 * if they ever change. 285 */ 286 enum array_mode_values { 287 DC_ARRAY_LINEAR_GENERAL = 0, 288 DC_ARRAY_LINEAR_ALLIGNED, 289 DC_ARRAY_1D_TILED_THIN1, 290 DC_ARRAY_1D_TILED_THICK, 291 DC_ARRAY_2D_TILED_THIN1, 292 DC_ARRAY_PRT_TILED_THIN1, 293 DC_ARRAY_PRT_2D_TILED_THIN1, 294 DC_ARRAY_2D_TILED_THICK, 295 DC_ARRAY_2D_TILED_X_THICK, 296 DC_ARRAY_PRT_TILED_THICK, 297 DC_ARRAY_PRT_2D_TILED_THICK, 298 DC_ARRAY_PRT_3D_TILED_THIN1, 299 DC_ARRAY_3D_TILED_THIN1, 300 DC_ARRAY_3D_TILED_THICK, 301 DC_ARRAY_3D_TILED_X_THICK, 302 DC_ARRAY_PRT_3D_TILED_THICK, 303 }; 304 305 enum tile_mode_values { 306 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 307 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 308 }; 309 310 enum swizzle_mode_values { 311 DC_SW_LINEAR = 0, 312 DC_SW_256B_S = 1, 313 DC_SW_256_D = 2, 314 DC_SW_256_R = 3, 315 DC_SW_4KB_S = 5, 316 DC_SW_4KB_D = 6, 317 DC_SW_4KB_R = 7, 318 DC_SW_64KB_S = 9, 319 DC_SW_64KB_D = 10, 320 DC_SW_64KB_R = 11, 321 DC_SW_VAR_S = 13, 322 DC_SW_VAR_D = 14, 323 DC_SW_VAR_R = 15, 324 DC_SW_64KB_S_T = 17, 325 DC_SW_64KB_D_T = 18, 326 DC_SW_4KB_S_X = 21, 327 DC_SW_4KB_D_X = 22, 328 DC_SW_4KB_R_X = 23, 329 DC_SW_64KB_S_X = 25, 330 DC_SW_64KB_D_X = 26, 331 DC_SW_64KB_R_X = 27, 332 DC_SW_VAR_S_X = 29, 333 DC_SW_VAR_D_X = 30, 334 DC_SW_VAR_R_X = 31, 335 DC_SW_MAX = 32, 336 DC_SW_UNKNOWN = DC_SW_MAX 337 }; 338 339 // Definition of swizzle modes with addr3 ASICs 340 enum swizzle_mode_addr3_values { 341 DC_ADDR3_SW_LINEAR = 0, 342 DC_ADDR3_SW_256B_2D = 1, 343 DC_ADDR3_SW_4KB_2D = 2, 344 DC_ADDR3_SW_64KB_2D = 3, 345 DC_ADDR3_SW_256KB_2D = 4, 346 DC_ADDR3_SW_4KB_3D = 5, 347 DC_ADDR3_SW_64KB_3D = 6, 348 DC_ADDR3_SW_256KB_3D = 7, 349 DC_ADDR3_SW_MAX = 8, 350 DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX 351 }; 352 353 enum dc_gfxversion { 354 DcGfxVersion7 = 0, 355 DcGfxVersion8, 356 DcGfxVersion9, 357 DcGfxVersion10, 358 DcGfxVersion11, 359 DcGfxAddr3, 360 DcGfxVersionUnknown 361 }; 362 363 struct dc_tiling_info { 364 unsigned int gfxversion; // Specifies which part of the union to use. Must use DalGfxVersion enum 365 union { 366 struct { 367 /* Specifies the number of memory banks for tiling 368 * purposes. 369 * Only applies to 2D and 3D tiling modes. 370 * POSSIBLE VALUES: 2,4,8,16 371 */ 372 unsigned int num_banks; 373 /* Specifies the number of tiles in the x direction 374 * to be incorporated into the same bank. 375 * Only applies to 2D and 3D tiling modes. 376 * POSSIBLE VALUES: 1,2,4,8 377 */ 378 unsigned int bank_width; 379 unsigned int bank_width_c; 380 /* Specifies the number of tiles in the y direction to 381 * be incorporated into the same bank. 382 * Only applies to 2D and 3D tiling modes. 383 * POSSIBLE VALUES: 1,2,4,8 384 */ 385 unsigned int bank_height; 386 unsigned int bank_height_c; 387 /* Specifies the macro tile aspect ratio. Only applies 388 * to 2D and 3D tiling modes. 389 */ 390 unsigned int tile_aspect; 391 unsigned int tile_aspect_c; 392 /* Specifies the number of bytes that will be stored 393 * contiguously for each tile. 394 * If the tile data requires more storage than this 395 * amount, it is split into multiple slices. 396 * This field must not be larger than 397 * GB_ADDR_CONFIG.DRAM_ROW_SIZE. 398 * Only applies to 2D and 3D tiling modes. 399 * For color render targets, TILE_SPLIT >= 256B. 400 */ 401 enum tile_split_values tile_split; 402 enum tile_split_values tile_split_c; 403 /* Specifies the addressing within a tile. 404 * 0x0 - DISPLAY_MICRO_TILING 405 * 0x1 - THIN_MICRO_TILING 406 * 0x2 - DEPTH_MICRO_TILING 407 * 0x3 - ROTATED_MICRO_TILING 408 */ 409 enum tile_mode_values tile_mode; 410 enum tile_mode_values tile_mode_c; 411 /* Specifies the number of pipes and how they are 412 * interleaved in the surface. 413 * Refer to memory addressing document for complete 414 * details and constraints. 415 */ 416 unsigned int pipe_config; 417 /* Specifies the tiling mode of the surface. 418 * THIN tiles use an 8x8x1 tile size. 419 * THICK tiles use an 8x8x4 tile size. 420 * 2D tiling modes rotate banks for successive Z slices 421 * 3D tiling modes rotate pipes and banks for Z slices 422 * Refer to memory addressing document for complete 423 * details and constraints. 424 */ 425 enum array_mode_values array_mode; 426 } gfx8; 427 428 struct { 429 enum swizzle_mode_values swizzle; 430 unsigned int num_pipes; 431 unsigned int max_compressed_frags; 432 unsigned int pipe_interleave; 433 434 unsigned int num_banks; 435 unsigned int num_shader_engines; 436 unsigned int num_rb_per_se; 437 bool shaderEnable; 438 439 bool meta_linear; 440 bool rb_aligned; 441 bool pipe_aligned; 442 unsigned int num_pkrs; 443 } gfx9;/*gfx9, gfx10 and above*/ 444 struct { 445 enum swizzle_mode_addr3_values swizzle; 446 } gfx_addr3;/*gfx with addr3 and above*/ 447 }; 448 449 struct { 450 bool avoid_full_update_on_tiling_change; 451 } flags; 452 }; 453 454 /* Rotation angle */ 455 enum dc_rotation_angle { 456 ROTATION_ANGLE_0 = 0, 457 ROTATION_ANGLE_90, 458 ROTATION_ANGLE_180, 459 ROTATION_ANGLE_270, 460 ROTATION_ANGLE_COUNT 461 }; 462 463 enum dc_scan_direction { 464 SCAN_DIRECTION_UNKNOWN = 0, 465 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ 466 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ 467 }; 468 469 /** 470 * struct dc_cursor_position: Hardware cursor data. 471 * 472 * This struct keeps the action information related to the cursor that will be 473 * sent and received from our DC core. 474 */ 475 struct dc_cursor_position { 476 /** 477 * @x: It represents the top left abscissa coordinate of the cursor. 478 */ 479 uint32_t x; 480 481 /** 482 * @y: It is the top ordinate of the cursor coordinate. 483 */ 484 uint32_t y; 485 486 /** 487 * @x_hotspot: Define the abscissa point where mouse click happens. 488 */ 489 uint32_t x_hotspot; 490 491 /** 492 * @y_hotspot: Define the ordinate point where mouse click happens. 493 */ 494 uint32_t y_hotspot; 495 496 /** 497 * @enable: This parameter indicates whether hardware cursor should be 498 * enabled. 499 */ 500 bool enable; 501 502 /** 503 * @translate_by_source: Translate cursor x/y by the source rectangle 504 * for each plane. 505 */ 506 bool translate_by_source; 507 508 /** 509 * @use_viewport_for_clip: Use viewport position for clip_x calculation 510 * instead of clip_rect. Required to protect against clip being overwritten 511 */ 512 bool use_viewport_for_clip; 513 }; 514 515 struct dc_cursor_mi_param { 516 unsigned int pixel_clk_khz; 517 unsigned int ref_clk_khz; 518 struct rect viewport; 519 struct rect recout; 520 struct fixed31_32 h_scale_ratio; 521 struct fixed31_32 v_scale_ratio; 522 enum dc_rotation_angle rotation; 523 bool mirror; 524 struct dc_stream_state *stream; 525 }; 526 527 /* IPP related types */ 528 529 enum { 530 GAMMA_RGB_256_ENTRIES = 256, 531 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024, 532 GAMMA_CS_TFM_1D_ENTRIES = 4096, 533 GAMMA_CUSTOM_ENTRIES = 4096, 534 GAMMA_MAX_ENTRIES = 4096 535 }; 536 537 enum dc_gamma_type { 538 GAMMA_RGB_256 = 1, 539 GAMMA_RGB_FLOAT_1024 = 2, 540 GAMMA_CS_TFM_1D = 3, 541 GAMMA_CUSTOM = 4, 542 }; 543 544 struct dc_csc_transform { 545 uint16_t matrix[12]; 546 bool enable_adjustment; 547 }; 548 549 struct dc_rgb_fixed { 550 struct fixed31_32 red; 551 struct fixed31_32 green; 552 struct fixed31_32 blue; 553 }; 554 555 struct dc_gamma { 556 struct kref refcount; 557 enum dc_gamma_type type; 558 unsigned int num_entries; 559 560 struct dc_gamma_entries { 561 struct fixed31_32 red[GAMMA_MAX_ENTRIES]; 562 struct fixed31_32 green[GAMMA_MAX_ENTRIES]; 563 struct fixed31_32 blue[GAMMA_MAX_ENTRIES]; 564 } entries; 565 566 /* private to DC core */ 567 struct dc_context *ctx; 568 569 /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT. 570 * is_logical_identity indicates the given gamma ramp regardless of type is identity. 571 */ 572 bool is_identity; 573 }; 574 575 /* Used by both ipp amd opp functions*/ 576 /* TODO: to be consolidated with enum color_space */ 577 578 /** 579 * enum dc_cursor_color_format - DC cursor programming mode 580 * 581 * This enum is for programming CURSOR_MODE register field. What this register 582 * should be programmed to depends on OS requested cursor shape flags and what 583 * we stored in the cursor surface. 584 */ 585 enum dc_cursor_color_format { 586 CURSOR_MODE_MONO, 587 CURSOR_MODE_COLOR_1BIT_AND, 588 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, 589 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA, 590 CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED, 591 CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED 592 }; 593 594 /* 595 * This is all the parameters required by DAL in order to update the cursor 596 * attributes, including the new cursor image surface address, size, hotspot 597 * location, color format, etc. 598 */ 599 600 union dc_cursor_attribute_flags { 601 struct { 602 uint32_t ENABLE_MAGNIFICATION:1; 603 uint32_t INVERSE_TRANSPARENT_CLAMPING:1; 604 uint32_t HORIZONTAL_MIRROR:1; 605 uint32_t VERTICAL_MIRROR:1; 606 uint32_t INVERT_PIXEL_DATA:1; 607 uint32_t ZERO_EXPANSION:1; 608 uint32_t MIN_MAX_INVERT:1; 609 uint32_t ENABLE_CURSOR_DEGAMMA:1; 610 uint32_t RESERVED:24; 611 } bits; 612 uint32_t value; 613 }; 614 615 struct dc_cursor_attributes { 616 /** 617 * @address: This field represents the framebuffer address associated 618 * with the cursor. It is important to highlight that this address is 619 * divided into a high and low parts. 620 */ 621 PHYSICAL_ADDRESS_LOC address; 622 623 /** 624 * @pitch: Cursor line stride. 625 */ 626 uint32_t pitch; 627 628 /** 629 * @width: Width should correspond to cursor surface width. 630 */ 631 uint32_t width; 632 /** 633 * @heigh: Height should correspond to cursor surface heigh. 634 */ 635 uint32_t height; 636 637 /** 638 * @color_format: DC cursor programming mode. 639 */ 640 enum dc_cursor_color_format color_format; 641 /** 642 * @sdr_white_level: Boosting (SDR) cursor in HDR mode. 643 */ 644 uint32_t sdr_white_level; 645 646 /** 647 * @rotation_angle: In case we support HW Cursor rotation in the future 648 */ 649 enum dc_rotation_angle rotation_angle; 650 651 union dc_cursor_attribute_flags attribute_flags; 652 }; 653 654 struct dpp_cursor_attributes { 655 int bias; 656 int scale; 657 }; 658 659 /* OPP */ 660 661 enum dc_color_space { 662 COLOR_SPACE_UNKNOWN, 663 COLOR_SPACE_SRGB, 664 COLOR_SPACE_XR_RGB, 665 COLOR_SPACE_SRGB_LIMITED, 666 COLOR_SPACE_MSREF_SCRGB, 667 COLOR_SPACE_YCBCR601, 668 COLOR_SPACE_YCBCR709, 669 COLOR_SPACE_XV_YCC_709, 670 COLOR_SPACE_XV_YCC_601, 671 COLOR_SPACE_YCBCR601_LIMITED, 672 COLOR_SPACE_YCBCR709_LIMITED, 673 COLOR_SPACE_2020_RGB_FULLRANGE, 674 COLOR_SPACE_2020_RGB_LIMITEDRANGE, 675 COLOR_SPACE_2020_YCBCR_LIMITED, 676 COLOR_SPACE_2020_YCBCR_FULL, 677 COLOR_SPACE_ADOBERGB, 678 COLOR_SPACE_DCIP3, 679 COLOR_SPACE_DISPLAYNATIVE, 680 COLOR_SPACE_DOLBYVISION, 681 COLOR_SPACE_APPCTRL, 682 COLOR_SPACE_CUSTOMPOINTS, 683 COLOR_SPACE_YCBCR709_BLACK, 684 COLOR_SPACE_2020_YCBCR = COLOR_SPACE_2020_YCBCR_LIMITED, 685 }; 686 687 enum dc_dither_option { 688 DITHER_OPTION_DEFAULT, 689 DITHER_OPTION_DISABLE, 690 DITHER_OPTION_FM6, 691 DITHER_OPTION_FM8, 692 DITHER_OPTION_FM10, 693 DITHER_OPTION_SPATIAL6_FRAME_RANDOM, 694 DITHER_OPTION_SPATIAL8_FRAME_RANDOM, 695 DITHER_OPTION_SPATIAL10_FRAME_RANDOM, 696 DITHER_OPTION_SPATIAL6, 697 DITHER_OPTION_SPATIAL8, 698 DITHER_OPTION_SPATIAL10, 699 DITHER_OPTION_TRUN6, 700 DITHER_OPTION_TRUN8, 701 DITHER_OPTION_TRUN10, 702 DITHER_OPTION_TRUN10_SPATIAL8, 703 DITHER_OPTION_TRUN10_SPATIAL6, 704 DITHER_OPTION_TRUN10_FM8, 705 DITHER_OPTION_TRUN10_FM6, 706 DITHER_OPTION_TRUN10_SPATIAL8_FM6, 707 DITHER_OPTION_SPATIAL10_FM8, 708 DITHER_OPTION_SPATIAL10_FM6, 709 DITHER_OPTION_TRUN8_SPATIAL6, 710 DITHER_OPTION_TRUN8_FM6, 711 DITHER_OPTION_SPATIAL8_FM6, 712 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6, 713 DITHER_OPTION_INVALID 714 }; 715 716 enum dc_quantization_range { 717 QUANTIZATION_RANGE_UNKNOWN, 718 QUANTIZATION_RANGE_FULL, 719 QUANTIZATION_RANGE_LIMITED 720 }; 721 722 enum dc_dynamic_expansion { 723 DYN_EXPANSION_AUTO, 724 DYN_EXPANSION_DISABLE 725 }; 726 727 /* XFM */ 728 729 /* used in struct dc_plane_state */ 730 struct scaling_taps { 731 uint32_t v_taps; 732 uint32_t h_taps; 733 uint32_t v_taps_c; 734 uint32_t h_taps_c; 735 bool integer_scaling; 736 }; 737 738 enum dc_timing_standard { 739 DC_TIMING_STANDARD_UNDEFINED, 740 DC_TIMING_STANDARD_DMT, 741 DC_TIMING_STANDARD_GTF, 742 DC_TIMING_STANDARD_CVT, 743 DC_TIMING_STANDARD_CVT_RB, 744 DC_TIMING_STANDARD_CEA770, 745 DC_TIMING_STANDARD_CEA861, 746 DC_TIMING_STANDARD_HDMI, 747 DC_TIMING_STANDARD_TV_NTSC, 748 DC_TIMING_STANDARD_TV_NTSC_J, 749 DC_TIMING_STANDARD_TV_PAL, 750 DC_TIMING_STANDARD_TV_PAL_M, 751 DC_TIMING_STANDARD_TV_PAL_CN, 752 DC_TIMING_STANDARD_TV_SECAM, 753 DC_TIMING_STANDARD_EXPLICIT, 754 /*!< For explicit timings from EDID, VBIOS, etc.*/ 755 DC_TIMING_STANDARD_USER_OVERRIDE, 756 /*!< For mode timing override by user*/ 757 DC_TIMING_STANDARD_MAX 758 }; 759 760 enum dc_color_depth { 761 COLOR_DEPTH_UNDEFINED, 762 COLOR_DEPTH_666, 763 COLOR_DEPTH_888, 764 COLOR_DEPTH_101010, 765 COLOR_DEPTH_121212, 766 COLOR_DEPTH_141414, 767 COLOR_DEPTH_161616, 768 COLOR_DEPTH_999, 769 COLOR_DEPTH_111111, 770 COLOR_DEPTH_COUNT 771 }; 772 773 enum dc_pixel_encoding { 774 PIXEL_ENCODING_UNDEFINED, 775 PIXEL_ENCODING_RGB, 776 PIXEL_ENCODING_YCBCR422, 777 PIXEL_ENCODING_YCBCR444, 778 PIXEL_ENCODING_YCBCR420, 779 PIXEL_ENCODING_COUNT 780 }; 781 782 enum dc_aspect_ratio { 783 ASPECT_RATIO_NO_DATA, 784 ASPECT_RATIO_4_3, 785 ASPECT_RATIO_16_9, 786 ASPECT_RATIO_64_27, 787 ASPECT_RATIO_256_135, 788 ASPECT_RATIO_FUTURE 789 }; 790 791 enum scanning_type { 792 SCANNING_TYPE_NODATA = 0, 793 SCANNING_TYPE_OVERSCAN, 794 SCANNING_TYPE_UNDERSCAN, 795 SCANNING_TYPE_FUTURE, 796 SCANNING_TYPE_UNDEFINED 797 }; 798 799 struct dc_crtc_timing_flags { 800 uint32_t INTERLACE :1; 801 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, 802 it is positive polarity --reversed with dal1 or video bios define*/ 803 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, 804 it is positive polarity --reversed with dal1 or video bios define*/ 805 806 uint32_t HORZ_COUNT_BY_TWO:1; 807 808 uint32_t EXCLUSIVE_3D :1; /* if this bit set, 809 timing can be driven in 3D format only 810 and there is no corresponding 2D timing*/ 811 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity 812 (right eye = '1', left eye = '0') */ 813 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled 814 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/ 815 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, 816 because corresponding 2D timing also present in the list*/ 817 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing 818 and we want to match priority of corresponding 3D timing*/ 819 uint32_t Y_ONLY :1; 820 821 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ 822 uint32_t DTD_COUNTER :5; /* values 1 to 16 */ 823 824 uint32_t FORCE_HDR :1; 825 826 /* HDMI 2.0 - Support scrambling for TMDS character 827 * rates less than or equal to 340Mcsc */ 828 uint32_t LTE_340MCSC_SCRAMBLE:1; 829 830 uint32_t DSC : 1; /* Use DSC with this timing */ 831 uint32_t VBLANK_SYNCHRONIZABLE: 1; 832 }; 833 834 enum dc_timing_3d_format { 835 TIMING_3D_FORMAT_NONE, 836 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/ 837 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/ 838 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/ 839 /* for active DP-HDMI dongle*/ 840 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/ 841 TIMING_3D_FORMAT_HW_FRAME_PACKING, 842 TIMING_3D_FORMAT_SW_FRAME_PACKING, 843 TIMING_3D_FORMAT_ROW_INTERLEAVE, 844 TIMING_3D_FORMAT_COLUMN_INTERLEAVE, 845 TIMING_3D_FORMAT_PIXEL_INTERLEAVE, 846 TIMING_3D_FORMAT_SIDE_BY_SIDE, 847 TIMING_3D_FORMAT_TOP_AND_BOTTOM, 848 TIMING_3D_FORMAT_SBS_SW_PACKED, 849 /* Side-by-side, packed by application/driver into 2D frame*/ 850 TIMING_3D_FORMAT_TB_SW_PACKED, 851 /* Top-and-bottom, packed by application/driver into 2D frame*/ 852 853 TIMING_3D_FORMAT_MAX, 854 }; 855 856 #define DC_DSC_QP_SET_SIZE 15 857 #define DC_DSC_RC_BUF_THRESH_SIZE 14 858 struct dc_dsc_rc_params_override { 859 int32_t rc_model_size; 860 int32_t rc_buf_thresh[DC_DSC_RC_BUF_THRESH_SIZE]; 861 int32_t rc_minqp[DC_DSC_QP_SET_SIZE]; 862 int32_t rc_maxqp[DC_DSC_QP_SET_SIZE]; 863 int32_t rc_offset[DC_DSC_QP_SET_SIZE]; 864 865 int32_t rc_tgt_offset_hi; 866 int32_t rc_tgt_offset_lo; 867 int32_t rc_edge_factor; 868 int32_t rc_quant_incr_limit0; 869 int32_t rc_quant_incr_limit1; 870 871 int32_t initial_fullness_offset; 872 int32_t initial_delay; 873 874 int32_t flatness_min_qp; 875 int32_t flatness_max_qp; 876 int32_t flatness_det_thresh; 877 }; 878 879 struct dc_dsc_config { 880 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ 881 uint32_t num_slices_v; /* Number of DSC slices - vertical */ 882 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 883 bool block_pred_enable; /* DSC block prediction enable */ 884 uint32_t linebuf_depth; /* DSC line buffer depth */ 885 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ 886 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ 887 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 888 bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */ 889 bool is_dp; /* indicate if DSC is applied based on DP's capability */ 890 uint32_t mst_pbn; /* pbn of display on dsc mst hub */ 891 const struct dc_dsc_rc_params_override *rc_params_ovrd; /* DM owned memory. If not NULL, apply custom dsc rc params */ 892 }; 893 894 /** 895 * struct dc_crtc_timing - Timing parameters used to configure DCN blocks 896 * 897 * DCN provides multiple signals and parameters that can be used to adjust 898 * timing parameters, this struct aggregate multiple of these values for easy 899 * access. In this struct, fields prefixed with h_* are related to horizontal 900 * timing, and v_* to vertical timing. Keep in mind that when we talk about 901 * vertical timings, the values, in general, are described in the number of 902 * lines; on the other hand, the horizontal values are in pixels. 903 */ 904 struct dc_crtc_timing { 905 /** 906 * @h_total: The total number of pixels from the rising edge of HSync 907 * until the rising edge of the current HSync. 908 */ 909 uint32_t h_total; 910 911 /** 912 * @h_border_left: The black pixels related to the left border 913 */ 914 uint32_t h_border_left; 915 916 /** 917 * @h_addressable: It is the range of pixels displayed horizontally. 918 * For example, if the display resolution is 3840@2160, the horizontal 919 * addressable area is 3840. 920 */ 921 uint32_t h_addressable; 922 923 /** 924 * @h_border_right: The black pixels related to the right border 925 */ 926 uint32_t h_border_right; 927 928 /** 929 * @h_front_porch: Period (in pixels) between HBlank start and the 930 * rising edge of HSync. 931 */ 932 uint32_t h_front_porch; 933 934 /** 935 * @h_sync_width: HSync duration in pixels. 936 */ 937 uint32_t h_sync_width; 938 939 /** 940 * @v_total: It is the total number of lines from the rising edge of 941 * the previous VSync until the rising edge of the current VSync. 942 * 943 * |--------------------------| 944 * +-+ V_TOTAL +-+ 945 * | | | | 946 * VSync ---+ +--------- // -----------+ +--- 947 */ 948 uint32_t v_total; 949 950 /** 951 * @v_border_top: The black border on the top. 952 */ 953 uint32_t v_border_top; 954 955 /** 956 * @v_addressable: It is the range of the scanout at which the 957 * framebuffer is displayed. For example, if the display resolution is 958 * 3840@2160, the addressable area is 2160 lines, or if the resolution 959 * is 1920x1080, the addressable area is 1080 lines. 960 */ 961 uint32_t v_addressable; 962 963 /** 964 * @v_border_bottom: The black border on the bottom. 965 */ 966 uint32_t v_border_bottom; 967 968 /** 969 * @v_front_porch: Period (in lines) between VBlank start and rising 970 * edge of VSync. 971 * +-+ 972 * VSync | | 973 * ----------+ +--------... 974 * +------------------... 975 * VBlank | 976 * --+ 977 * |-------| 978 * v_front_porch 979 */ 980 uint32_t v_front_porch; 981 982 /** 983 * @v_sync_width: VSync signal width in lines. 984 */ 985 uint32_t v_sync_width; 986 987 /** 988 * @pix_clk_100hz: Pipe pixel precision 989 * 990 * This field is used to communicate pixel clocks with 100 Hz accuracy 991 * from dc_crtc_timing to BIOS command table. 992 */ 993 uint32_t pix_clk_100hz; 994 995 uint32_t min_refresh_in_uhz; 996 uint32_t max_refresh_in_uhz; 997 998 uint32_t vic; 999 uint32_t hdmi_vic; 1000 uint32_t rid; 1001 uint32_t fr_index; 1002 uint32_t frl_uncompressed_video_bandwidth_in_kbps; 1003 enum dc_timing_3d_format timing_3d_format; 1004 enum dc_color_depth display_color_depth; 1005 enum dc_pixel_encoding pixel_encoding; 1006 enum dc_aspect_ratio aspect_ratio; 1007 enum scanning_type scan_type; 1008 1009 struct dc_crtc_timing_flags flags; 1010 uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 1011 struct dc_dsc_config dsc_cfg; 1012 1013 /* The number of pixels that HBlank has been expanded by from the original EDID timing. */ 1014 uint32_t expanded_hblank; 1015 }; 1016 1017 enum trigger_delay { 1018 TRIGGER_DELAY_NEXT_PIXEL = 0, 1019 TRIGGER_DELAY_NEXT_LINE, 1020 }; 1021 1022 enum crtc_event { 1023 CRTC_EVENT_VSYNC_RISING = 0, 1024 CRTC_EVENT_VSYNC_FALLING 1025 }; 1026 1027 struct crtc_trigger_info { 1028 bool enabled; 1029 struct dc_stream_state *event_source; 1030 enum crtc_event event; 1031 enum trigger_delay delay; 1032 }; 1033 1034 struct dc_crtc_timing_adjust { 1035 uint32_t v_total_min; 1036 uint32_t v_total_max; 1037 uint32_t v_total_mid; 1038 uint32_t v_total_mid_frame_num; 1039 uint32_t allow_otg_v_count_halt; 1040 uint8_t timing_adjust_pending; 1041 }; 1042 1043 1044 /* Passed on init */ 1045 enum vram_type { 1046 VIDEO_MEMORY_TYPE_GDDR5 = 2, 1047 VIDEO_MEMORY_TYPE_DDR3 = 3, 1048 VIDEO_MEMORY_TYPE_DDR4 = 4, 1049 VIDEO_MEMORY_TYPE_HBM = 5, 1050 VIDEO_MEMORY_TYPE_GDDR6 = 6, 1051 }; 1052 1053 enum dwb_cnv_out_bpc { 1054 DWB_CNV_OUT_BPC_8BPC = 0, 1055 DWB_CNV_OUT_BPC_10BPC = 1, 1056 }; 1057 1058 enum dwb_output_depth { 1059 DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0, 1060 DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1, 1061 }; 1062 1063 enum dwb_capture_rate { 1064 dwb_capture_rate_0 = 0, /* Every frame is captured. */ 1065 dwb_capture_rate_1 = 1, /* Every other frame is captured. */ 1066 dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */ 1067 dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */ 1068 }; 1069 1070 enum dwb_scaler_mode { 1071 dwb_scaler_mode_bypass444 = 0, 1072 dwb_scaler_mode_rgb444 = 1, 1073 dwb_scaler_mode_yuv444 = 2, 1074 dwb_scaler_mode_yuv420 = 3 1075 }; 1076 1077 enum dwb_subsample_position { 1078 DWB_INTERSTITIAL_SUBSAMPLING = 0, 1079 DWB_COSITED_SUBSAMPLING = 1 1080 }; 1081 1082 enum dwb_stereo_eye_select { 1083 DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */ 1084 DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */ 1085 }; 1086 1087 enum dwb_stereo_type { 1088 DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */ 1089 DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ 1090 }; 1091 1092 enum dwb_out_format { 1093 DWB_OUT_FORMAT_32BPP_ARGB = 0, 1094 DWB_OUT_FORMAT_32BPP_RGBA = 1, 1095 DWB_OUT_FORMAT_64BPP_ARGB = 2, 1096 DWB_OUT_FORMAT_64BPP_RGBA = 3 1097 }; 1098 1099 enum dwb_out_denorm { 1100 DWB_OUT_DENORM_10BPC = 0, 1101 DWB_OUT_DENORM_8BPC = 1, 1102 DWB_OUT_DENORM_BYPASS = 2 1103 }; 1104 1105 enum cm_gamut_remap_select { 1106 CM_GAMUT_REMAP_MODE_BYPASS = 0, 1107 CM_GAMUT_REMAP_MODE_RAMA_COEFF, 1108 CM_GAMUT_REMAP_MODE_RAMB_COEFF, 1109 CM_GAMUT_REMAP_MODE_RESERVED 1110 }; 1111 1112 enum cm_gamut_coef_format { 1113 CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0, 1114 CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 1115 }; 1116 1117 enum mpcc_gamut_remap_mode_select { 1118 MPCC_GAMUT_REMAP_MODE_SELECT_0 = 0, 1119 MPCC_GAMUT_REMAP_MODE_SELECT_1, 1120 MPCC_GAMUT_REMAP_MODE_SELECT_2 1121 }; 1122 1123 enum mpcc_gamut_remap_id { 1124 MPCC_OGAM_GAMUT_REMAP, 1125 MPCC_MCM_FIRST_GAMUT_REMAP, 1126 MPCC_MCM_SECOND_GAMUT_REMAP, 1127 MPCC_RMCM_GAMUT_REMAP, 1128 }; 1129 1130 enum cursor_matrix_mode { 1131 CUR_MATRIX_BYPASS = 0, 1132 CUR_MATRIX_SET_A, 1133 CUR_MATRIX_SET_B 1134 }; 1135 1136 struct mcif_warmup_params { 1137 union large_integer start_address; 1138 unsigned int address_increment; 1139 unsigned int region_size; 1140 unsigned int p_vmid; 1141 }; 1142 1143 #define MCIF_BUF_COUNT 4 1144 1145 struct mcif_buf_params { 1146 unsigned long long luma_address[MCIF_BUF_COUNT]; 1147 unsigned long long chroma_address[MCIF_BUF_COUNT]; 1148 unsigned int luma_pitch; 1149 unsigned int chroma_pitch; 1150 unsigned int warmup_pitch; 1151 unsigned int swlock; 1152 unsigned int p_vmid; 1153 uint8_t tmz_id; 1154 }; 1155 1156 1157 #define MAX_TG_COLOR_VALUE 0x3FF 1158 struct tg_color { 1159 /* Maximum 10 bits color value */ 1160 uint16_t color_r_cr; 1161 uint16_t color_g_y; 1162 uint16_t color_b_cb; 1163 }; 1164 1165 enum symclk_state { 1166 SYMCLK_OFF_TX_OFF, 1167 SYMCLK_ON_TX_ON, 1168 SYMCLK_ON_TX_OFF, 1169 }; 1170 1171 struct phy_state { 1172 struct { 1173 uint8_t otg : 1; 1174 uint8_t reserved : 7; 1175 } symclk_ref_cnts; 1176 enum symclk_state symclk_state; 1177 }; 1178 1179 enum cm_hist_tap_point { 1180 CM_HIST_TAP_POINT_1, 1181 CM_HIST_TAP_POINT_2, 1182 CM_HIST_TAP_POINT_3, 1183 CM_HIST_TAP_POINT_4, 1184 }; 1185 1186 enum cm_hist_src { 1187 CM_HIST_SRC1, 1188 CM_HIST_SRC2, 1189 CM_HIST_SRC3, 1190 }; 1191 1192 enum cm_hist_format { 1193 CM_HIST_FORMAT_FIXED_POINT, 1194 CM_HIST_FORMAT_FP16_POS, 1195 CM_HIST_FORMAT_FP16_POS_AND_NEG, 1196 }; 1197 1198 enum cm_hist_read_channel_mask { 1199 CM_HIST_READ_DISABLED, 1200 CM_HIST_READ_CH1, 1201 CM_HIST_READ_CH2, 1202 CM_HIST_READ_CH1_CH2, 1203 CM_HIST_READ_CH3, 1204 CM_HIST_READ_CH1_CH3, 1205 CM_HIST_READ_CH2_CH3, 1206 CM_HIST_READ_ALL, 1207 }; 1208 1209 enum cm_hist_src1_mode { 1210 CM_HIST_SRC1_MODE_R_OR_CR, 1211 CM_HIST_SRC1_MODE_MAX_RGB, 1212 }; 1213 1214 enum cm_hist_src2_mode { 1215 CM_HIST_SRC2_MODE_G_OR_Y, 1216 CM_HIST_SRC2_MODE_RGB_TO_Y, 1217 }; 1218 1219 enum cm_hist_src3_mode { 1220 CM_HIST_SRC3_MODE_B_OR_CB, 1221 CM_HIST_SRC3_MODE_MIN_RGB, 1222 }; 1223 1224 struct cm_hist_control { 1225 enum cm_hist_tap_point tap_point; 1226 uint32_t channels_enabled; 1227 enum cm_hist_src1_mode src_1_select; 1228 enum cm_hist_src2_mode src_2_select; 1229 enum cm_hist_src3_mode src_3_select; 1230 enum cm_hist_src ch1_src; 1231 enum cm_hist_src ch2_src; 1232 enum cm_hist_src ch3_src; 1233 enum cm_hist_format format; 1234 enum cm_hist_read_channel_mask read_channel_mask; 1235 }; 1236 1237 struct cm_hist { 1238 uint32_t ch1[256]; 1239 uint32_t ch2[256]; 1240 uint32_t ch3[256]; 1241 }; 1242 #endif /* DC_HW_TYPES_H */ 1243 1244