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Searched refs:MDIO_MMD_VEND2 (Results 1 – 25 of 35) sorted by relevance

12

/linux/drivers/net/pcs/
H A Dpcs-xpcs-nxp.c74 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL2, in nxp_sja1105_sgmii_pma_config()
89 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0, in nxp_sja1110_pma_config()
94 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1, in nxp_sja1110_pma_config()
100 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER1_0, in nxp_sja1110_pma_config()
107 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_0, val); in nxp_sja1110_pma_config()
113 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_1, val); in nxp_sja1110_pma_config()
122 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_TRIM, val); in nxp_sja1110_pma_config()
127 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DATAPATH_1, 0); in nxp_sja1110_pma_config()
134 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0, in nxp_sja1110_pma_config()
139 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL1, in nxp_sja1110_pma_config()
[all …]
H A Dpcs-xpcs.c291 dev = MDIO_MMD_VEND2; in xpcs_soft_reset()
390 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK, in xpcs_link_up_usxgmii()
774 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); in xpcs_config_aneg_c37_sgmii()
779 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_sgmii()
800 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); in xpcs_config_aneg_c37_sgmii()
815 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); in xpcs_config_aneg_c37_sgmii()
820 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_sgmii()
842 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); in xpcs_config_aneg_c37_1000basex()
847 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, in xpcs_config_aneg_c37_1000basex()
862 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); in xpcs_config_aneg_c37_1000basex()
[all …]
H A Dpcs-xpcs-plat.c173 return xpcs_mmio_read_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg); in xpcs_mmio_read_c22()
175 return xpcs_mmio_read_reg_direct(pxpcs, MDIO_MMD_VEND2, reg); in xpcs_mmio_read_c22()
186 return xpcs_mmio_write_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg, val); in xpcs_mmio_write_c22()
188 return xpcs_mmio_write_reg_direct(pxpcs, MDIO_MMD_VEND2, reg, val); in xpcs_mmio_write_c22()
H A Dpcs-lynx.c67 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); in lynx_pcs_get_state_usxgmii()
76 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); in lynx_pcs_get_state_usxgmii()
167 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, in lynx_pcs_config_usxgmii()
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_ethtool.c1236 { ETH_SR_MII_CTRL, MDIO_MMD_VEND2, 0x0000}, in lan743x_sgmii_regs()
1237 { ETH_SR_MII_STS, MDIO_MMD_VEND2, 0x0001}, in lan743x_sgmii_regs()
1238 { ETH_SR_MII_DEV_ID1, MDIO_MMD_VEND2, 0x0002}, in lan743x_sgmii_regs()
1239 { ETH_SR_MII_DEV_ID2, MDIO_MMD_VEND2, 0x0003}, in lan743x_sgmii_regs()
1240 { ETH_SR_MII_AN_ADV, MDIO_MMD_VEND2, 0x0004}, in lan743x_sgmii_regs()
1241 { ETH_SR_MII_LP_BABL, MDIO_MMD_VEND2, 0x0005}, in lan743x_sgmii_regs()
1242 { ETH_SR_MII_EXPN, MDIO_MMD_VEND2, 0x0006}, in lan743x_sgmii_regs()
1243 { ETH_SR_MII_EXT_STS, MDIO_MMD_VEND2, 0x000F}, in lan743x_sgmii_regs()
1244 { ETH_SR_MII_TIME_SYNC_ABL, MDIO_MMD_VEND2, 0x0708}, in lan743x_sgmii_regs()
1245 { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x0709}, in lan743x_sgmii_regs()
[all …]
H A Dlan743x_main.c1040 mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1056 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1061 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1066 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1099 mii_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR); in lan743x_serdes_clock_and_aneg_update()
1103 an_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, VR_MII_AN_CTRL); in lan743x_serdes_clock_and_aneg_update()
1107 dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1123 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
1134 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, in lan743x_serdes_clock_and_aneg_update()
1139 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_serdes_clock_and_aneg_update()
[all …]
/linux/drivers/net/phy/
H A Ddp83td510.c302 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT); in dp83td510_get_mse_snapshot()
324 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2, in dp83td510_led_brightness_set()
376 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1, in dp83td510_led_hw_control_set()
382 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2, in dp83td510_led_hw_control_set()
391 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1); in dp83td510_led_hw_control_get()
447 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2, in dp83td510_led_polarity_set()
477 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_1); in dp83td510_update_stats()
483 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_2); in dp83td510_update_stats()
490 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_3); in dp83td510_update_stats()
496 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_4); in dp83td510_update_stats()
[all …]
H A Ddp83tg720.c217 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LINK_QUAL_3); in dp83tg720_update_stats()
235 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_1); in dp83tg720_update_stats()
241 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_2); in dp83tg720_update_stats()
248 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_3); in dp83tg720_update_stats()
254 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_4); in dp83tg720_update_stats()
260 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_5); in dp83tg720_update_stats()
267 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_6); in dp83tg720_update_stats()
336 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83tg720_cable_test_start()
341 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2, in dp83tg720_cable_test_start()
346 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3, in dp83tg720_cable_test_start()
[all …]
H A Ddp83822.c229 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1, in dp83822_config_wol()
231 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2, in dp83822_config_wol()
233 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3, in dp83822_config_wol()
236 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
244 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
247 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
250 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
264 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
267 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
296 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); in dp83822_get_wol()
[all …]
H A Dmicrochip_t1s.c151 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb_indirect_read()
156 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, in lan865x_revb_indirect_read()
161 return phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_DATA); in lan865x_revb_indirect_read()
195 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in lan865x_read_cfg_params()
212 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i], in lan865x_write_cfg_params()
276 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
311 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_check_reset_complete()
317 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); in lan867x_check_reset_complete()
353 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revc_config_init()
[all …]
H A Dintel-xway.c251 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_init_leds()
255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_init_leds()
268 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_init_leds()
269 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_init_leds()
270 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_init_leds()
271 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_init_leds()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_init_leds()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_init_leds()
387 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index), 0); in xway_gphy_led_brightness_set()
391 return phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index), 0); in xway_gphy_led_brightness_set()
[all …]
H A Dphy-c45.c1292 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1301 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1307 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1314 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1320 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); in genphy_c45_plca_get_cfg()
1353 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1368 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1385 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1393 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1408 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
[all …]
H A Dmarvell10g.c195 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); in mv3310_hwmon_read_temp_reg()
252 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
259 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, in mv3310_hwmon_config()
306 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_down()
315 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
329 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
647 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); in mv3310_get_mactype()
659 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
665 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
1322 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); in mv3110_get_wol()
[all …]
H A Dmarvell-88x2222.c78 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
83 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
199 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
H A Dadin1100.c148 int rc = phy_read_mmd(phydev, MDIO_MMD_VEND2, in adin_phy_ack_intr()
168 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in adin_config_intr()
177 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2, in adin_phy_handle_interrupt()
H A Dair_en8811h.c695 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_on_set()
722 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_blink_set()
852 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), in air_led_hw_control_set()
858 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), in air_led_hw_control_set()
880 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), in air_led_init()
895 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, in air_leds_init()
900 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, in air_leds_init()
907 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, in air_leds_init()
914 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, in air_leds_init()
H A Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
H A Dmxl-gpy.c753 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
760 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
767 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
780 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
796 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
/linux/drivers/net/phy/realtek/
H A Drealtek_hwmon.c33 raw = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSRR) & 0x3ff; in rtl822x_hwmon_read()
38 raw = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSSR) >> 6; in rtl822x_hwmon_read()
68 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSALRM, 3); in rtl822x_hwmon_init()
H A Drealtek_main.c1167 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); in rtlgen_read_vend2()
1172 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, in rtlgen_write_vend2()
1180 if (devnum == MDIO_MMD_VEND2) in rtlgen_read_mmd()
1199 if (devnum == MDIO_MMD_VEND2) in rtlgen_write_mmd()
1261 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) in rtl822xb_read_mmd()
1301 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) in rtl822xb_write_mmd()
1472 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); in rtl822x_get_features()
1493 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, in rtl822x_config_aneg()
1540 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); in rtl822x_read_status()
1587 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, in rtl822x_c45_config_aneg()
[all …]
/linux/drivers/net/phy/mediatek/
H A Dmtk-phy-lib.c127 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mtk_phy_led_hw_ctrl_get()
133 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, in mtk_phy_led_hw_ctrl_get()
255 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_led_hw_ctrl_set()
263 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_led_hw_ctrl_set()
300 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_hw_led_on_set()
325 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_hw_led_blink_set()
H A Dmtk-2p5ge.c351 phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, in mt798x_2p5ge_phy_probe()
353 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, in mt798x_2p5ge_phy_probe()
356 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, in mt798x_2p5ge_phy_probe()
359 phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, in mt798x_2p5ge_phy_probe()
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c42 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_clear_interrupts()
44 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_clear_interrupts()
51 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_disable_interrupts()
53 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_disable_interrupts()
68 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_enable_interrupts()
70 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_enable_interrupts()
259 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
268 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
270 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL); in xgbe_an37_set()
272 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL, reg); in xgbe_an37_set()
[all …]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read_c45()
23 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1105_pcs_mdio_read_c45()
25 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1105_pcs_mdio_read_c45()
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write_c45()
67 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1110_pcs_mdio_read_c45()
69 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1110_pcs_mdio_read_c45()
/linux/include/uapi/linux/
H A Dmdio.h29 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ macro
180 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)

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