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Searched refs:MDIO_MMD_AN (Results 1 – 25 of 40) sorted by relevance

12

/linux/drivers/net/phy/
H A Dphy-c45.c241 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, in genphy_c45_baset1_an_config_aneg()
250 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, in genphy_c45_baset1_an_config_aneg()
288 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in genphy_c45_an_config_aneg()
299 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_an_config_aneg()
328 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
348 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
372 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_check_and_restart_aneg()
406 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
427 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
480 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_baset1_read_lpa()
[all …]
H A Dbcm84881.c113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in bcm84881_config_aneg()
129 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in bcm84881_aneg_done()
133 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR); in bcm84881_aneg_done()
146 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in bcm84881_read_status()
155 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in bcm84881_read_status()
159 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR); in bcm84881_read_status()
185 val = phy_read_mmd(phydev, MDIO_MMD_AN, in bcm84881_read_status()
H A Dmarvell-88q2xxx.c141 { MDIO_MMD_AN, 0x8032, 0x0064 },
142 { MDIO_MMD_AN, 0x8031, 0x0a01 },
143 { MDIO_MMD_AN, 0x8031, 0x0c01 },
149 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
167 { MDIO_MMD_AN, 0x8032, 0x2020 },
168 { MDIO_MMD_AN, 0x8031, 0xa28 },
169 { MDIO_MMD_AN, 0x8031, 0xc28 },
179 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
186 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
209 { MDIO_MMD_AN, 0x8032, 0x2020 },
[all …]
H A Dadin1100.c84 ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS); in adin_read_status()
117 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
120 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
126 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
135 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
H A Dbcm-phy-lib.c377 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL); in bcm_phy_set_eee()
386 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); in bcm_phy_set_eee()
389 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV); in bcm_phy_set_eee()
405 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); in bcm_phy_set_eee()
512 { "phy_lpi_count", MDIO_MMD_AN, BRCM_CL45VEN_EEE_LPI_CNT, 0, 16 },
H A Dmarvell10g.c612 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
618 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN, in mv2110_set_mactype()
626 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
937 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, in mv3310_config_aneg()
1024 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in mv3310_read_status_copper()
1081 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); in mv3310_read_status_copper()
H A Dteranetics.c62 reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in teranetics_read_status()
H A Das21xxx.c643 *bmcr = phy_read_mmd(phydev, MDIO_MMD_AN, in as21xxx_read_link()
656 status = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in as21xxx_read_link()
672 lpagb = phy_read_mmd(phydev, MDIO_MMD_AN, in as21xxx_read_c22_lpa()
678 int adv = phy_read_mmd(phydev, MDIO_MMD_AN, in as21xxx_read_c22_lpa()
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c75 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); in xgbe_an73_clear_interrupts()
80 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in xgbe_an73_disable_interrupts()
85 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK); in xgbe_an73_enable_interrupts()
302 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_an73_set()
311 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_an73_set()
388 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_an73_tx_training()
389 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_an73_tx_training()
427 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); in xgbe_an73_tx_xnp()
428 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); in xgbe_an73_tx_xnp()
429 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); in xgbe_an73_tx_xnp()
[all …]
H A Dxgbe-phy-v1.c134 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_an_outcome()
135 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_an_outcome()
158 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an_outcome()
159 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an_outcome()
182 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an_outcome()
183 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an_outcome()
H A Dxgbe-phy-v2.c1584 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an73_redrv_outcome()
1585 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an73_redrv_outcome()
1647 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an73_redrv_outcome()
1648 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an73_redrv_outcome()
1665 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_an73_outcome()
1666 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_an73_outcome()
1689 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an73_outcome()
1690 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an73_outcome()
1705 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an73_outcome()
1706 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an73_outcome()
/linux/drivers/net/phy/qcom/
H A Dqcom-phy-lib.c651 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_hw_control_enable()
660 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca808x_led_reg_hw_control_status()
668 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_brightness_set()
682 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, in qca808x_led_reg_blink_set()
689 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_blink_set()
710 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_CTRL, in qcom_phy_counter_config()
723 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_15_0); in qcom_phy_update_stats()
729 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_31_16); in qcom_phy_update_stats()
737 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_ERR_PKT); in qcom_phy_update_stats()
744 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_TX_PKT_15_0); in qcom_phy_update_stats()
[all …]
H A Dqca808x.c108 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, in qca808x_phy_fast_retrain_config()
164 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); in qca808x_is_1g_only()
205 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, in qca808x_config_init()
262 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in qca808x_read_status()
405 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in qca808x_config_aneg()
497 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_hw_control_set()
528 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca808x_led_hw_control_get()
558 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_hw_control_reset()
624 return phy_modify_mmd(phydev, MDIO_MMD_AN, in qca808x_led_polarity_set()
H A Dqca807x.c234 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, mask, in qca807x_led_hw_control_set()
266 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca807x_led_hw_control_get()
285 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca807x_led_hw_control_get()
327 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, mask); in qca807x_led_hw_control_reset()
376 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg); in qca807x_gpio_get()
389 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg); in qca807x_gpio_set()
397 return phy_write_mmd(priv->phy, MDIO_MMD_AN, reg, val); in qca807x_gpio_set()
665 MDIO_MMD_AN, in qca807x_configure_serdes()
761 control_dac = phy_read_mmd(phydev, MDIO_MMD_AN, in qca807x_config_init()
770 return phy_write_mmd(phydev, MDIO_MMD_AN, in qca807x_config_init()
/linux/drivers/vfio/platform/reset/
H A Dvfio_platform_amdxgbe.c87 value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1); in vfio_platform_amdxgbe_reset()
89 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value); in vfio_platform_amdxgbe_reset()
92 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in vfio_platform_amdxgbe_reset()
95 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INT, 0); in vfio_platform_amdxgbe_reset()
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c134 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_enable()
147 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_restart()
162 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in aq100x_advertise()
173 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, AQ_1G_CTRL, in aq100x_advertise()
188 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in aq100x_advertise()
223 err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v); in aq100x_get_link_status()
/linux/drivers/net/phy/aquantia/
H A Daquantia_main.c194 return phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_PROV, in aqr_set_mdix()
240 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, in aqr_config_aneg()
260 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); in aqr_config_intr()
265 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, in aqr_config_intr()
283 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); in aqr_config_intr()
295 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, in aqr_handle_interrupt()
315 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); in aqr_read_status()
331 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_STATUS1); in aqr_read_status()
402 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv); in aqr105_setup_forced()
405 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, vend); in aqr105_setup_forced()
[all …]
/linux/drivers/net/ethernet/sfc/falcon/
H A Dmdio_10g.c55 if (mmd != MDIO_MMD_AN) { in ef4_mdio_check_mmd()
285 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); in ef4_mdio_an_reconfigure()
291 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); in ef4_mdio_an_reconfigure()
293 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); in ef4_mdio_an_reconfigure()
307 ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA)); in ef4_mdio_get_pause()
H A Dtenxpress.c263 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); in sfx7101_check_bad_lp()
446 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); in tenxpress_get_link_ksettings()
449 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in tenxpress_get_link_ksettings()
473 ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in sfx7101_set_npage_adv()
/linux/drivers/net/
H A Dmdio.c142 mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1, in mdio45_nway_restart()
153 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, addr); in mdio45_get_an()
258 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, in mdio45_ethtool_ksettings_get_npage()
276 MDIO_MMD_AN, MDIO_STAT1); in mdio45_ethtool_ksettings_get_npage()
402 devad = MDIO_MMD_AN; in mdio_mii_ioctl()
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1118 MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1142 MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1160 MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1165 MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1341 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1349 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
[all …]
H A Dixgbe_x550.c1933 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_check_link_t_X550em()
2390 MDIO_MMD_AN, &reg); in ixgbe_get_lasi_ext_t_x550em()
2397 MDIO_MMD_AN, &reg); in ixgbe_get_lasi_ext_t_x550em()
2440 MDIO_MMD_AN, &reg); in ixgbe_enable_lasi_ext_t_x550em()
2448 MDIO_MMD_AN, reg); in ixgbe_enable_lasi_ext_t_x550em()
2615 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_ext_phy_t_x550em_get_link()
2620 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_ext_phy_t_x550em_get_link()
2667 MDIO_MMD_AN, in ixgbe_setup_internal_phy_t_x550em()
2831 MDIO_MMD_AN, in ixgbe_get_lcd_t_x550em()
3067 MDIO_MMD_AN, in ixgbe_enter_lplu_t_x550em()
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs.c425 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); in _xpcs_config_aneg_c73()
438 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); in _xpcs_config_aneg_c73()
449 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); in _xpcs_config_aneg_c73()
461 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, in xpcs_config_aneg_c73()
473 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); in xpcs_aneg_done_c73()
504 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); in xpcs_read_lpa_c73()
1027 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); in xpcs_get_state_c73()
/linux/include/uapi/linux/
H A Dmdio.h25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ macro
177 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c1184 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) in rtlgen_read_mmd()
1186 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) in rtlgen_read_mmd()
1201 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) in rtlgen_write_mmd()
1218 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) in rtl822x_read_mmd()
1220 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) in rtl822x_read_mmd()
1234 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) in rtl822x_write_mmd()

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