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Searched refs:MDIO_CTRL1 (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/net/ethernet/sfc/falcon/
H A Dmdio_10g.c39 ef4_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET); in ef4_mdio_reset_mmd()
43 ctrl = ef4_mdio_read(port, mmd, MDIO_CTRL1); in ef4_mdio_reset_mmd()
86 stat = ef4_mdio_read(efx, mmd, MDIO_CTRL1); in ef4_mdio_wait_reset_mmds()
188 MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK, in ef4_mdio_phy_reconfigure()
191 MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK, in ef4_mdio_phy_reconfigure()
194 MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK, in ef4_mdio_phy_reconfigure()
207 ef4_mdio_set_flag(efx, mmd, MDIO_CTRL1, in ef4_mdio_set_mmd_lpower()
291 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); in ef4_mdio_an_reconfigure()
293 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); in ef4_mdio_an_reconfigure()
H A Dqt202x_phy.c204 ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, in qt2025c_bug17190_workaround()
207 ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, in qt2025c_bug17190_workaround()
/linux/drivers/vfio/platform/reset/
H A Dvfio_platform_amdxgbe.c71 pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1); in vfio_platform_amdxgbe_reset()
73 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1, pcs_value); in vfio_platform_amdxgbe_reset()
79 MDIO_CTRL1); in vfio_platform_amdxgbe_reset()
87 value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1); in vfio_platform_amdxgbe_reset()
89 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value); in vfio_platform_amdxgbe_reset()
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c123 MDIO_MMD_PMAPMD, MDIO_CTRL1, in aq100x_power_down()
134 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_enable()
147 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_restart()
197 MDIO_MMD_PMAPMD, MDIO_CTRL1, in aq100x_set_loopback()
292 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
328 err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v); in t3_aq100x_phy_prep()
332 err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1, in t3_aq100x_phy_prep()
H A Dael1002.c148 MDIO_MMD_PMAPMD, MDIO_CTRL1, in ael1002_power_down()
H A Dt3_hw.c358 err = t3_mdio_change_bits(phy, mmd, MDIO_CTRL1, MDIO_CTRL1_LPOWER, in t3_phy_reset()
364 err = t3_mdio_read(phy, mmd, MDIO_CTRL1, &ctl); in t3_phy_reset()
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v1.c213 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_pcs_power_cycle()
216 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_pcs_power_cycle()
221 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_pcs_power_cycle()
269 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_kr_mode()
272 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_kr_mode()
312 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_kx_2500_mode()
315 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_kx_2500_mode()
355 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_kx_1000_mode()
358 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_kx_1000_mode()
548 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_reset()
[all …]
H A Dxgbe-mdio.c259 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
268 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
302 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_an73_set()
311 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_an73_set()
902 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_an37_init()
904 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_an37_init()
1460 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, in xgbe_dump_phy_registers()
1461 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); in xgbe_dump_phy_registers()
1473 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, in xgbe_dump_phy_registers()
1474 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); in xgbe_dump_phy_registers()
H A Dxgbe-platform.c389 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_platform_suspend()
391 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); in xgbe_platform_suspend()
407 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); in xgbe_platform_resume()
H A Dxgbe-pci.c364 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_pci_suspend()
366 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); in xgbe_pci_suspend()
380 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); in xgbe_pci_resume()
/linux/drivers/net/phy/
H A Dmarvell-88q2xxx.c150 { MDIO_MMD_PMAPMD, MDIO_CTRL1,
154 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0 },
155 { MDIO_MMD_PCS, MDIO_CTRL1, 0x0 },
181 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
187 { MDIO_MMD_PMAPMD, MDIO_CTRL1, 0x0840 },
605 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in mv88q2xxx_suspend()
621 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in mv88q2xxx_resume()
H A Dphy-c45.c58 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
72 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
119 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
169 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
323 u16 reg = MDIO_CTRL1; in genphy_c45_an_disable_aneg()
343 u16 reg = MDIO_CTRL1; in genphy_c45_restart_aneg()
364 u16 reg = MDIO_CTRL1; in genphy_c45_check_and_restart_aneg()
427 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
607 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_read_pma()
1237 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, in genphy_c45_loopback()
H A Dbcm84881.c27 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in bcm84881_wait_init()
146 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in bcm84881_read_status()
H A Dmarvell10g.c337 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, in mv3310_reset()
343 unit + MDIO_CTRL1, val, in mv3310_reset()
H A Dbcm7xxx.c606 case MDIO_CTRL1: in bcm7xxx_28nm_ephy_regnum_to_shd()
H A Dadin.c209 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
H A Dphy.c1849 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, in phy_eee_rx_clock_stop()
/linux/drivers/net/pcs/
H A Dpcs-xpcs-wx.c186 xpcs_modify(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, in txgbe_xpcs_switch_mode()
191 xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, 0); in txgbe_xpcs_switch_mode()
192 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL1, 0); in txgbe_xpcs_switch_mode()
H A Dpcs-xpcs.c386 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); in xpcs_link_up_usxgmii()
395 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, in xpcs_link_up_usxgmii()
461 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, in xpcs_config_aneg_c73()
575 pcs_ctrl1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL1); in xpcs_c45_read_pcs_speed()
/linux/drivers/net/
H A Dmdio.c142 mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1, in mdio45_nway_restart()
259 MDIO_CTRL1); in mdio45_ethtool_ksettings_get_npage()
312 MDIO_CTRL1); in mdio45_ethtool_ksettings_get_npage()
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c421 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_reset_phy_generic()
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, in ixgbe_reset_phy_generic()
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_generic()
1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_generic()
1389 hw->phy.ops.read_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_tnx()
1394 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_tnx()
1416 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); in ixgbe_reset_phy_nl()
1419 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, in ixgbe_reset_phy_nl()
1423 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, in ixgbe_reset_phy_nl()
2844 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg); in ixgbe_set_copper_phy_power()
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dserdes.h45 #define MV88E6390_10G_CTRL1 (0x1000 + MDIO_CTRL1)
/linux/include/uapi/linux/
H A Dmdio.h32 #define MDIO_CTRL1 MII_BMCR macro
/linux/drivers/net/phy/aquantia/
H A Daquantia_main.c413 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, in aqr105_setup_forced()
1052 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr_gen1_suspend()
1064 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr_gen1_resume()
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c1637 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in rtl822x_c45_soft_reset()
1643 MDIO_CTRL1, val, in rtl822x_c45_soft_reset()