Searched refs:MCR_RTS (Results 1 – 7 of 7) sorted by relevance
56 #define MCR_RTS 0x02 macro299 priv->line_control |= MCR_RTS; in spcp8x5_set_termios()413 priv->line_control |= MCR_RTS; in spcp8x5_tiocmset()417 priv->line_control &= ~MCR_RTS; in spcp8x5_tiocmset()444 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in spcp8x5_tiocmget()
52 #define MCR_RTS 0x02 /* Assert RTS */ macro939 mos7840_port->shadowMCR &= ~MCR_RTS; in mos7840_throttle()969 mos7840_port->shadowMCR |= MCR_RTS; in mos7840_unthrottle()992 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in mos7840_tiocmget()1015 mcr &= ~MCR_RTS; in mos7840_tiocmset()1022 mcr |= MCR_RTS; in mos7840_tiocmset()1275 mos7840_port->shadowMCR |= (MCR_DTR | MCR_RTS); in mos7840_change_port_settings()
123 #define MCR_RTS 0x02 // Assert RTS macro
1523 status = ti_do_config(port, UMPC_SET_CLR_RTS, mcr & MCR_RTS); in restore_mcr()1912 edge_port->shadow_mcr = MCR_RTS | MCR_DTR; in edge_open()2187 edge_port->shadow_mcr &= ~MCR_RTS; in stop_read()2205 edge_port->shadow_mcr |= MCR_RTS; in restart_read()2376 mcr |= MCR_RTS; in edge_tiocmset()2383 mcr &= ~MCR_RTS; in edge_tiocmset()2410 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ in edge_tiocmget()
1397 edge_port->shadowMCR &= ~MCR_RTS; in edge_throttle()1434 edge_port->shadowMCR |= MCR_RTS; in edge_unthrottle()1503 mcr |= MCR_RTS; in edge_tiocmset()1510 mcr &= ~MCR_RTS; in edge_tiocmset()1534 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ in edge_tiocmget()2472 edge_port->shadowMCR |= (MCR_DTR | MCR_RTS); in change_port_settings()
132 #define MCR_RTS 0x0200 /* Request to Send */ macro
182 #define MCR_RTS 0x02 /* RTS output */ macro225 #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */305 outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase)); in fpga_reset()320 bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR; in fpga_write()