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Searched refs:MAX_PIPES (Results 1 – 25 of 68) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h245 struct mem_input *mis[MAX_PIPES];
246 struct hubp *hubps[MAX_PIPES];
247 struct input_pixel_processor *ipps[MAX_PIPES];
248 struct transform *transforms[MAX_PIPES];
249 struct dpp *dpps[MAX_PIPES];
250 struct output_pixel_processor *opps[MAX_PIPES];
251 struct timing_generator *timing_generators[MAX_PIPES];
252 struct stream_encoder *stream_enc[MAX_PIPES * 2];
257 struct dce_aux *engines[MAX_PIPES];
258 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
[all …]
H A Dresource.h391 struct pipe_ctx *opp_heads[MAX_PIPES]);
401 struct pipe_ctx *dpp_pipes[MAX_PIPES]);
410 struct pipe_ctx *dpp_pipes[MAX_PIPES]);
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_enc_cfg.c101 for (i = 0; i < MAX_PIPES; i++) { in remove_link_enc_assignment()
237 for (i = 0; i < MAX_PIPES; i++) { in get_link_enc_used_by_link()
253 for (i = 0; i < MAX_PIPES; i++) { in clear_enc_assignments()
303 for (i = 0; i < MAX_PIPES; i++) in link_enc_cfg_link_encs_assign()
399 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
405 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
418 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
469 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_stream_using_link_enc()
508 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_link_enc_used_by_link()
532 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_next_avail_link_enc()
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H A Ddc_stream.c266 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes()
413 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position()
715 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter()
745 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp()
783 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos()
810 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done()
816 if (i == MAX_PIPES) in dc_stream_dmdata_status_done()
840 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata()
846 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
882 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_pipe_ctx()
H A Ddc.c431 for (i = 0; i < MAX_PIPES; i++) { in set_long_vtotal()
495 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_adjust_vmin_vmax()
537 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_last_used_drr_vtotal()
603 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_crc_window()
610 if (i == MAX_PIPES) in dc_stream_forward_crc_window()
669 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_multiple_crc_window()
676 if (i == MAX_PIPES) in dc_stream_forward_multiple_crc_window()
794 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crc()
800 if (i == MAX_PIPES) in dc_stream_get_crc()
820 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dyn_expansion()
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H A Ddc_resource.c107 if (current_snapshot->line_count >= MAX_PIPES) in capture_pipe_topology_data()
737 for (i = 0; i < MAX_PIPES; i++) { in resource_find_used_clk_src_for_sharing()
1454 struct pipe_ctx *opp_heads[MAX_PIPES]; in resource_build_test_pattern_params()
1746 for (i = 0; i < MAX_PIPES; i++) { in resource_build_scaling_params_for_context()
2000 for (i = 0; i < MAX_PIPES; i++) { in resource_get_otg_master_for_stream()
2010 struct pipe_ctx *opp_heads[MAX_PIPES]) in resource_get_opp_heads_for_otg_master() argument
2026 ASSERT(i < MAX_PIPES); in resource_get_opp_heads_for_otg_master()
2035 struct pipe_ctx *dpp_pipes[MAX_PIPES]) in resource_get_dpp_pipes_for_opp_head() argument
2045 ASSERT(i < MAX_PIPES); in resource_get_dpp_pipes_for_opp_head()
2054 struct pipe_ctx *dpp_pipes[MAX_PIPES]) in resource_get_dpp_pipes_for_plane() argument
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h869 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
1183 uint32_t dml21_force_pstate_method_values[MAX_PIPES];
1200 uint32_t acpi_transition_bitmasks[MAX_PIPES];
1821 …bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first…
1882 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];
1883 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];
1884 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];
1885 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];
1886 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];
1887 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.h138 type OTG_ADD_PIXEL[MAX_PIPES];\
139 type OTG_DROP_PIXEL[MAX_PIPES];\
175 type DTBCLK_DTO_ENABLE[MAX_PIPES];\
176 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
177 type PIPE_DTO_SRC_SEL[MAX_PIPES];\
178 type DTBCLK_DTO_DIV[MAX_PIPES];\
367 type DP_DTO_ENABLE[MAX_PIPES];
394 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \
401 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \
402 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_internal_types.h131 struct dml2_pipe_combine_factor odm_factors[MAX_PIPES];
132 struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES][MAX_PIPES];
H A Ddml2_dc_resource_mgmt.c47 unsigned int odm_slice_end_x[MAX_PIPES];
48 struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];
349 unsigned int preferred_pipe_candidates[MAX_PIPES] = {0}; in find_more_pipes_for_stream()
350 unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0}; in find_more_pipes_for_stream()
415 unsigned int preferred_pipe_candidates[MAX_PIPES] = {0}; in find_more_free_pipes()
416 unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0}; in find_more_free_pipes()
612 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_stream()
650 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_plane()
911 struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0}; in get_source_mpc_factor()
927 struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES]) in populate_mpc_factors_for_stream() argument
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dhw_shared.h45 #define MAX_PIPES 6 macro
46 #define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
96 struct pipe_topology_line pipe_log_lines[MAX_PIPES];
H A Dopp.h231 int dpp[MAX_PIPES];
232 int mpcc[MAX_PIPES];
240 bool mpcc_disconnect_pending[MAX_PIPES];
H A Dpg_cntl.h35 bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
H A Ddccg.h196 int pipe_dppclk_khz[MAX_PIPES];
198 bool dpp_clock_gated[MAX_PIPES];
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.c141 if (dsc_inst < MAX_PIPES) in pg_cntl35_dsc_pg_control()
232 if (hubp_dpp_inst < MAX_PIPES) { in pg_cntl35_hubp_dpp_pg_control()
353 if (mpcc_inst < MAX_PIPES) in pg_cntl35_mpcc_pg_control()
363 if (opp_inst < MAX_PIPES) in pg_cntl35_opp_pg_control()
373 if (optc_inst < MAX_PIPES) in pg_cntl35_optc_pg_control()
561 memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool)); in pg_cntl35_create()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
H A Ddcn401_optc.c59 bool first_preferred_memory_for_opp[MAX_PIPES] = {0}; in decide_odm_mem_bit_map()
60 bool second_preferred_memory_for_opp[MAX_PIPES] = {0}; in decide_odm_mem_bit_map()
83 for (i = 0; i < MAX_PIPES; i++) { in decide_odm_mem_bit_map()
94 for (i = 0; i < MAX_PIPES; i++) { in decide_odm_mem_bit_map()
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_panel_replay.c59 for (int i = 0; i < MAX_PIPES; i++) { in dp_pr_set_static_screen_param()
127 for (i = 0; i < MAX_PIPES; i++) { in dp_setup_panel_replay()
218 for (unsigned int i = 0; i < MAX_PIPES; i++) { in dp_pr_get_panel_inst()
285 for (unsigned int i = 0; i < MAX_PIPES; i++) { in dp_pr_copy_settings()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c514 struct pipe_ctx *pipe_ctx_list[MAX_PIPES]; in dcn32_auto_dpm_test_log()
517 for (int i = 0; i < MAX_PIPES; i++) { in dcn32_auto_dpm_test_log()
564 uint32_t pix_clk_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
565 int p_state_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
566 int disp_src_width_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
567 int disp_src_height_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
568 uint64_t disp_src_refresh_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
569 bool is_scaled_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h228 uint32_t PHASE[MAX_PIPES];
229 uint32_t MODULO[MAX_PIPES];
230 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.h42 struct pipe_ctx *pipes[MAX_PIPES]);
H A Dlink_resource.c40 for (i = 0; i < MAX_PIPES; i++) { in link_get_cur_link_res()
H A Dlink_validation.c376 for (i = 0; i < MAX_PIPES; i++) { in get_dp_tunnel_settings()
399 for (uint8_t i = 0; (i < MAX_PIPES && i < new_ctx->stream_count); i++) { in link_validate_dp_tunnel_bandwidth()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c998 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp()
999 int initial_slack[MAX_PIPES]; in increase_dsc_bpp()
1101 bool tried[MAX_PIPES]; in try_disable_dsc()
1102 int kbps_increase[MAX_PIPES]; in try_disable_dsc()
1194 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link()
1357 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; in is_dsc_need_re_compute()
1373 for (i = 0; i < MAX_PIPES; i++) in is_dsc_need_re_compute()
1488 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
1558 bool computed_streams[MAX_PIPES]; in pre_compute_mst_dsc_configs_for_state()
H A Damdgpu_dm_debugfs.c1300 for (i = 0; i < MAX_PIPES; i++) { in odm_combine_segments_show()
1576 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_read()
1678 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_write()
1762 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_read()
1862 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_write()
1946 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_read()
2046 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_write()
2126 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_read()
2223 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_write()
2301 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_width_read()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c418 struct pipe_ctx *pipe_ctx_list[MAX_PIPES]; in dcn401_auto_dpm_test_log()
421 for (int i = 0; i < MAX_PIPES; i++) { in dcn401_auto_dpm_test_log()
466 uint32_t pix_clk_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
467 int p_state_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
468 int disp_src_width_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
469 int disp_src_height_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
470 uint64_t disp_src_refresh_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
471 bool is_scaled_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()

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