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Searched refs:L3_PWM_TIMER_INIT_VAL_MASK (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/xe/ !
H A Dxe_tuning.c35 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
36 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
40 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
41 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
117 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
118 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
136 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
137 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
/linux/drivers/gpu/drm/xe/regs/ !
H A Dxe_gt_regs.h432 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) macro
/linux/drivers/gpu/drm/i915/gt/ !
H A Dintel_workarounds.c707 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, in dg2_ctx_gt_tuning_init()
708 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); in dg2_ctx_gt_tuning_init()
H A Dintel_gt_regs.h1008 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) macro