Searched refs:KVM_REG_RISCV_CONFIG (Results 1 – 4 of 4) sorted by relevance
256 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); in config_id_to_str()258 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG); in config_id_to_str()765 case KVM_REG_RISCV_CONFIG: in print_reg()817 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa),818 …KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_…819 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid),820 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid),821 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid),822 …KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_…823 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode),[all …]
282 KVM_REG_RISCV_CONFIG); in kvm_riscv_vcpu_get_reg_config()336 KVM_REG_RISCV_CONFIG); in kvm_riscv_vcpu_set_reg_config()870 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CONFIG | i; in copy_config_reg_indices()1254 case KVM_REG_RISCV_CONFIG: in kvm_riscv_vcpu_set_reg()1287 case KVM_REG_RISCV_CONFIG: in kvm_riscv_vcpu_get_reg()
40 #define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, 0, \
252 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) macro