1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC
4 *
5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
6 * Copyright (C) 2022 StarFive Technology Co., Ltd.
7 */
8
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/io.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/seq_file.h>
20 #include <linux/spinlock.h>
21
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
28
29 #include "../core.h"
30 #include "../pinctrl-utils.h"
31 #include "../pinmux.h"
32 #include "../pinconf.h"
33 #include "pinctrl-starfive-jh7110.h"
34
35 /* pad control bits */
36 #define JH7110_PADCFG_POS BIT(7)
37 #define JH7110_PADCFG_SMT BIT(6)
38 #define JH7110_PADCFG_SLEW BIT(5)
39 #define JH7110_PADCFG_PD BIT(4)
40 #define JH7110_PADCFG_PU BIT(3)
41 #define JH7110_PADCFG_BIAS (JH7110_PADCFG_PD | JH7110_PADCFG_PU)
42 #define JH7110_PADCFG_DS_MASK GENMASK(2, 1)
43 #define JH7110_PADCFG_DS_2MA (0U << 1)
44 #define JH7110_PADCFG_DS_4MA BIT(1)
45 #define JH7110_PADCFG_DS_8MA (2U << 1)
46 #define JH7110_PADCFG_DS_12MA (3U << 1)
47 #define JH7110_PADCFG_IE BIT(0)
48
49 /*
50 * The packed pinmux values from the device tree look like this:
51 *
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
53 * | din | dout | doen | function | pin |
54 */
jh7110_pinmux_din(u32 v)55 static unsigned int jh7110_pinmux_din(u32 v)
56 {
57 return (v & GENMASK(31, 24)) >> 24;
58 }
59
jh7110_pinmux_dout(u32 v)60 static u32 jh7110_pinmux_dout(u32 v)
61 {
62 return (v & GENMASK(23, 16)) >> 16;
63 }
64
jh7110_pinmux_doen(u32 v)65 static u32 jh7110_pinmux_doen(u32 v)
66 {
67 return (v & GENMASK(15, 10)) >> 10;
68 }
69
jh7110_pinmux_function(u32 v)70 static u32 jh7110_pinmux_function(u32 v)
71 {
72 return (v & GENMASK(9, 8)) >> 8;
73 }
74
jh7110_pinmux_pin(u32 v)75 static unsigned int jh7110_pinmux_pin(u32 v)
76 {
77 return v & GENMASK(7, 0);
78 }
79
jh7110_from_irq_data(struct irq_data * d)80 static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d)
81 {
82 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
83
84 return container_of(gc, struct jh7110_pinctrl, gc);
85 }
86
jh7110_from_irq_desc(struct irq_desc * desc)87 struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc)
88 {
89 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
90
91 return container_of(gc, struct jh7110_pinctrl, gc);
92 }
93 EXPORT_SYMBOL_GPL(jh7110_from_irq_desc);
94
95 #ifdef CONFIG_DEBUG_FS
jh7110_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)96 static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev,
97 struct seq_file *s, unsigned int pin)
98 {
99 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
100 const struct jh7110_pinctrl_soc_info *info = sfp->info;
101
102 seq_printf(s, "%s", dev_name(pctldev->dev));
103
104 if (pin < sfp->gc.ngpio) {
105 unsigned int offset = 4 * (pin / 4);
106 unsigned int shift = 8 * (pin % 4);
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
109 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);
110
111 dout = (dout >> shift) & info->dout_mask;
112 doen = (doen >> shift) & info->doen_mask;
113 gpi = ((gpi >> shift) - 2) & info->gpi_mask;
114
115 seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi);
116 }
117 }
118 #else
119 #define jh7110_pin_dbg_show NULL
120 #endif
121
jh7110_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** maps,unsigned int * num_maps)122 static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
123 struct device_node *np,
124 struct pinctrl_map **maps,
125 unsigned int *num_maps)
126 {
127 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
128 struct device *dev = sfp->gc.parent;
129 struct device_node *child;
130 struct pinctrl_map *map;
131 const char **pgnames;
132 const char *grpname;
133 int ngroups;
134 int nmaps;
135 int ret;
136
137 ngroups = 0;
138 for_each_available_child_of_node(np, child)
139 ngroups += 1;
140 nmaps = 2 * ngroups;
141
142 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
143 if (!pgnames)
144 return -ENOMEM;
145
146 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
147 if (!map)
148 return -ENOMEM;
149
150 nmaps = 0;
151 ngroups = 0;
152 mutex_lock(&sfp->mutex);
153 for_each_available_child_of_node_scoped(np, child) {
154 int npins = of_property_count_u32_elems(child, "pinmux");
155 int *pins;
156 u32 *pinmux;
157 int i;
158
159 if (npins < 1) {
160 dev_err(dev,
161 "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
162 np, child);
163 ret = -EINVAL;
164 goto free_map;
165 }
166
167 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
168 if (!grpname) {
169 ret = -ENOMEM;
170 goto free_map;
171 }
172
173 pgnames[ngroups++] = grpname;
174
175 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
176 if (!pins) {
177 ret = -ENOMEM;
178 goto free_map;
179 }
180
181 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
182 if (!pinmux) {
183 ret = -ENOMEM;
184 goto free_map;
185 }
186
187 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
188 if (ret)
189 goto free_map;
190
191 for (i = 0; i < npins; i++)
192 pins[i] = jh7110_pinmux_pin(pinmux[i]);
193
194 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
195 map[nmaps].data.mux.function = np->name;
196 map[nmaps].data.mux.group = grpname;
197 nmaps += 1;
198
199 ret = pinctrl_generic_add_group(pctldev, grpname,
200 pins, npins, pinmux);
201 if (ret < 0) {
202 dev_err(dev, "error adding group %s: %d\n", grpname, ret);
203 goto free_map;
204 }
205
206 ret = pinconf_generic_parse_dt_config(child, pctldev,
207 &map[nmaps].data.configs.configs,
208 &map[nmaps].data.configs.num_configs);
209 if (ret) {
210 dev_err(dev, "error parsing pin config of group %s: %d\n",
211 grpname, ret);
212 goto free_map;
213 }
214
215 /* don't create a map if there are no pinconf settings */
216 if (map[nmaps].data.configs.num_configs == 0)
217 continue;
218
219 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
220 map[nmaps].data.configs.group_or_pin = grpname;
221 nmaps += 1;
222 }
223
224 ret = pinmux_generic_add_function(pctldev, np->name,
225 pgnames, ngroups, NULL);
226 if (ret < 0) {
227 dev_err(dev, "error adding function %s: %d\n", np->name, ret);
228 goto free_map;
229 }
230 mutex_unlock(&sfp->mutex);
231
232 *maps = map;
233 *num_maps = nmaps;
234 return 0;
235
236 free_map:
237 pinctrl_utils_free_map(pctldev, map, nmaps);
238 mutex_unlock(&sfp->mutex);
239 return ret;
240 }
241
242 static const struct pinctrl_ops jh7110_pinctrl_ops = {
243 .get_groups_count = pinctrl_generic_get_group_count,
244 .get_group_name = pinctrl_generic_get_group_name,
245 .get_group_pins = pinctrl_generic_get_group_pins,
246 .pin_dbg_show = jh7110_pin_dbg_show,
247 .dt_node_to_map = jh7110_dt_node_to_map,
248 .dt_free_map = pinctrl_utils_free_map,
249 };
250
jh7110_set_gpiomux(struct jh7110_pinctrl * sfp,unsigned int pin,unsigned int din,u32 dout,u32 doen)251 void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
252 unsigned int din, u32 dout, u32 doen)
253 {
254 const struct jh7110_pinctrl_soc_info *info = sfp->info;
255
256 unsigned int offset = 4 * (pin / 4);
257 unsigned int shift = 8 * (pin % 4);
258 u32 dout_mask = info->dout_mask << shift;
259 u32 done_mask = info->doen_mask << shift;
260 u32 ival, imask;
261 void __iomem *reg_dout;
262 void __iomem *reg_doen;
263 void __iomem *reg_din;
264 unsigned long flags;
265
266 reg_dout = sfp->base + info->dout_reg_base + offset;
267 reg_doen = sfp->base + info->doen_reg_base + offset;
268 dout <<= shift;
269 doen <<= shift;
270 if (din != GPI_NONE) {
271 unsigned int ioffset = 4 * (din / 4);
272 unsigned int ishift = 8 * (din % 4);
273
274 reg_din = sfp->base + info->gpi_reg_base + ioffset;
275 ival = (pin + 2) << ishift;
276 imask = info->gpi_mask << ishift;
277 } else {
278 reg_din = NULL;
279 }
280
281 raw_spin_lock_irqsave(&sfp->lock, flags);
282 dout |= readl_relaxed(reg_dout) & ~dout_mask;
283 writel_relaxed(dout, reg_dout);
284 doen |= readl_relaxed(reg_doen) & ~done_mask;
285 writel_relaxed(doen, reg_doen);
286 if (reg_din) {
287 ival |= readl_relaxed(reg_din) & ~imask;
288 writel_relaxed(ival, reg_din);
289 }
290 raw_spin_unlock_irqrestore(&sfp->lock, flags);
291 }
292 EXPORT_SYMBOL_GPL(jh7110_set_gpiomux);
293
jh7110_set_mux(struct pinctrl_dev * pctldev,unsigned int fsel,unsigned int gsel)294 static int jh7110_set_mux(struct pinctrl_dev *pctldev,
295 unsigned int fsel, unsigned int gsel)
296 {
297 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
298 const struct jh7110_pinctrl_soc_info *info = sfp->info;
299 const struct group_desc *group;
300 const u32 *pinmux;
301 unsigned int i;
302
303 group = pinctrl_generic_get_group(pctldev, gsel);
304 if (!group)
305 return -EINVAL;
306
307 pinmux = group->data;
308 for (i = 0; i < group->grp.npins; i++) {
309 u32 v = pinmux[i];
310
311 if (info->jh7110_set_one_pin_mux)
312 info->jh7110_set_one_pin_mux(sfp,
313 jh7110_pinmux_pin(v),
314 jh7110_pinmux_din(v),
315 jh7110_pinmux_dout(v),
316 jh7110_pinmux_doen(v),
317 jh7110_pinmux_function(v));
318 }
319
320 return 0;
321 }
322
323 static const struct pinmux_ops jh7110_pinmux_ops = {
324 .get_functions_count = pinmux_generic_get_function_count,
325 .get_function_name = pinmux_generic_get_function_name,
326 .get_function_groups = pinmux_generic_get_function_groups,
327 .set_mux = jh7110_set_mux,
328 .strict = true,
329 };
330
331 static const u8 jh7110_drive_strength_mA[4] = { 2, 4, 8, 12 };
332
jh7110_padcfg_ds_to_mA(u32 padcfg)333 static u32 jh7110_padcfg_ds_to_mA(u32 padcfg)
334 {
335 return jh7110_drive_strength_mA[(padcfg >> 1) & 3U];
336 }
337
jh7110_padcfg_ds_from_mA(u32 v)338 static u32 jh7110_padcfg_ds_from_mA(u32 v)
339 {
340 int i;
341
342 for (i = 0; i < 3; i++) {
343 if (v <= jh7110_drive_strength_mA[i])
344 break;
345 }
346 return i << 1;
347 }
348
jh7110_padcfg_rmw(struct jh7110_pinctrl * sfp,unsigned int pin,u32 mask,u32 value)349 static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp,
350 unsigned int pin, u32 mask, u32 value)
351 {
352 const struct jh7110_pinctrl_soc_info *info = sfp->info;
353 void __iomem *reg;
354 unsigned long flags;
355 int padcfg_base;
356
357 if (!info->jh7110_get_padcfg_base)
358 return;
359
360 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
361 if (padcfg_base < 0)
362 return;
363
364 reg = sfp->base + padcfg_base + 4 * pin;
365 value &= mask;
366
367 raw_spin_lock_irqsave(&sfp->lock, flags);
368 value |= readl_relaxed(reg) & ~mask;
369 writel_relaxed(value, reg);
370 raw_spin_unlock_irqrestore(&sfp->lock, flags);
371 }
372
jh7110_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)373 static int jh7110_pinconf_get(struct pinctrl_dev *pctldev,
374 unsigned int pin, unsigned long *config)
375 {
376 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
377 const struct jh7110_pinctrl_soc_info *info = sfp->info;
378 int param = pinconf_to_config_param(*config);
379 u32 padcfg, arg;
380 bool enabled;
381 int padcfg_base;
382
383 if (!info->jh7110_get_padcfg_base)
384 return 0;
385
386 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
387 if (padcfg_base < 0)
388 return 0;
389
390 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
391 switch (param) {
392 case PIN_CONFIG_BIAS_DISABLE:
393 enabled = !(padcfg & JH7110_PADCFG_BIAS);
394 arg = 0;
395 break;
396 case PIN_CONFIG_BIAS_PULL_DOWN:
397 enabled = padcfg & JH7110_PADCFG_PD;
398 arg = 1;
399 break;
400 case PIN_CONFIG_BIAS_PULL_UP:
401 enabled = padcfg & JH7110_PADCFG_PU;
402 arg = 1;
403 break;
404 case PIN_CONFIG_DRIVE_STRENGTH:
405 enabled = true;
406 arg = jh7110_padcfg_ds_to_mA(padcfg);
407 break;
408 case PIN_CONFIG_INPUT_ENABLE:
409 enabled = padcfg & JH7110_PADCFG_IE;
410 arg = enabled;
411 break;
412 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
413 enabled = padcfg & JH7110_PADCFG_SMT;
414 arg = enabled;
415 break;
416 case PIN_CONFIG_SLEW_RATE:
417 enabled = true;
418 arg = !!(padcfg & JH7110_PADCFG_SLEW);
419 break;
420 default:
421 return -ENOTSUPP;
422 }
423
424 *config = pinconf_to_config_packed(param, arg);
425 return enabled ? 0 : -EINVAL;
426 }
427
jh7110_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int gsel,unsigned long * config)428 static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev,
429 unsigned int gsel,
430 unsigned long *config)
431 {
432 const struct group_desc *group;
433
434 group = pinctrl_generic_get_group(pctldev, gsel);
435 if (!group)
436 return -EINVAL;
437
438 return jh7110_pinconf_get(pctldev, group->grp.pins[0], config);
439 }
440
jh7110_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int gsel,unsigned long * configs,unsigned int num_configs)441 static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,
442 unsigned int gsel,
443 unsigned long *configs,
444 unsigned int num_configs)
445 {
446 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
447 const struct group_desc *group;
448 u16 mask, value;
449 int i;
450
451 group = pinctrl_generic_get_group(pctldev, gsel);
452 if (!group)
453 return -EINVAL;
454
455 mask = 0;
456 value = 0;
457 for (i = 0; i < num_configs; i++) {
458 int param = pinconf_to_config_param(configs[i]);
459 u32 arg = pinconf_to_config_argument(configs[i]);
460
461 switch (param) {
462 case PIN_CONFIG_BIAS_DISABLE:
463 mask |= JH7110_PADCFG_BIAS;
464 value &= ~JH7110_PADCFG_BIAS;
465 break;
466 case PIN_CONFIG_BIAS_PULL_DOWN:
467 if (arg == 0)
468 return -ENOTSUPP;
469 mask |= JH7110_PADCFG_BIAS;
470 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PD;
471 break;
472 case PIN_CONFIG_BIAS_PULL_UP:
473 if (arg == 0)
474 return -ENOTSUPP;
475 mask |= JH7110_PADCFG_BIAS;
476 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PU;
477 break;
478 case PIN_CONFIG_DRIVE_STRENGTH:
479 mask |= JH7110_PADCFG_DS_MASK;
480 value = (value & ~JH7110_PADCFG_DS_MASK) |
481 jh7110_padcfg_ds_from_mA(arg);
482 break;
483 case PIN_CONFIG_INPUT_ENABLE:
484 mask |= JH7110_PADCFG_IE;
485 if (arg)
486 value |= JH7110_PADCFG_IE;
487 else
488 value &= ~JH7110_PADCFG_IE;
489 break;
490 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
491 mask |= JH7110_PADCFG_SMT;
492 if (arg)
493 value |= JH7110_PADCFG_SMT;
494 else
495 value &= ~JH7110_PADCFG_SMT;
496 break;
497 case PIN_CONFIG_SLEW_RATE:
498 mask |= JH7110_PADCFG_SLEW;
499 if (arg)
500 value |= JH7110_PADCFG_SLEW;
501 else
502 value &= ~JH7110_PADCFG_SLEW;
503 break;
504 default:
505 return -ENOTSUPP;
506 }
507 }
508
509 for (i = 0; i < group->grp.npins; i++)
510 jh7110_padcfg_rmw(sfp, group->grp.pins[i], mask, value);
511
512 return 0;
513 }
514
515 #ifdef CONFIG_DEBUG_FS
jh7110_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)516 static void jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev,
517 struct seq_file *s, unsigned int pin)
518 {
519 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
520 const struct jh7110_pinctrl_soc_info *info = sfp->info;
521 u32 value;
522 int padcfg_base;
523
524 if (!info->jh7110_get_padcfg_base)
525 return;
526
527 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
528 if (padcfg_base < 0)
529 return;
530
531 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
532 seq_printf(s, " (0x%02x)", value);
533 }
534 #else
535 #define jh7110_pinconf_dbg_show NULL
536 #endif
537
538 static const struct pinconf_ops jh7110_pinconf_ops = {
539 .pin_config_get = jh7110_pinconf_get,
540 .pin_config_group_get = jh7110_pinconf_group_get,
541 .pin_config_group_set = jh7110_pinconf_group_set,
542 .pin_config_dbg_show = jh7110_pinconf_dbg_show,
543 .is_generic = true,
544 };
545
jh7110_gpio_get_direction(struct gpio_chip * gc,unsigned int gpio)546 static int jh7110_gpio_get_direction(struct gpio_chip *gc,
547 unsigned int gpio)
548 {
549 struct jh7110_pinctrl *sfp = container_of(gc,
550 struct jh7110_pinctrl, gc);
551 const struct jh7110_pinctrl_soc_info *info = sfp->info;
552 unsigned int offset = 4 * (gpio / 4);
553 unsigned int shift = 8 * (gpio % 4);
554 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
555
556 doen = (doen >> shift) & info->doen_mask;
557
558 return doen == GPOEN_ENABLE ?
559 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
560 }
561
jh7110_gpio_direction_input(struct gpio_chip * gc,unsigned int gpio)562 static int jh7110_gpio_direction_input(struct gpio_chip *gc,
563 unsigned int gpio)
564 {
565 struct jh7110_pinctrl *sfp = container_of(gc,
566 struct jh7110_pinctrl, gc);
567 const struct jh7110_pinctrl_soc_info *info = sfp->info;
568
569 /* enable input and schmitt trigger */
570 jh7110_padcfg_rmw(sfp, gpio,
571 JH7110_PADCFG_IE | JH7110_PADCFG_SMT,
572 JH7110_PADCFG_IE | JH7110_PADCFG_SMT);
573
574 if (info->jh7110_set_one_pin_mux)
575 info->jh7110_set_one_pin_mux(sfp, gpio,
576 GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
577
578 return 0;
579 }
580
jh7110_gpio_direction_output(struct gpio_chip * gc,unsigned int gpio,int value)581 static int jh7110_gpio_direction_output(struct gpio_chip *gc,
582 unsigned int gpio, int value)
583 {
584 struct jh7110_pinctrl *sfp = container_of(gc,
585 struct jh7110_pinctrl, gc);
586 const struct jh7110_pinctrl_soc_info *info = sfp->info;
587
588 if (info->jh7110_set_one_pin_mux)
589 info->jh7110_set_one_pin_mux(sfp, gpio,
590 GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW,
591 GPOEN_ENABLE, 0);
592
593 /* disable input, schmitt trigger and bias */
594 jh7110_padcfg_rmw(sfp, gpio,
595 JH7110_PADCFG_IE | JH7110_PADCFG_SMT |
596 JH7110_PADCFG_BIAS, 0);
597 return 0;
598 }
599
jh7110_gpio_get(struct gpio_chip * gc,unsigned int gpio)600 static int jh7110_gpio_get(struct gpio_chip *gc, unsigned int gpio)
601 {
602 struct jh7110_pinctrl *sfp = container_of(gc,
603 struct jh7110_pinctrl, gc);
604 const struct jh7110_pinctrl_soc_info *info = sfp->info;
605 void __iomem *reg = sfp->base + info->gpioin_reg_base
606 + 4 * (gpio / 32);
607
608 return !!(readl_relaxed(reg) & BIT(gpio % 32));
609 }
610
jh7110_gpio_set(struct gpio_chip * gc,unsigned int gpio,int value)611 static int jh7110_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
612 {
613 struct jh7110_pinctrl *sfp = container_of(gc,
614 struct jh7110_pinctrl, gc);
615 const struct jh7110_pinctrl_soc_info *info = sfp->info;
616 unsigned int offset = 4 * (gpio / 4);
617 unsigned int shift = 8 * (gpio % 4);
618 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;
619 u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift;
620 u32 mask = info->dout_mask << shift;
621 unsigned long flags;
622
623 raw_spin_lock_irqsave(&sfp->lock, flags);
624 dout |= readl_relaxed(reg_dout) & ~mask;
625 writel_relaxed(dout, reg_dout);
626 raw_spin_unlock_irqrestore(&sfp->lock, flags);
627
628 return 0;
629 }
630
jh7110_gpio_set_config(struct gpio_chip * gc,unsigned int gpio,unsigned long config)631 static int jh7110_gpio_set_config(struct gpio_chip *gc,
632 unsigned int gpio, unsigned long config)
633 {
634 struct jh7110_pinctrl *sfp = container_of(gc,
635 struct jh7110_pinctrl, gc);
636 u32 arg = pinconf_to_config_argument(config);
637 u32 value;
638 u32 mask;
639
640 switch (pinconf_to_config_param(config)) {
641 case PIN_CONFIG_BIAS_DISABLE:
642 mask = JH7110_PADCFG_BIAS;
643 value = 0;
644 break;
645 case PIN_CONFIG_BIAS_PULL_DOWN:
646 if (arg == 0)
647 return -ENOTSUPP;
648 mask = JH7110_PADCFG_BIAS;
649 value = JH7110_PADCFG_PD;
650 break;
651 case PIN_CONFIG_BIAS_PULL_UP:
652 if (arg == 0)
653 return -ENOTSUPP;
654 mask = JH7110_PADCFG_BIAS;
655 value = JH7110_PADCFG_PU;
656 break;
657 case PIN_CONFIG_DRIVE_PUSH_PULL:
658 return 0;
659 case PIN_CONFIG_INPUT_ENABLE:
660 mask = JH7110_PADCFG_IE;
661 value = arg ? JH7110_PADCFG_IE : 0;
662 break;
663 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
664 mask = JH7110_PADCFG_SMT;
665 value = arg ? JH7110_PADCFG_SMT : 0;
666 break;
667 default:
668 return -ENOTSUPP;
669 }
670
671 jh7110_padcfg_rmw(sfp, gpio, mask, value);
672 return 0;
673 }
674
jh7110_gpio_add_pin_ranges(struct gpio_chip * gc)675 static int jh7110_gpio_add_pin_ranges(struct gpio_chip *gc)
676 {
677 struct jh7110_pinctrl *sfp = container_of(gc,
678 struct jh7110_pinctrl, gc);
679
680 sfp->gpios.name = sfp->gc.label;
681 sfp->gpios.base = sfp->gc.base;
682 sfp->gpios.pin_base = 0;
683 sfp->gpios.npins = sfp->gc.ngpio;
684 sfp->gpios.gc = &sfp->gc;
685 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
686 return 0;
687 }
688
jh7110_irq_ack(struct irq_data * d)689 static void jh7110_irq_ack(struct irq_data *d)
690 {
691 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
692 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
693 irq_hw_number_t gpio = irqd_to_hwirq(d);
694 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
695 + 4 * (gpio / 32);
696 u32 mask = BIT(gpio % 32);
697 unsigned long flags;
698 u32 value;
699
700 raw_spin_lock_irqsave(&sfp->lock, flags);
701 value = readl_relaxed(ic) & ~mask;
702 writel_relaxed(value, ic);
703 writel_relaxed(value | mask, ic);
704 raw_spin_unlock_irqrestore(&sfp->lock, flags);
705 }
706
jh7110_irq_mask(struct irq_data * d)707 static void jh7110_irq_mask(struct irq_data *d)
708 {
709 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
710 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
711 irq_hw_number_t gpio = irqd_to_hwirq(d);
712 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
713 + 4 * (gpio / 32);
714 u32 mask = BIT(gpio % 32);
715 unsigned long flags;
716 u32 value;
717
718 raw_spin_lock_irqsave(&sfp->lock, flags);
719 value = readl_relaxed(ie) & ~mask;
720 writel_relaxed(value, ie);
721 raw_spin_unlock_irqrestore(&sfp->lock, flags);
722
723 gpiochip_disable_irq(&sfp->gc, d->hwirq);
724 }
725
jh7110_irq_mask_ack(struct irq_data * d)726 static void jh7110_irq_mask_ack(struct irq_data *d)
727 {
728 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
729 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
730 irq_hw_number_t gpio = irqd_to_hwirq(d);
731 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
732 + 4 * (gpio / 32);
733 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
734 + 4 * (gpio / 32);
735 u32 mask = BIT(gpio % 32);
736 unsigned long flags;
737 u32 value;
738
739 raw_spin_lock_irqsave(&sfp->lock, flags);
740 value = readl_relaxed(ie) & ~mask;
741 writel_relaxed(value, ie);
742
743 value = readl_relaxed(ic) & ~mask;
744 writel_relaxed(value, ic);
745 writel_relaxed(value | mask, ic);
746 raw_spin_unlock_irqrestore(&sfp->lock, flags);
747 }
748
jh7110_irq_unmask(struct irq_data * d)749 static void jh7110_irq_unmask(struct irq_data *d)
750 {
751 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
752 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
753 irq_hw_number_t gpio = irqd_to_hwirq(d);
754 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
755 + 4 * (gpio / 32);
756 u32 mask = BIT(gpio % 32);
757 unsigned long flags;
758 u32 value;
759
760 gpiochip_enable_irq(&sfp->gc, d->hwirq);
761
762 raw_spin_lock_irqsave(&sfp->lock, flags);
763 value = readl_relaxed(ie) | mask;
764 writel_relaxed(value, ie);
765 raw_spin_unlock_irqrestore(&sfp->lock, flags);
766 }
767
jh7110_irq_set_type(struct irq_data * d,unsigned int trigger)768 static int jh7110_irq_set_type(struct irq_data *d, unsigned int trigger)
769 {
770 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
771 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
772 irq_hw_number_t gpio = irqd_to_hwirq(d);
773 void __iomem *base = sfp->base + 4 * (gpio / 32);
774 u32 mask = BIT(gpio % 32);
775 u32 irq_type, edge_both, polarity;
776 unsigned long flags;
777
778 switch (trigger) {
779 case IRQ_TYPE_EDGE_RISING:
780 irq_type = mask; /* 1: edge triggered */
781 edge_both = 0; /* 0: single edge */
782 polarity = mask; /* 1: rising edge */
783 break;
784 case IRQ_TYPE_EDGE_FALLING:
785 irq_type = mask; /* 1: edge triggered */
786 edge_both = 0; /* 0: single edge */
787 polarity = 0; /* 0: falling edge */
788 break;
789 case IRQ_TYPE_EDGE_BOTH:
790 irq_type = mask; /* 1: edge triggered */
791 edge_both = mask; /* 1: both edges */
792 polarity = 0; /* 0: ignored */
793 break;
794 case IRQ_TYPE_LEVEL_HIGH:
795 irq_type = 0; /* 0: level triggered */
796 edge_both = 0; /* 0: ignored */
797 polarity = 0; /* 0: high level */
798 break;
799 case IRQ_TYPE_LEVEL_LOW:
800 irq_type = 0; /* 0: level triggered */
801 edge_both = 0; /* 0: ignored */
802 polarity = mask; /* 1: low level */
803 break;
804 default:
805 return -EINVAL;
806 }
807
808 if (trigger & IRQ_TYPE_EDGE_BOTH)
809 irq_set_handler_locked(d, handle_edge_irq);
810 else
811 irq_set_handler_locked(d, handle_level_irq);
812
813 raw_spin_lock_irqsave(&sfp->lock, flags);
814 irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask;
815 writel_relaxed(irq_type, base + irq_reg->is_reg_base);
816
817 edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask;
818 writel_relaxed(edge_both, base + irq_reg->ibe_reg_base);
819
820 polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask;
821 writel_relaxed(polarity, base + irq_reg->iev_reg_base);
822 raw_spin_unlock_irqrestore(&sfp->lock, flags);
823 return 0;
824 }
825
826 static struct irq_chip jh7110_irq_chip = {
827 .irq_ack = jh7110_irq_ack,
828 .irq_mask = jh7110_irq_mask,
829 .irq_mask_ack = jh7110_irq_mask_ack,
830 .irq_unmask = jh7110_irq_unmask,
831 .irq_set_type = jh7110_irq_set_type,
832 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
833 GPIOCHIP_IRQ_RESOURCE_HELPERS,
834 };
835
jh7110_disable_clock(void * data)836 static void jh7110_disable_clock(void *data)
837 {
838 clk_disable_unprepare(data);
839 }
840
jh7110_pinctrl_probe(struct platform_device * pdev)841 int jh7110_pinctrl_probe(struct platform_device *pdev)
842 {
843 struct device *dev = &pdev->dev;
844 const struct jh7110_pinctrl_soc_info *info;
845 struct jh7110_pinctrl *sfp;
846 struct pinctrl_desc *jh7110_pinctrl_desc;
847 struct reset_control *rst;
848 struct clk *clk;
849 int ret;
850
851 info = of_device_get_match_data(&pdev->dev);
852 if (!info)
853 return -ENODEV;
854
855 if (!info->pins || !info->npins) {
856 dev_err(dev, "wrong pinctrl info\n");
857 return -EINVAL;
858 }
859
860 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
861 if (!sfp)
862 return -ENOMEM;
863
864 #if IS_ENABLED(CONFIG_PM_SLEEP)
865 sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs,
866 sizeof(*sfp->saved_regs), GFP_KERNEL);
867 if (!sfp->saved_regs)
868 return -ENOMEM;
869 #endif
870
871 sfp->base = devm_platform_ioremap_resource(pdev, 0);
872 if (IS_ERR(sfp->base))
873 return PTR_ERR(sfp->base);
874
875 clk = devm_clk_get_optional(dev, NULL);
876 if (IS_ERR(clk))
877 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
878
879 rst = devm_reset_control_get_exclusive(dev, NULL);
880 if (IS_ERR(rst))
881 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
882
883 /*
884 * we don't want to assert reset and risk undoing pin muxing for the
885 * early boot serial console, but let's make sure the reset line is
886 * deasserted in case someone runs a really minimal bootloader.
887 */
888 ret = reset_control_deassert(rst);
889 if (ret)
890 return dev_err_probe(dev, ret, "could not deassert reset\n");
891
892 if (clk) {
893 ret = clk_prepare_enable(clk);
894 if (ret)
895 return dev_err_probe(dev, ret, "could not enable clock\n");
896
897 ret = devm_add_action_or_reset(dev, jh7110_disable_clock, clk);
898 if (ret)
899 return ret;
900 }
901
902 jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev,
903 sizeof(*jh7110_pinctrl_desc),
904 GFP_KERNEL);
905 if (!jh7110_pinctrl_desc)
906 return -ENOMEM;
907
908 jh7110_pinctrl_desc->name = dev_name(dev);
909 jh7110_pinctrl_desc->pins = info->pins;
910 jh7110_pinctrl_desc->npins = info->npins;
911 jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops;
912 jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops;
913 jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops;
914 jh7110_pinctrl_desc->owner = THIS_MODULE;
915
916 sfp->info = info;
917 sfp->dev = dev;
918 platform_set_drvdata(pdev, sfp);
919 sfp->gc.parent = dev;
920 raw_spin_lock_init(&sfp->lock);
921 mutex_init(&sfp->mutex);
922
923 ret = devm_pinctrl_register_and_init(dev,
924 jh7110_pinctrl_desc,
925 sfp, &sfp->pctl);
926 if (ret)
927 return dev_err_probe(dev, ret,
928 "could not register pinctrl driver\n");
929
930 sfp->gc.label = dev_name(dev);
931 sfp->gc.owner = THIS_MODULE;
932 sfp->gc.request = pinctrl_gpio_request;
933 sfp->gc.free = pinctrl_gpio_free;
934 sfp->gc.get_direction = jh7110_gpio_get_direction;
935 sfp->gc.direction_input = jh7110_gpio_direction_input;
936 sfp->gc.direction_output = jh7110_gpio_direction_output;
937 sfp->gc.get = jh7110_gpio_get;
938 sfp->gc.set = jh7110_gpio_set;
939 sfp->gc.set_config = jh7110_gpio_set_config;
940 sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
941 sfp->gc.base = info->gc_base;
942 sfp->gc.ngpio = info->ngpios;
943
944 jh7110_irq_chip.name = sfp->gc.label;
945 gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip);
946 sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler;
947 sfp->gc.irq.num_parents = 1;
948 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
949 sizeof(*sfp->gc.irq.parents),
950 GFP_KERNEL);
951 if (!sfp->gc.irq.parents)
952 return -ENOMEM;
953 sfp->gc.irq.default_type = IRQ_TYPE_NONE;
954 sfp->gc.irq.handler = handle_bad_irq;
955 sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw;
956
957 ret = platform_get_irq(pdev, 0);
958 if (ret < 0)
959 return ret;
960 sfp->gc.irq.parents[0] = ret;
961
962 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
963 if (ret)
964 return dev_err_probe(dev, ret, "could not register gpiochip\n");
965
966 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);
967
968 return pinctrl_enable(sfp->pctl);
969 }
970 EXPORT_SYMBOL_GPL(jh7110_pinctrl_probe);
971
jh7110_pinctrl_suspend(struct device * dev)972 static int jh7110_pinctrl_suspend(struct device *dev)
973 {
974 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
975 unsigned long flags;
976 unsigned int i;
977
978 raw_spin_lock_irqsave(&sfp->lock, flags);
979 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
980 sfp->saved_regs[i] = readl_relaxed(sfp->base + 4 * i);
981
982 raw_spin_unlock_irqrestore(&sfp->lock, flags);
983 return 0;
984 }
985
jh7110_pinctrl_resume(struct device * dev)986 static int jh7110_pinctrl_resume(struct device *dev)
987 {
988 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
989 unsigned long flags;
990 unsigned int i;
991
992 raw_spin_lock_irqsave(&sfp->lock, flags);
993 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
994 writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i);
995
996 raw_spin_unlock_irqrestore(&sfp->lock, flags);
997 return 0;
998 }
999
1000 const struct dev_pm_ops jh7110_pinctrl_pm_ops = {
1001 LATE_SYSTEM_SLEEP_PM_OPS(jh7110_pinctrl_suspend, jh7110_pinctrl_resume)
1002 };
1003 EXPORT_SYMBOL_GPL(jh7110_pinctrl_pm_ops);
1004
1005 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC");
1006 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1007 MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
1008 MODULE_LICENSE("GPL");
1009