| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 482 bool Interlace,
618 bool Interlace[],
1014 bool Interlace[],
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| H A D | display_mode_vba_32.c | 437 …ermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
696 v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] && in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
774 …hParametersWatermarksAndPerformanceCalculation.myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1439 isInterlaceTiming = (mode_lib->vba.Interlace[k] && in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1533 mode_lib->vba.Interlace, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1597 mode_lib->vba.Interlace, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2357 == dm_420 && mode_lib->vba.Interlace[k] == 1 && in dml32_ModeSupportAndSystemConfigurationFull()
2730 …deSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k]; in dml32_ModeSupportAndSystemConfigurationFull()
2962 mode_lib->vba.MaximumVStartup[i][j][k] = ((mode_lib->vba.Interlace[k] && in dml32_ModeSupportAndSystemConfigurationFull()
3083 mode_lib->vba.Interlace, in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
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| H A D | display_mode_vba_util_32.c | 2537 bool Interlace, in dml32_CalculatePrefetchSourceLines() argument
2568 *VInitPreFill = dml_floor((VRatio + (double) VTaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in dml32_CalculatePrefetchSourceLines()
2952 bool Interlace[], in dml32_UseMinimumDCFCLK()
3099 Interlace[k], in dml32_UseMinimumDCFCLK()
5608 bool Interlace[], in dml32_CalculateStutterEfficiency() argument
5862 bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP; in dml32_CalculateStutterEfficiency()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.c | 201 bool Interlace,
502 bool Interlace[],
673 bool Interlace,
1754 bool Interlace, argument
1767 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
2374 v->Interlace[k],
2431 v->Interlace[k],
2568 v->Interlace[k],
2627 myPipe.InterlaceEnable = v->Interlace[k];
3169 isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_mode_vba_20v2.c | 85 bool Interlace,
150 bool Interlace,
492 bool Interlace, in CalculateDelayAfterScaler()
529 if (OutputFormat == dm_420 || (Interlace && ProgressiveToInterlaceUnitInOPP)) in CalculateDelayAfterScaler()
873 bool Interlace, in CalculatePrefetchSourceLines() argument
885 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in CalculatePrefetchSourceLines()
1930 mode_lib->vba.Interlace[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1972 mode_lib->vba.Interlace[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2129 …lDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2174 mode_lib->vba.Interlace[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]
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| H A D | display_mode_vba_20.c | 126 bool Interlace,
813 bool Interlace, in CalculatePrefetchSourceLines() argument
825 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in CalculatePrefetchSourceLines()
1894 mode_lib->vba.Interlace[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1936 mode_lib->vba.Interlace[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2140 mode_lib->vba.Interlace[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4172 && mode_lib->vba.Interlace[k] == true in dml20_ModeSupportAndSystemConfigurationFull()
4527 mode_lib->vba.Interlace[k], in dml20_ModeSupportAndSystemConfigurationFull()
4566 mode_lib->vba.Interlace[k], in dml20_ModeSupportAndSystemConfigurationFull()
4757 mode_lib->vba.Interlace[k], in dml20_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 192 bool Interlace,
493 bool Interlace[],
1737 bool Interlace, argument
1750 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
2355 v->Interlace[k],
2412 v->Interlace[k],
2542 (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
2608 myPipe.InterlaceEnable = v->Interlace[k];
3150 isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
3225 v->Interlace,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_utils.c | 45 dml_timing_array->Interlace[dst_index] = dml_timing_array->Interlace[src_index]; in dml2_util_copy_dml_timing()
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| H A D | display_mode_core_structs.h | 612 dml_bool_t Interlace[__DML_NUM_PLANES__]; member
1300 dml_bool_t *Interlace; member
1543 dml_bool_t *Interlace; member
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| H A D | dml_display_rq_dlg_calc.c | 215 dml_bool_t interlaced = timing->Interlace[plane_idx]; in dml_rq_dlg_get_dlg_reg()
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| H A D | display_mode_core.c | 219 dml_bool_t Interlace,
2378 dml_bool_t Interlace, in CalculatePrefetchSourceLines() argument
2409 …*VInitPreFill = (dml_uint_t)(dml_floor((VRatio + (dml_float_t) VTaps + 1 + Interlace * 0.5 * VRati… in CalculatePrefetchSourceLines()
2700 if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) { in PixelClockAdjustmentForProgressiveToInterlaceUnit()
3924 dml_bool_t isInterlaceTiming = p->Interlace[k] && !p->ProgressiveToInterlaceUnitInOPP; in CalculateStutterEfficiency()
4670 p->Interlace[k], in UseMinimumDCFCLK()
6201 if (timing->Interlace[plane_idx] && !ptoi_supported) in CalculateMaxVStartup()
6376 myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k]; in dml_prefetch_check()
7392 …put.OutputFormat[k] == dml_420 && mode_lib->ms.cache_display_cfg.timing.Interlace[k] == 1 && mode_… in dml_core_mode_support()
7730 s->SurfParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k]; in dml_core_mode_support()
[all …]
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| H A D | display_mode_util.c | 538 dml_print("DML: timing_cfg: plane=%d, Interlace = %d\n", i, timing->Interlace[i]); in dml_print_dml_display_cfg_timing()
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| H A D | dml2_translation_helper.c | 768 out->Interlace[location] = in->timing.flags.INTERLACE; in populate_dml_timing_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 146 bool Interlace,
1518 bool Interlace, in CalculatePrefetchSourceLines() argument
1530 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in CalculatePrefetchSourceLines()
2130 v->Interlace[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2187 v->Interlace[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2337 myPipe.InterlaceEnable = v->Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4013 …|| (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP … in dml30_ModeSupportAndSystemConfigurationFull()
4240 v->Interlace[k], in dml30_ModeSupportAndSystemConfigurationFull()
4295 v->Interlace[k], in dml30_ModeSupportAndSystemConfigurationFull()
4602 myPipe.InterlaceEnable = v->Interlace[k]; in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_mode_vba_21.c | 164 bool Interlace,
1212 bool Interlace, in CalculatePrefetchSourceLines() argument
1224 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in CalculatePrefetchSourceLines()
1865 mode_lib->vba.Interlace[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1921 mode_lib->vba.Interlace[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2148 myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3442 myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; in CalculatePrefetchSchedulePerPlane()
4387 && mode_lib->vba.Interlace[k] == true in dml21_ModeSupportAndSystemConfigurationFull()
4637 mode_lib->vba.Interlace[k], in dml21_ModeSupportAndSystemConfigurationFull()
4693 mode_lib->vba.Interlace[k], in dml21_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 594 mode_lib->vba.Interlace[mode_lib->vba.NumberOfActivePlanes] = dst->interlaced; in fetch_pipe_params()
1055 if (mode_lib->vba.Interlace[k] == 1 in PixelClockAdjustmentForProgressiveToInterlaceUnit()
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| H A D | display_mode_vba.h | 498 bool Interlace[DC__NUM_DPP__MAX]; member
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| /linux/drivers/gpu/drm/amd/display/dc/bios/ |
| H A D | bios_parser.c | 1370 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace; in get_embedded_panel_info_v1_2()
1488 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace; in get_embedded_panel_info_v1_3()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 3246 USHORT Interlace:1; member
3262 USHORT Interlace:1;
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 3723 USHORT Interlace:1; member
3739 USHORT Interlace:1;
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 1830 bool Interlace, in CalculatePrefetchSourceLines() argument
1862 …*VInitPreFill = (unsigned int)(math_floor2((VRatio + (double)VTaps + 1 + (Interlace ? 1 : 0) * 0.5… in CalculatePrefetchSourceLines()
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