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/linux/Documentation/translations/zh_CN/core-api/irq/
H A Dirq-domain.rst16 目前Linux内核的设计使用了一个巨大的数字空间，每个独立的IRQ源都被分配了一个不
19 个中断控制器都能得到非重复的Linux IRQ号（数字）分配。
23 避免了重新实现与IRQ核心系统相同的回调机制。
25 在这里，中断号与硬件中断号离散了所有种类的对应关系：而在过去，IRQ号可以选择，
26 使它们与硬件IRQ线进入根中断控制器（即实际向CPU发射中断线的组件）相匹配，现
29 出于这个原因，我们需要一种机制将控制器本地中断号（即硬件irq编号）与Linux IRQ
33 提供任何对控制器本地IRQ(hwirq)号到Linux IRQ号空间的反向映射的支持。
35 irq_domain 库在 irq_alloc_desc*() API 的基础上增加了 hwirq 和 IRQ 号码
40 Device Tree和ACPI GSI），并且可以很容易地扩展以支持其它IRQ拓扑数据源。
50 在大多数情况下，irq_domain在开始时是空的，没有任何hwirq和IRQ号之间的映射。
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H A Dconcepts.rst12 什么是IRQ？
15 IRQ (Interrupt ReQuest) 指来自设备的中断请求。
17 多个设备可以连接到同一个引脚，从而共享一个IRQ。
19 IRQ编号是用来描述硬件中断源的内核标识符。通常它是一个到全局irq_desc数组的索引，
22 IRQ编号是对机器上可能的中断源的枚举。通常枚举的是系统中所有中断控制器的输入引脚
25 体系结构可以给IRQ号赋予额外的含义，在涉及到硬件手动配置的情况下，我们鼓励这样做。
26 ISA IRQ是赋予这种额外含义的一个典型例子。
H A Dirq-affinity.rst12 SMP IRQ 亲和性
20 /proc/irq/IRQ#/smp_affinity和/proc/irq/IRQ#/smp_affinity_list指定了哪些CPU能
21 够关联到一个给定的IRQ源，这两个文件包含了这些指定cpu的cpu位掩码(smp_affinity)和cpu列
22 表(smp_affinity_list)。它不允许关闭所有CPU， 同时如果IRQ控制器不支持中断请求亲和
23 (IRQ affinity)，那么所有cpu的默认值将保持不变(即关联到所有CPU).
25 /proc/irq/default_smp_affinity指明了适用于所有非激活IRQ的默认亲和性掩码。一旦IRQ被
50 现在让我们把这个IRQ限制在CPU(4-7)。
/linux/Documentation/translations/zh_CN/core-api/
H A Dgenericirq.rst18 Linux通用IRQ处理
32 本文档提供给那些希望在通用IRQ处理层的帮助下实现基于其架构的中断子系统的开发
58 这种高层IRQ处理程序的拆分实现使我们能够为每个特定的中断类型优化中断处理的流
61 最初的通用IRQ实现使用hw_interrupt_type结构体及其 ``->ack`` ``->end`` 等回
64 这两个IRQ类型共享许多低级的细节，但有不同的流处理。
68 分析一些架构的IRQ子系统的实现可以发现，他们中的大多数可以使用一套通用的“irq
69 流”方法，只需要添加芯片级的特定代码。这种分离对于那些需要IRQ流本身而不需要芯
70 片细节的特定（子）架构也很有价值——以提供了一个更透明的IRQ子系统设计。
77 的IRQ流实现“电平触发型”中断，并添加一个（子）架构特定的“边沿型”实现。
81 被使用，因为它能使IRQ子系统更小更干净。它已经被废弃三年了，即将被删除。
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/linux/Documentation/translations/zh_CN/PCI/
H A Dpci.rst58 - 注册IRQ处理程序(request_irq())
64 - 禁用设备产生的IRQ
65 - 释放IRQ（free_irq()）
186 - 注册IRQ处理程序（request_irq()）
201 - 分配一个IRQ（如果BIOS没有）。
284 注册IRQ处理函数
289 所有IRQ线的中断处理程序都应该用 ``IRQF_SHARED`` 注册，并使用devid将IRQ映射
290 到设备（记住，所有的PCI IRQ线都可以共享）。
293 中断号码代表从PCI设备到中断控制器的IRQ线。在MSI和MSI-X中（更多内容见下文），中
318 2) MSI避免了DMA/IRQ竞争条件。到主机内存的DMA被保证在MSI交付时对主机CPU是可
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/linux/Documentation/translations/zh_CN/networking/
H A Dnapi.rst96 调度与IRQ屏蔽
101 显式屏蔽中断的驱动程序（而非设备自动屏蔽 IRQ）应使用 napi_schedule_prep() 和
112 IRQ 仅应在成功调用 napi_complete_done() 后取消屏蔽：
121 napi_schedule_irqoff() 是 napi_schedule() 的一个变体，它利用了在中断请求（IRQ）上下文
122 环境中调用所带来的特性（无需屏蔽中断）。如果中断请求（IRQ）是通过线程处理的（例如启用了
141 将一个通道视为一个为特定类型队列提供服务的 IRQ（中断请求）/ NAPI 实例。例如，配置为 1 个
178 软件IRQ合并
182 的中断请求（IRQ）合并。不过，在某些情况下，软件层面的合并操作也很有帮助。
209 ``irq-suspend-timeout`` 用于确定应用程序可以完全挂起 IRQ 的时长。与 SO_PREFER_BUSY_POLL
256 IRQ缓解
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/linux/Documentation/arch/arm/
H A Dinterrupts.rst16 Secondly, the IRQ subsystem.
39 SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
48 We also bring the idea of an IRQ "chip" (mainly to reduce the size of
57 * Acknowledge the IRQ.
58 * If this is a level-based IRQ, then it is expected to mask the IRQ
63 * Mask the IRQ in hardware.
67 * Unmask the IRQ in hardware.
71 * Re-run the IRQ
75 * Set the type of the IRQ.
90 the hardware IRQ if possible. If not, may call the handler
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/linux/Documentation/core-api/irq/
H A Dirq-domain.rst6 space where each separate IRQ source is assigned a unique number.
10 IRQ numbers.
15 mechanisms as the IRQ core system by modelling their interrupt
18 So in the past, IRQ numbers could be chosen so that they match the
19 hardware IRQ line into the root interrupt controller (i.e. the
25 interrupt numbers, called hardware IRQs, from Linux IRQ numbers.
28 IRQ numbers, but they don't provide any support for reverse mapping of
29 the controller-local IRQ (hwirq) number into the Linux IRQ number
32 The irq_domain library adds a mapping between hwirq and IRQ numbers on
40 other IRQ topology data sources. The implementation is performed
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H A Dirq-affinity.rst2 SMP IRQ affinity
10 /proc/irq/IRQ#/smp_affinity and /proc/irq/IRQ#/smp_affinity_list specify
11 which target CPUs are permitted for a given IRQ source. It's a bitmask
13 allowed to turn off all CPUs, and if an IRQ controller does not support
14 IRQ affinity then the value will not change from the default of all CPUs.
17 to all non-active IRQs. Once IRQ is allocated/activated its affinity bitmask
43 Now lets restrict that IRQ to CPU(4-7).
63 Here is an example of limiting that same IRQ (44) to CPUs 1024 to 1031::
H A Dconcepts.rst2 What is an IRQ?
5 An IRQ is an interrupt request from a device. Currently, they can come
7 the same pin thus sharing an IRQ. Such as on legacy PCI bus: All devices
11 An IRQ number is a kernel identifier used to talk about a hardware
16 An IRQ number is an enumeration of the possible interrupt sources on a
22 Architectures can assign additional meaning to the IRQ numbers, and
/linux/Documentation/translations/zh_TW/
H A DIRQ.txt26 何爲 IRQ?
28 一個 IRQ 是來自某個設備的一個中斷請求。目前，它們可以來自一個硬體引腳，
29 或來自一個數據包。多個設備可能連接到同個硬體引腳，從而共享一個 IRQ。
31 一個 IRQ 編號是用於告知硬體中斷源的內核標識。通常情況下，這是一個
35 一個 IRQ 編號是設備上某個可能的中斷源的枚舉。通常情況下，枚舉的編號是
39 架構可以對 IRQ 編號指定額外的含義，在硬體涉及任何手工配置的情況下，
40 是被提倡的。ISA 的 IRQ 是一個分配這類額外含義的典型例子。
/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst9 LoongArch的IRQ芯片模型（层级关系）
13 中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
20 断控制器（在配套芯片组里面）。这些中断控制器（或者说IRQ芯片）以一种层次树的组织形式
21 级联在一起，一共有两种层级关系模型（传统IRQ模型和扩展IRQ模型）。
23 传统IRQ模型
59 扩展IRQ模型
90 虚拟扩展IRQ模型
145 高级扩展IRQ模型
/linux/Documentation/misc-devices/
H A Dpci-endpoint-test.rst16 #) raise legacy IRQ
17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
34 Tests legacy IRQ
42 Changes driver IRQ type configuration. The IRQ type
45 Gets driver IRQ type configuration.
/linux/Documentation/driver-api/hte/
H A Dtegra-hte.rst10 (Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp
34 LIC (Legacy Interrupt Controller) IRQ GTE
37 This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree
39 provides an example of how a consumer can request an IRQ line. Since it is a
40 one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ
44 The provider source code of both IRQ and GPIO GTE instances is located at
46 ``drivers/hte/hte-tegra194-test.c`` demonstrates HTE API usage for both IRQ
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst9 LoongArch的IRQ芯片模型（層級關係）
13 中的中斷控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
20 斷控制器（在配套芯片組裏面）。這些中斷控制器（或者說IRQ芯片）以一種層次樹的組織形式
21 級聯在一起，一共有兩種層級關係模型（傳統IRQ模型和擴展IRQ模型）。
23 傳統IRQ模型
59 擴展IRQ模型
/linux/Documentation/core-api/
H A Dgenericirq.rst4 Linux generic IRQ handling
23 generic IRQ handling layer.
51 This split implementation of high-level IRQ handlers allows us to
56 The original general IRQ implementation used hw_interrupt_type
61 ``ioapic_edge_irq`` IRQ-type which share many of the low-level details but
67 Analysing a couple of architecture's IRQ subsystem implementations
71 IRQ flow itself but not in the chip details - and thus provides a more
72 transparent IRQ subsystem design.
82 IRQ-flow implementation for 'level type' interrupts and add a
89 enables smaller and cleaner IRQ subsystems. It's deprecated for three
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/linux/drivers/pinctrl/renesas/
H A Dpfc-r8a73a4.c236 #define IRQ(a) IRQ##a##_MARK macro
238 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */ enumerator
239 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1), enumerator
240 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2), enumerator
241 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3), enumerator
242 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4), enumerator
243 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5), enumerator
244 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6), enumerator
245 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7), enumerator
246 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8), enumerator
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/linux/Documentation/power/
H A Dsuspend-and-interrupts.rst43 The IRQF_NO_SUSPEND flag is used to indicate that to the IRQ subsystem when
45 leave the corresponding IRQ enabled so as to allow the interrupt to work as
50 Note that the IRQF_NO_SUSPEND flag affects the entire IRQ and not just one
51 user of it. Thus, if the IRQ is shared, all of the interrupt handlers installed
54 the IRQ's users. For this reason, using IRQF_NO_SUSPEND and IRQF_SHARED at the
75 The IRQ subsystem provides two helper functions to be used by device drivers for
77 handling the given IRQ as a system wakeup interrupt line and disable_irq_wake()
80 Calling enable_irq_wake() causes suspend_device_irqs() to treat the given IRQ
81 in a special way. Namely, the IRQ remains enabled, but on the first interrupt
105 IRQ subsystem to trigger a system wakeup.
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/linux/Documentation/virt/kvm/devices/
H A Dmpic.rst34 IRQ input line for each standard openpic source. 0 is inactive and 1
41 "attr" is the IRQ number. IRQ numbers for standard sources are the
44 IRQ Routing:
46 The MPIC emulation supports IRQ routing. Only a single MPIC device can
58 Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.
/linux/Documentation/tools/rtla/
H A Drtla-timerlat-hist.rst49 …Index IRQ-000 Thr-000 IRQ-001 Thr-001 IRQ-002 Thr-002 IRQ-003 Thr-003 IRQ-004 …
H A Drtla-timerlat-top.rst53 0 00:00:12 | IRQ Timer Latency (us) | Thread Timer Latency (us)
80 IRQ handler delay: 27.49 us (65.52 %)
81 IRQ latency: 28.13 us
82 Timerlat IRQ duration: 9.59 us (22.85 %)
109 Max timerlat IRQ latency from idle: 17.48 us in cpu 4
112 In this case, the major factor was the delay suffered by the *IRQ handler*
/linux/arch/arc/kernel/
H A Dentry-compact.S118 ;##################### Scratch Mem for IRQ stack switching #############
152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
155 ; -L1 IRQ taken
157 ; -preemption off IRQ, user task in syscall picked to run
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
306 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
307 ; IRQ shd definitely not happen between now and rtie
320 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
343 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
350 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
/linux/Documentation/arch/x86/i386/
H A DIO-APIC.rst17 distribute IRQ load further.
40 none of those IRQ sources is performance-critical.
44 you can use the pirq= boot parameter to 'hand-construct' IRQ entries. This
52 connected to the PCI chipset IRQ routing facility (the incoming PIRQ1-4
65 Every PCI card emits a PCI IRQ, which can be INTA, INTB, INTC or INTD::
79 a card in slot4, issuing INTA IRQ, it will end up as a signal on PIRQ4 of
81 between the PIRQ lines. (distributing IRQ sources properly is not a
103 [value '0' is a generic 'placeholder', reserved for empty (or non-IRQ emitting)
107 permute all IRQ numbers properly ... it will take some time though. An
/linux/Documentation/scsi/
H A Dg_NCR5380.rst22 for the correct IRQ line automatically. If the irq parameter is 0 or 255
23 then no IRQ will be used.
71 E.g. a port mapped NCR5380 board, driver to probe for IRQ::
79 E.g. a memory mapped NCR53C400 board with no IRQ::
87 E.g. two cards, DTC3181 (in non-PnP mode) at 0x240 with no IRQ
88 and HP C2502 at 0x300 with IRQ 7::
/linux/Documentation/devicetree/bindings/iio/accel/
H A Dlis302.txt36 - st,irq{1,2}-disable: disable IRQ 1/2
37 - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition
38 - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition
39 - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready condition
40 - st,irq{1,2}-click: raise IRQ 1/2 on click condition
41 - st,irq-open-drain: consider IRQ lines open-drain
42 - st,irq-active-low: make IRQ lines active low

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