| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfxhub_v2_0.c | 228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v2_0_init_cache_regs()
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| H A D | gfxhub_v3_0_3.c | 234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v3_0_3_init_cache_regs()
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| H A D | gfxhub_v1_0.c | 191 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs()
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| H A D | gfxhub_v12_0.c | 237 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v12_0_init_cache_regs()
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| H A D | gfxhub_v3_0.c | 229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v3_0_init_cache_regs()
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| H A D | gfxhub_v11_5_0.c | 232 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v11_5_0_init_cache_regs()
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| H A D | gfxhub_v1_2.c | 242 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_2_xcc_init_cache_regs()
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| H A D | mmhub_v1_8.c | 292 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, in mmhub_v1_8_init_cache_regs()
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| H A D | mmhub_v1_0.c | 177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
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| H A D | gmc_v7_0.c | 643 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
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| H A D | mmhub_v1_7.c | 219 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_7_init_cache_regs()
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| H A D | gmc_v8_0.c | 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
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| H A D | mmhub_v9_4.c | 257 INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v9_4_init_cache_regs()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv770d.h | 648 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | nid.h | 118 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | sid.h | 379 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | cikd.h | 497 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | evergreend.h | 1156 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | r600d.h | 593 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
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| H A D | ni.c | 1274 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
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| H A D | si.c | 4291 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
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| H A D | cik.c | 5445 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
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