Searched refs:INTEL_PMC_IDX_FIXED (Results 1 – 7 of 7) sorted by relevance
13 #define INTEL_PMC_IDX_FIXED 32 macro342 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)346 #define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)350 #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)355 #define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)374 #define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)382 #define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)
1679 if (idx >= INTEL_PMC_IDX_FIXED) in __intel_pmu_pebs_update_cfg()1680 *pebs_data_cfg |= PEBS_DATACFG_FIX_BIT(idx - INTEL_PMC_IDX_FIXED); in __intel_pmu_pebs_update_cfg()1858 if (hwc->idx >= INTEL_PMC_IDX_FIXED) { in intel_pmu_pebs_via_pt_enable()1860 idx = hwc->idx - INTEL_PMC_IDX_FIXED; in intel_pmu_pebs_via_pt_enable()1919 if (idx >= INTEL_PMC_IDX_FIXED) { in intel_pmu_pebs_enable()1921 idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED); in intel_pmu_pebs_enable()1923 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED); in intel_pmu_pebs_enable()2394 (bit + INTEL_PMC_IDX_FIXED == INTEL_PMC_IDX_FIXED_SLOTS)) { in __setup_pebs_counter_group()2398 intel_perf_event_update_pmc(cpuc->events[bit + INTEL_PMC_IDX_FIXED], in __setup_pebs_counter_group()3016 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; in intel_pmu_drain_pebs_nhm()[all …]
2773 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); in intel_pmu_disable_fixed()2782 if (idx < INTEL_PMC_IDX_FIXED) { in __intel_pmu_update_event_ext()2787 x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); in __intel_pmu_update_event_ext()2821 case 0 ... INTEL_PMC_IDX_FIXED - 1: in intel_pmu_disable_event()2826 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: in intel_pmu_disable_event()3140 idx -= INTEL_PMC_IDX_FIXED; in intel_pmu_enable_fixed()3158 if (idx < INTEL_PMC_IDX_FIXED) { in intel_pmu_config_acr()3165 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); in intel_pmu_config_acr()3303 case 0 ... INTEL_PMC_IDX_FIXED - 1: in intel_pmu_enable_event()3311 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: in intel_pmu_enable_event()[all …]
292 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; in zhaoxin_pmu_disable_fixed()316 int idx = hwc->idx - INTEL_PMC_IDX_FIXED; in zhaoxin_pmu_enable_fixed()608 x86_pmu.intel_ctrl |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED; in zhaoxin_pmu_init()
903 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { in __perf_sched_find_counter()904 idx = INTEL_PMC_IDX_FIXED; in __perf_sched_find_counter()918 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { in __perf_sched_find_counter()1261 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1: in x86_assign_hw_event()1263 hwc->event_base = x86_pmu_fixed_ctr_addr(idx - INTEL_PMC_IDX_FIXED); in x86_assign_hw_event()1264 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | in x86_assign_hw_event()2558 if (i >= INTEL_PMC_IDX_FIXED) { in perf_clear_dirty_counters()2560 if (!test_bit(i - INTEL_PMC_IDX_FIXED, hybrid(cpuc->pmu, fixed_cntr_mask))) in perf_clear_dirty_counters()2563 wrmsrq(x86_pmu_fixed_ctr_addr(i - INTEL_PMC_IDX_FIXED), 0); in perf_clear_dirty_counters()
1454 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); in fixed_counter_disabled()
24 #define KVM_FIXED_PMC_BASE_IDX INTEL_PMC_IDX_FIXED