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/linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Dirq.c16 const irq_ID_t ID);
19 const irq_ID_t ID);
51 const irq_ID_t ID) in irq_clear_all() argument
55 assert(ID < N_IRQ_ID); in irq_clear_all()
56 assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH); in irq_clear_all()
58 if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) { in irq_clear_all()
59 mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]); in irq_clear_all()
62 irq_reg_store(ID, in irq_clear_all()
71 const irq_ID_t ID, in irq_enable_channel() argument
74 unsigned int mask = irq_reg_load(ID, in irq_enable_channel()
[all …]
H A Dfifo_monitor.c35 const fifo_monitor_ID_t ID,
40 const fifo_monitor_ID_t ID,
45 const fifo_monitor_ID_t ID, in fifo_channel_get_state() argument
54 state->src_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
57 state->fifo_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
60 state->fifo_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
63 state->sink_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
68 state->src_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
71 state->fifo_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
74 state->fifo_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
[all …]
H A Dinput_formatter.c51 const input_formatter_ID_t ID) in input_formatter_rst() argument
56 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_rst()
58 addr = HIVE_IF_SRST_ADDRESS[ID]; in input_formatter_rst()
59 rst = HIVE_IF_SRST_MASK[ID]; in input_formatter_rst()
65 if (!HIVE_IF_BIN_COPY[ID]) { in input_formatter_rst()
66 input_formatter_reg_store(ID, addr, rst); in input_formatter_rst()
73 const input_formatter_ID_t ID) in input_formatter_get_alignment() argument
75 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_get_alignment()
77 return input_formatter_alignment[ID]; in input_formatter_get_alignment()
81 const input_formatter_ID_t ID, in input_formatter_set_fifo_blocking_mode() argument
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H A Dsp_private.h17 const sp_ID_t ID, in sp_ctrl_store() argument
21 assert(ID < N_SP_ID); in sp_ctrl_store()
22 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); in sp_ctrl_store()
23 ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in sp_ctrl_store()
28 const sp_ID_t ID, in sp_ctrl_load() argument
31 assert(ID < N_SP_ID); in sp_ctrl_load()
32 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); in sp_ctrl_load()
33 return ia_css_device_load_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in sp_ctrl_load()
37 const sp_ID_t ID, in sp_ctrl_getbit() argument
41 hrt_data val = sp_ctrl_load(ID, reg); in sp_ctrl_getbit()
[all …]
H A Dgp_device.c15 const gp_device_ID_t ID, in gp_device_get_state() argument
18 assert(ID < N_GP_DEVICE_ID); in gp_device_get_state()
21 state->syncgen_enable = gp_device_reg_load(ID, in gp_device_get_state()
23 state->syncgen_free_running = gp_device_reg_load(ID, in gp_device_get_state()
25 state->syncgen_pause = gp_device_reg_load(ID, in gp_device_get_state()
27 state->nr_frames = gp_device_reg_load(ID, in gp_device_get_state()
29 state->syngen_nr_pix = gp_device_reg_load(ID, in gp_device_get_state()
31 state->syngen_nr_pix = gp_device_reg_load(ID, in gp_device_get_state()
33 state->syngen_nr_lines = gp_device_reg_load(ID, in gp_device_get_state()
35 state->syngen_hblank_cycles = gp_device_reg_load(ID, in gp_device_get_state()
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H A Disp_private.h22 const isp_ID_t ID, in isp_ctrl_store() argument
26 assert(ID < N_ISP_ID); in isp_ctrl_store()
27 assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); in isp_ctrl_store()
29 ia_css_device_store_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in isp_ctrl_store()
31 hrt_master_port_store_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in isp_ctrl_store()
37 const isp_ID_t ID, in isp_ctrl_load() argument
40 assert(ID < N_ISP_ID); in isp_ctrl_load()
41 assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); in isp_ctrl_load()
43 return ia_css_device_load_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in isp_ctrl_load()
45 return hrt_master_port_uload_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in isp_ctrl_load()
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H A Devent_fifo_private.h18 STORAGE_CLASS_EVENT_C void event_wait_for(const event_ID_t ID) in event_wait_for() argument
20 assert(ID < N_EVENT_ID); in event_wait_for()
21 assert(event_source_addr[ID] != ((hrt_address) - 1)); in event_wait_for()
22 (void)ia_css_device_load_uint32(event_source_addr[ID]); in event_wait_for()
26 STORAGE_CLASS_EVENT_C void cnd_event_wait_for(const event_ID_t ID, in cnd_event_wait_for() argument
30 event_wait_for(ID); in cnd_event_wait_for()
34 STORAGE_CLASS_EVENT_C hrt_data event_receive_token(const event_ID_t ID) in event_receive_token() argument
36 assert(ID < N_EVENT_ID); in event_receive_token()
37 assert(event_source_addr[ID] != ((hrt_address) - 1)); in event_receive_token()
38 return ia_css_device_load_uint32(event_source_addr[ID]); in event_receive_token()
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H A Dinput_system.c35 static void receiver_rst(const rx_ID_t ID);
36 static void input_system_network_rst(const input_system_ID_t ID);
39 const input_system_ID_t ID,
44 const input_system_ID_t ID,
49 const input_system_ID_t ID,
54 const input_system_ID_t ID,
73 static void gp_device_rst(const gp_device_ID_t ID);
75 static void input_selector_cfg_for_sensor(const gp_device_ID_t ID);
77 static void input_switch_rst(const gp_device_ID_t ID);
80 const gp_device_ID_t ID,
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H A Disp.c19 const isp_ID_t ID, in cnd_isp_irq_enable() argument
23 isp_ctrl_setbit(ID, ISP_IRQ_READY_REG, ISP_IRQ_READY_BIT); in cnd_isp_irq_enable()
25 isp_ctrl_setbit(ID, ISP_IRQ_CLEAR_REG, ISP_IRQ_CLEAR_BIT); in cnd_isp_irq_enable()
27 isp_ctrl_clearbit(ID, ISP_IRQ_READY_REG, in cnd_isp_irq_enable()
36 unsigned int isp_is_ready(isp_ID_t ID) in isp_is_ready() argument
38 assert(ID < N_ISP_ID); in isp_is_ready()
39 return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT); in isp_is_ready()
43 unsigned int isp_is_sleeping(isp_ID_t ID) in isp_is_sleeping() argument
45 assert(ID < N_ISP_ID); in isp_is_sleeping()
46 return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_SLEEPING_BIT); in isp_is_sleeping()
[all …]
H A Dfifo_monitor_private.h24 const fifo_monitor_ID_t ID, in fifo_switch_set() argument
28 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_set()
29 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_switch_set()
31 (void)ID; in fifo_switch_set()
39 const fifo_monitor_ID_t ID, in fifo_switch_get() argument
42 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_get()
43 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_switch_get()
45 (void)ID; in fifo_switch_get()
51 const fifo_monitor_ID_t ID, in fifo_monitor_reg_store() argument
55 assert(ID < N_FIFO_MONITOR_ID); in fifo_monitor_reg_store()
[all …]
/linux/drivers/staging/media/atomisp/pci/css_2401_system/host/
H A Dcsi_rx_private.h29 const csi_rx_frontend_ID_t ID, in csi_rx_fe_ctrl_reg_load() argument
32 assert(ID < N_CSI_RX_FRONTEND_ID); in csi_rx_fe_ctrl_reg_load()
33 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); in csi_rx_fe_ctrl_reg_load()
34 return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof( in csi_rx_fe_ctrl_reg_load()
43 const csi_rx_frontend_ID_t ID, in csi_rx_fe_ctrl_reg_store() argument
47 assert(ID < N_CSI_RX_FRONTEND_ID); in csi_rx_fe_ctrl_reg_store()
48 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); in csi_rx_fe_ctrl_reg_store()
50 ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data), in csi_rx_fe_ctrl_reg_store()
59 const csi_rx_backend_ID_t ID, in csi_rx_be_ctrl_reg_load() argument
62 assert(ID < N_CSI_RX_BACKEND_ID); in csi_rx_be_ctrl_reg_load()
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H A Dpixelgen_private.h24 const pixelgen_ID_t ID, in pixelgen_ctrl_reg_load() argument
27 assert(ID < N_PIXELGEN_ID); in pixelgen_ctrl_reg_load()
28 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1); in pixelgen_ctrl_reg_load()
29 return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof( in pixelgen_ctrl_reg_load()
38 const pixelgen_ID_t ID, in pixelgen_ctrl_reg_store() argument
42 assert(ID < N_PIXELGEN_ID); in pixelgen_ctrl_reg_store()
43 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); in pixelgen_ctrl_reg_store()
45 ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data), in pixelgen_ctrl_reg_store()
61 const pixelgen_ID_t ID, in pixelgen_ctrl_get_state() argument
65 pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX); in pixelgen_ctrl_get_state()
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H A Disys_stream2mmio_private.h35 const stream2mmio_ID_t ID, in stream2mmio_get_state() argument
44 for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { in stream2mmio_get_state()
45 stream2mmio_get_sid_state(ID, i, &state->sid_state[i]); in stream2mmio_get_state()
54 const stream2mmio_ID_t ID, in stream2mmio_get_sid_state() argument
59 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID); in stream2mmio_get_sid_state()
62 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID); in stream2mmio_get_sid_state()
65 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID); in stream2mmio_get_sid_state()
68 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID); in stream2mmio_get_sid_state()
71 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID); in stream2mmio_get_sid_state()
74 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_NUM_ITEMS_REG_ID); in stream2mmio_get_sid_state()
[all …]
/linux/drivers/staging/media/atomisp/pci/
H A Disp2401_input_system_private.h18 static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_reg_load() argument
21 assert(ID < N_IBUF_CTRL_ID); in ibuf_ctrl_reg_load()
22 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); in ibuf_ctrl_reg_load()
23 return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in ibuf_ctrl_reg_load()
27 static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_reg_store() argument
31 assert(ID < N_IBUF_CTRL_ID); in ibuf_ctrl_reg_store()
32 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); in ibuf_ctrl_reg_store()
34 ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in ibuf_ctrl_reg_store()
38 static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_get_proc_state() argument
48 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE); in ibuf_ctrl_get_proc_state()
[all …]
H A Disp2400_input_system_private.h17 const input_system_ID_t ID, in input_system_reg_store() argument
21 assert(ID < N_INPUT_SYSTEM_ID); in input_system_reg_store()
22 assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); in input_system_reg_store()
23 ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof(hrt_data), in input_system_reg_store()
29 const input_system_ID_t ID, in input_system_reg_load() argument
32 assert(ID < N_INPUT_SYSTEM_ID); in input_system_reg_load()
33 assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); in input_system_reg_load()
34 return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof( in input_system_reg_load()
39 const rx_ID_t ID, in receiver_reg_store() argument
43 assert(ID < N_RX_ID); in receiver_reg_store()
[all …]
/linux/rust/kernel/
H A Dlist.rs263 pub struct List<T: ?Sized + ListItem<ID>, const ID: u64 = 0> {
265 _ty: PhantomData<ListArc<T, ID>>,
270 unsafe impl<T, const ID: u64> Send for List<T, ID>
272 ListArc<T, ID>: Send,
273 T: ?Sized + ListItem<ID>,
278 unsafe impl<T, const ID: u64> Sync for List<T, ID>
280 ListArc<T, ID>: Sync,
281 T: ?Sized + ListItem<ID>,
293 pub unsafe trait ListItem<const ID: u64 = 0>: ListArcSafe<ID> {
307 unsafe fn view_links(me: *const Self) -> *mut ListLinks<ID>; in view_links() argument
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H A Dworkqueue.rs267 pub fn enqueue<W, const ID: u64>(&self, w: W) -> W::EnqueueOutput in enqueue()
269 W: RawWorkItem<ID> + Send + 'static, in enqueue()
300 pub fn enqueue_delayed<W, const ID: u64>(&self, w: W, delay: Jiffies) -> W::EnqueueOutput in enqueue_delayed()
302 W: RawDelayedWorkItem<ID> + Send + 'static, in enqueue_delayed()
389 pub unsafe trait RawWorkItem<const ID: u64> {
424 pub unsafe trait RawDelayedWorkItem<const ID: u64>: RawWorkItem<ID> {}
443 pub unsafe trait WorkItemPointer<const ID: u64>: RawWorkItem<ID> {
458 pub trait WorkItem<const ID: u64 = 0> {
461 type Pointer: WorkItemPointer<ID>;
479 pub struct Work<T: ?Sized, const ID: u64 = 0> {
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/linux/drivers/scsi/aic7xxx/
H A Daic7xxx_osm_pci.c47 #define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI) macro
51 ID(ID_AHA_2902_04_10_15_20C_30C),
53 ID(ID_AHA_2930CU),
54 ID(ID_AHA_1480A & ID_DEV_VENDOR_MASK),
55 ID(ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK),
56 ID(ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK),
57 ID(ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK),
59 ID(ID_AHA_2940),
60 ID(ID_AHA_3940),
61 ID(ID_AHA_398X),
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H A Daiclib.h163 ID(x), \
164 ID((x) | 0x0001000000000000ull), \
165 ID((x) | 0x0002000000000000ull), \
166 ID((x) | 0x0003000000000000ull), \
167 ID((x) | 0x0004000000000000ull), \
168 ID((x) | 0x0005000000000000ull), \
169 ID((x) | 0x0006000000000000ull), \
170 ID((x) | 0x0007000000000000ull), \
171 ID((x) | 0x0008000000000000ull), \
172 ID((x) | 0x0009000000000000ull), \
[all …]
/linux/rust/kernel/list/
H A Darc.rs33 pub trait ListArcSafe<const ID: u64 = 0> {
57 pub unsafe trait TryNewListArc<const ID: u64 = 0>: ListArcSafe<ID> {
157 /// * Each reference counted object has at most one `ListArc` for each value of `ID`.
163 pub struct ListArc<T, const ID: u64 = 0>
165 T: ListArcSafe<ID> + ?Sized,
170 impl<T: ListArcSafe<ID>, const ID: u64> ListArc<T, ID> {
202 impl<T, const ID
279 try_from_arc(arc: Arc<T>) -> Result<Self, Arc<T>> where T: TryNewListArc<ID>, try_from_arc() argument
295 try_from_arc_borrow(arc: ArcBorrow<'_, T>) -> Option<Self> where T: TryNewListArc<ID>, try_from_arc_borrow() argument
310 try_from_arc_or_drop(arc: Arc<T>) -> Option<Self> where T: TryNewListArc<ID>, try_from_arc_or_drop() argument
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/linux/drivers/gpu/drm/i915/
H A Dintel_device_info.c127 #define ID(id) (id) macro
130 INTEL_HSW_ULT_GT1_IDS(ID),
131 INTEL_HSW_ULT_GT2_IDS(ID),
132 INTEL_HSW_ULT_GT3_IDS(ID),
133 INTEL_BDW_ULT_GT1_IDS(ID),
134 INTEL_BDW_ULT_GT2_IDS(ID),
135 INTEL_BDW_ULT_GT3_IDS(ID),
136 INTEL_BDW_ULT_RSVD_IDS(ID),
137 INTEL_SKL_ULT_GT1_IDS(ID),
138 INTEL_SKL_ULT_GT2_IDS(ID),
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/linux/drivers/pinctrl/cirrus/
H A Dpinctrl-lochnagar.c53 #define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \ argument
54 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \
59 #define LN_PIN_SAIF(REV, ID, NAME) \ argument
60 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \
63 #define LN_PIN_AIF(REV, ID) \ argument
64 LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \
65 LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
66 LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
67 LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
69 #define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \ argument
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/linux/Documentation/translations/zh_CN/core-api/
H A Didr.rst18 ID分配
27 符、进程ID、网络协议中的数据包标识符、SCSI标记和设备实例编号。IDR和IDA为这个问题
28 提供了一个合理的解决方案，以避免每个人都自创。IDR提供将ID映射到指针的能力，而IDA
29 仅提供ID分配，因此内存效率更高。
39 您可以调用idr_alloc()来分配一个未使用的ID。通过调用idr_find()查询与该ID相关的指针，
40 并通过调用idr_remove()释放该ID。
42 如果需要更改与一个ID相关联的指针，可以调用idr_replace()。这样做的一个常见原因是通
43 过将 ``NULL`` 指针传递给分配函数来保留ID；用保留的ID初始化对象，最后将初始化的对
46 一些用户需要分配大于 ``INT_MAX`` 的ID。到目前为止，所有这些用户都满足 ``UINT_MAX``
47 的限制，他们使用idr_alloc_u32()。如果您需要超出u32的ID，我们将与您合作以满足您的
[all …]
/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
H A Disp_public.h21 const isp_ID_t ID,
33 const isp_ID_t ID,
46 const isp_ID_t ID,
58 const isp_ID_t ID,
71 const isp_ID_t ID,
84 const isp_ID_t ID,
98 const isp_ID_t ID,
113 const isp_ID_t ID,
128 const isp_ID_t ID,
142 const isp_ID_t ID,
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/linux/drivers/char/agp/
H A Dvia-agp.c506 #define ID(x) \ macro
515 ID(PCI_DEVICE_ID_VIA_82C597_0),
516 ID(PCI_DEVICE_ID_VIA_82C598_0),
517 ID(PCI_DEVICE_ID_VIA_8501_0),
518 ID(PCI_DEVICE_ID_VIA_8601_0),
519 ID(PCI_DEVICE_ID_VIA_82C691_0),
520 ID(PCI_DEVICE_ID_VIA_8371_0),
521 ID(PCI_DEVICE_ID_VIA_8633_0),
522 ID(PCI_DEVICE_ID_VIA_XN266),
523 ID(PCI_DEVICE_ID_VIA_8361),
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