1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2022 Intel Corporation */ 3 #ifndef _ICP_QAT_FW_COMP_H_ 4 #define _ICP_QAT_FW_COMP_H_ 5 #include "icp_qat_fw.h" 6 7 enum icp_qat_fw_comp_cmd_id { 8 ICP_QAT_FW_COMP_CMD_STATIC = 0, 9 ICP_QAT_FW_COMP_CMD_DYNAMIC = 1, 10 ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2, 11 ICP_QAT_FW_COMP_CMD_ZSTD_COMPRESS = 10, 12 ICP_QAT_FW_COMP_CMD_ZSTD_DECOMPRESS = 11, 13 ICP_QAT_FW_COMP_CMD_DELIMITER 14 }; 15 16 enum icp_qat_fw_comp_20_cmd_id { 17 ICP_QAT_FW_COMP_20_CMD_LZ4_COMPRESS = 3, 18 ICP_QAT_FW_COMP_20_CMD_LZ4_DECOMPRESS = 4, 19 ICP_QAT_FW_COMP_20_CMD_LZ4S_COMPRESS = 5, 20 ICP_QAT_FW_COMP_20_CMD_LZ4S_DECOMPRESS = 6, 21 ICP_QAT_FW_COMP_20_CMD_RESERVED_7 = 7, 22 ICP_QAT_FW_COMP_20_CMD_RESERVED_8 = 8, 23 ICP_QAT_FW_COMP_20_CMD_RESERVED_9 = 9, 24 ICP_QAT_FW_COMP_23_CMD_ZSTD_COMPRESS = 10, 25 ICP_QAT_FW_COMP_23_CMD_ZSTD_DECOMPRESS = 11, 26 ICP_QAT_FW_COMP_20_CMD_DELIMITER 27 }; 28 29 #define ICP_QAT_FW_COMP_STATELESS_SESSION 0 30 #define ICP_QAT_FW_COMP_STATEFUL_SESSION 1 31 #define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0 32 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1 33 #define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0 34 #define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1 35 #define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0 36 #define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1 37 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1 38 #define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0 39 #define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2 40 #define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1 41 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3 42 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1 43 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4 44 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1 45 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5 46 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1 47 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7 48 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1 49 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MAX_VALUE 0xFFFFFFFF 50 51 #define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \ 52 ret_uncomp, secure_ram) \ 53 ((((sesstype) & ICP_QAT_FW_COMP_SESSION_TYPE_MASK) << \ 54 ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \ 55 (((autoselect) & ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) << \ 56 ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \ 57 (((enhanced_asb) & ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) << \ 58 ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \ 59 (((ret_uncomp) & ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) << \ 60 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \ 61 (((secure_ram) & ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) << \ 62 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS)) 63 64 #define ICP_QAT_FW_COMP_SESSION_TYPE_GET(flags) \ 65 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \ 66 ICP_QAT_FW_COMP_SESSION_TYPE_MASK) 67 68 #define ICP_QAT_FW_COMP_SESSION_TYPE_SET(flags, val) \ 69 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \ 70 ICP_QAT_FW_COMP_SESSION_TYPE_MASK) 71 72 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_GET(flags) \ 73 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS, \ 74 ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) 75 76 #define ICP_QAT_FW_COMP_EN_ASB_GET(flags) \ 77 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS, \ 78 ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) 79 80 #define ICP_QAT_FW_COMP_RET_UNCOMP_GET(flags) \ 81 QAT_FIELD_GET(flags, \ 82 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS, \ 83 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) 84 85 #define ICP_QAT_FW_COMP_SECURE_RAM_USE_GET(flags) \ 86 QAT_FIELD_GET(flags, \ 87 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS, \ 88 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) 89 90 struct icp_qat_fw_comp_req_hdr_cd_pars { 91 union { 92 struct { 93 __u64 content_desc_addr; 94 __u16 content_desc_resrvd1; 95 __u8 content_desc_params_sz; 96 __u8 content_desc_hdr_resrvd2; 97 __u32 content_desc_resrvd3; 98 } s; 99 struct { 100 __u32 comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2]; 101 __u32 content_desc_resrvd4; 102 } sl; 103 } u; 104 }; 105 106 struct icp_qat_fw_comp_req_params { 107 __u32 comp_len; 108 __u32 out_buffer_sz; 109 union { 110 struct { 111 __u32 initial_crc32; 112 __u32 initial_adler; 113 } legacy; 114 __u64 crc_data_addr; 115 } crc; 116 __u32 req_par_flags; 117 __u32 rsrvd; 118 }; 119 120 #define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr, \ 121 cnvdfx, crc, xxhash_acc, \ 122 cnv_error_type, append_crc, \ 123 drop_data, partial_decomp) \ 124 ((((sop) & ICP_QAT_FW_COMP_SOP_MASK) << \ 125 ICP_QAT_FW_COMP_SOP_BITPOS) | \ 126 (((eop) & ICP_QAT_FW_COMP_EOP_MASK) << \ 127 ICP_QAT_FW_COMP_EOP_BITPOS) | \ 128 (((bfinal) & ICP_QAT_FW_COMP_BFINAL_MASK) \ 129 << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \ 130 (((cnv) & ICP_QAT_FW_COMP_CNV_MASK) << \ 131 ICP_QAT_FW_COMP_CNV_BITPOS) | \ 132 (((cnvnr) & ICP_QAT_FW_COMP_CNVNR_MASK) \ 133 << ICP_QAT_FW_COMP_CNVNR_BITPOS) | \ 134 (((cnvdfx) & ICP_QAT_FW_COMP_CNV_DFX_MASK) \ 135 << ICP_QAT_FW_COMP_CNV_DFX_BITPOS) | \ 136 (((crc) & ICP_QAT_FW_COMP_CRC_MODE_MASK) \ 137 << ICP_QAT_FW_COMP_CRC_MODE_BITPOS) | \ 138 (((xxhash_acc) & ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) \ 139 << ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS) | \ 140 (((cnv_error_type) & ICP_QAT_FW_COMP_CNV_ERROR_MASK) \ 141 << ICP_QAT_FW_COMP_CNV_ERROR_BITPOS) | \ 142 (((append_crc) & ICP_QAT_FW_COMP_APPEND_CRC_MASK) \ 143 << ICP_QAT_FW_COMP_APPEND_CRC_BITPOS) | \ 144 (((drop_data) & ICP_QAT_FW_COMP_DROP_DATA_MASK) \ 145 << ICP_QAT_FW_COMP_DROP_DATA_BITPOS) | \ 146 (((partial_decomp) & ICP_QAT_FW_COMP_PARTIAL_DECOMP_MASK) \ 147 << ICP_QAT_FW_COMP_PARTIAL_DECOMP_BITPOS)) 148 149 #define ICP_QAT_FW_COMP_NOT_SOP 0 150 #define ICP_QAT_FW_COMP_SOP 1 151 #define ICP_QAT_FW_COMP_NOT_EOP 0 152 #define ICP_QAT_FW_COMP_EOP 1 153 #define ICP_QAT_FW_COMP_NOT_BFINAL 0 154 #define ICP_QAT_FW_COMP_BFINAL 1 155 #define ICP_QAT_FW_COMP_NO_CNV 0 156 #define ICP_QAT_FW_COMP_CNV 1 157 #define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0 158 #define ICP_QAT_FW_COMP_CNV_RECOVERY 1 159 #define ICP_QAT_FW_COMP_NO_CNV_DFX 0 160 #define ICP_QAT_FW_COMP_CNV_DFX 1 161 #define ICP_QAT_FW_COMP_CRC_MODE_LEGACY 0 162 #define ICP_QAT_FW_COMP_CRC_MODE_E2E 1 163 #define ICP_QAT_FW_COMP_NO_XXHASH_ACC 0 164 #define ICP_QAT_FW_COMP_XXHASH_ACC 1 165 #define ICP_QAT_FW_COMP_APPEND_CRC 1 166 #define ICP_QAT_FW_COMP_NO_APPEND_CRC 0 167 #define ICP_QAT_FW_COMP_DROP_DATA 1 168 #define ICP_QAT_FW_COMP_NO_DROP_DATA 0 169 #define ICP_QAT_FW_COMP_PARTIAL_DECOMPRESS 1 170 #define ICP_QAT_FW_COMP_NO_PARTIAL_DECOMPRESS 0 171 #define ICP_QAT_FW_COMP_SOP_BITPOS 0 172 #define ICP_QAT_FW_COMP_SOP_MASK 0x1 173 #define ICP_QAT_FW_COMP_EOP_BITPOS 1 174 #define ICP_QAT_FW_COMP_EOP_MASK 0x1 175 #define ICP_QAT_FW_COMP_BFINAL_BITPOS 6 176 #define ICP_QAT_FW_COMP_BFINAL_MASK 0x1 177 #define ICP_QAT_FW_COMP_CNV_BITPOS 16 178 #define ICP_QAT_FW_COMP_CNV_MASK 0x1 179 #define ICP_QAT_FW_COMP_CNVNR_BITPOS 17 180 #define ICP_QAT_FW_COMP_CNVNR_MASK 0x1 181 #define ICP_QAT_FW_COMP_CNV_DFX_BITPOS 18 182 #define ICP_QAT_FW_COMP_CNV_DFX_MASK 0x1 183 #define ICP_QAT_FW_COMP_CRC_MODE_BITPOS 19 184 #define ICP_QAT_FW_COMP_CRC_MODE_MASK 0x1 185 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS 20 186 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK 0x1 187 #define ICP_QAT_FW_COMP_CNV_ERROR_BITPOS 21 188 #define ICP_QAT_FW_COMP_CNV_ERROR_MASK 0b111 189 #define ICP_QAT_FW_COMP_CNV_ERROR_NONE 0b000 190 #define ICP_QAT_FW_COMP_CNV_ERROR_CHECKSUM 0b001 191 #define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_OBC_DIFF 0b010 192 #define ICP_QAT_FW_COMP_CNV_ERROR_DCPR 0b011 193 #define ICP_QAT_FW_COMP_CNV_ERROR_XLT 0b100 194 #define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_IBC_DIFF 0b101 195 #define ICP_QAT_FW_COMP_APPEND_CRC_BITPOS 24 196 #define ICP_QAT_FW_COMP_APPEND_CRC_MASK 0x1 197 #define ICP_QAT_FW_COMP_DROP_DATA_BITPOS 25 198 #define ICP_QAT_FW_COMP_DROP_DATA_MASK 0x1 199 #define ICP_QAT_FW_COMP_PARTIAL_DECOMP_BITPOS 27 200 #define ICP_QAT_FW_COMP_PARTIAL_DECOMP_MASK 0x1 201 202 #define ICP_QAT_FW_COMP_SOP_GET(flags) \ 203 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SOP_BITPOS, \ 204 ICP_QAT_FW_COMP_SOP_MASK) 205 206 #define ICP_QAT_FW_COMP_SOP_SET(flags, val) \ 207 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_SOP_BITPOS, \ 208 ICP_QAT_FW_COMP_SOP_MASK) 209 210 #define ICP_QAT_FW_COMP_EOP_GET(flags) \ 211 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_EOP_BITPOS, \ 212 ICP_QAT_FW_COMP_EOP_MASK) 213 214 #define ICP_QAT_FW_COMP_EOP_SET(flags, val) \ 215 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_EOP_BITPOS, \ 216 ICP_QAT_FW_COMP_EOP_MASK) 217 218 #define ICP_QAT_FW_COMP_BFINAL_GET(flags) \ 219 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_BFINAL_BITPOS, \ 220 ICP_QAT_FW_COMP_BFINAL_MASK) 221 222 #define ICP_QAT_FW_COMP_BFINAL_SET(flags, val) \ 223 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_BFINAL_BITPOS, \ 224 ICP_QAT_FW_COMP_BFINAL_MASK) 225 226 #define ICP_QAT_FW_COMP_CNV_GET(flags) \ 227 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_BITPOS, \ 228 ICP_QAT_FW_COMP_CNV_MASK) 229 230 #define ICP_QAT_FW_COMP_CNVNR_GET(flags) \ 231 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNVNR_BITPOS, \ 232 ICP_QAT_FW_COMP_CNVNR_MASK) 233 234 #define ICP_QAT_FW_COMP_CNV_DFX_GET(flags) \ 235 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_DFX_BITPOS, \ 236 ICP_QAT_FW_COMP_CNV_DFX_MASK) 237 238 #define ICP_QAT_FW_COMP_CNV_DFX_SET(flags, val) \ 239 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_CNV_DFX_BITPOS, \ 240 ICP_QAT_FW_COMP_CNV_DFX_MASK) 241 242 #define ICP_QAT_FW_COMP_CRC_MODE_GET(flags) \ 243 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CRC_MODE_BITPOS, \ 244 ICP_QAT_FW_COMP_CRC_MODE_MASK) 245 246 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_GET(flags) \ 247 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \ 248 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) 249 250 #define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_SET(flags, val) \ 251 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \ 252 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) 253 254 #define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_GET(flags) \ 255 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_ERROR_BITPOS, \ 256 ICP_QAT_FW_COMP_CNV_ERROR_MASK) 257 258 #define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_SET(flags, val) \ 259 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_CNV_ERROR_BITPOS, \ 260 ICP_QAT_FW_COMP_CNV_ERROR_MASK) 261 262 struct icp_qat_fw_xlt_req_params { 263 __u64 inter_buff_ptr; 264 }; 265 266 struct icp_qat_fw_comp_cd_hdr { 267 __u16 ram_bank_flags; 268 __u8 comp_cfg_offset; 269 __u8 next_curr_id; 270 __u32 resrvd; 271 __u64 comp_state_addr; 272 __u64 ram_banks_addr; 273 }; 274 275 #define COMP_CPR_INITIAL_CRC 0 276 #define COMP_CPR_INITIAL_ADLER 1 277 278 struct icp_qat_fw_xlt_cd_hdr { 279 __u16 resrvd1; 280 __u8 resrvd2; 281 __u8 next_curr_id; 282 __u32 resrvd3; 283 }; 284 285 struct icp_qat_fw_comp_req { 286 struct icp_qat_fw_comn_req_hdr comn_hdr; 287 struct icp_qat_fw_comp_req_hdr_cd_pars cd_pars; 288 struct icp_qat_fw_comn_req_mid comn_mid; 289 struct icp_qat_fw_comp_req_params comp_pars; 290 union { 291 struct icp_qat_fw_xlt_req_params xlt_pars; 292 __u32 resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2]; 293 struct { 294 __u32 partial_decompress_length; 295 __u32 partial_decompress_offset; 296 } partial_decompress; 297 } u1; 298 union { 299 __u32 resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2]; 300 struct { 301 __u32 asb_value; 302 __u32 reserved; 303 } asb_threshold; 304 } u3; 305 struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl; 306 union { 307 struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl; 308 __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2]; 309 } u2; 310 }; 311 312 struct icp_qat_fw_resp_comp_pars { 313 __u32 input_byte_counter; 314 __u32 output_byte_counter; 315 union { 316 struct { 317 __u32 curr_crc32; 318 __u32 curr_adler_32; 319 } legacy; 320 __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_2]; 321 } crc; 322 }; 323 324 struct icp_qat_fw_comp_state { 325 __u32 rd8_counter; 326 __u32 status_flags; 327 __u32 in_counter; 328 __u32 out_counter; 329 __u64 intermediate_state; 330 __u32 lobc; 331 __u32 replaybc; 332 __u64 pcrc64_poly; 333 __u32 crc32; 334 __u32 adler_xxhash32; 335 __u64 pcrc64_xorout; 336 __u32 out_buf_size; 337 __u32 in_buf_size; 338 __u64 in_pcrc64; 339 __u64 out_pcrc64; 340 __u32 lobs; 341 __u32 libc; 342 __u64 reserved; 343 __u32 xxhash_state[4]; 344 __u32 cleartext[4]; 345 }; 346 347 struct icp_qat_fw_comp_resp { 348 struct icp_qat_fw_comn_resp_hdr comn_resp; 349 __u64 opaque_data; 350 struct icp_qat_fw_resp_comp_pars comp_resp_pars; 351 }; 352 353 #define QAT_FW_COMP_BANK_FLAG_MASK 0x1 354 #define QAT_FW_COMP_BANK_I_BITPOS 8 355 #define QAT_FW_COMP_BANK_H_BITPOS 7 356 #define QAT_FW_COMP_BANK_G_BITPOS 6 357 #define QAT_FW_COMP_BANK_F_BITPOS 5 358 #define QAT_FW_COMP_BANK_E_BITPOS 4 359 #define QAT_FW_COMP_BANK_D_BITPOS 3 360 #define QAT_FW_COMP_BANK_C_BITPOS 2 361 #define QAT_FW_COMP_BANK_B_BITPOS 1 362 #define QAT_FW_COMP_BANK_A_BITPOS 0 363 364 enum icp_qat_fw_comp_bank_enabled { 365 ICP_QAT_FW_COMP_BANK_DISABLED = 0, 366 ICP_QAT_FW_COMP_BANK_ENABLED = 1, 367 ICP_QAT_FW_COMP_BANK_DELIMITER = 2 368 }; 369 370 #define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, bank_h_enable, \ 371 bank_g_enable, bank_f_enable, \ 372 bank_e_enable, bank_d_enable, \ 373 bank_c_enable, bank_b_enable, \ 374 bank_a_enable) \ 375 ((((bank_i_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 376 QAT_FW_COMP_BANK_I_BITPOS) | \ 377 (((bank_h_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 378 QAT_FW_COMP_BANK_H_BITPOS) | \ 379 (((bank_g_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 380 QAT_FW_COMP_BANK_G_BITPOS) | \ 381 (((bank_f_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 382 QAT_FW_COMP_BANK_F_BITPOS) | \ 383 (((bank_e_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 384 QAT_FW_COMP_BANK_E_BITPOS) | \ 385 (((bank_d_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 386 QAT_FW_COMP_BANK_D_BITPOS) | \ 387 (((bank_c_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 388 QAT_FW_COMP_BANK_C_BITPOS) | \ 389 (((bank_b_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 390 QAT_FW_COMP_BANK_B_BITPOS) | \ 391 (((bank_a_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \ 392 QAT_FW_COMP_BANK_A_BITPOS)) 393 394 struct icp_qat_fw_comp_crc_data_struct { 395 __u32 crc32; 396 union { 397 __u32 adler; 398 __u32 xxhash; 399 } adler_xxhash_u; 400 __u32 cpr_in_crc_lo; 401 __u32 cpr_in_crc_hi; 402 __u32 cpr_out_crc_lo; 403 __u32 cpr_out_crc_hi; 404 __u32 xlt_in_crc_lo; 405 __u32 xlt_in_crc_hi; 406 __u32 xlt_out_crc_lo; 407 __u32 xlt_out_crc_hi; 408 __u32 prog_crc_poly_lo; 409 __u32 prog_crc_poly_hi; 410 __u32 xor_out_lo; 411 __u32 xor_out_hi; 412 __u32 append_crc_lo; 413 __u32 append_crc_hi; 414 }; 415 416 struct xxhash_acc_state_buff { 417 __u32 in_counter; 418 __u32 out_counter; 419 __u32 xxhash_state[4]; 420 __u32 clear_txt[4]; 421 }; 422 423 #endif 424