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Searched refs:I915_MAX_PIPES (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_trace.h49 static_assert(I915_MAX_PIPES - 1 == _TRACE_PIPE_D);
75 __array(u32, frame, I915_MAX_PIPES)
76 __array(u32, scanline, I915_MAX_PIPES)
84 sizeof(__entry->frame[0]) * I915_MAX_PIPES);
86 sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
104 __array(u32, frame, I915_MAX_PIPES)
105 __array(u32, scanline, I915_MAX_PIPES)
114 sizeof(__entry->frame[0]) * I915_MAX_PIPES);
116 sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
234 __array(u32, frame, I915_MAX_PIPES)
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H A Dintel_frontbuffer.c240 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
242 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); in intel_frontbuffer_track()
H A Dintel_link_bw.h21 int max_bpp_x16[I915_MAX_PIPES];
H A Dintel_display_limits.h23 I915_MAX_PIPES = _PIPE_EDP enumerator
H A Dintel_dp_tunnel.c20 struct drm_dp_tunnel_ref ref[I915_MAX_PIPES];
471 drm_WARN_ON(display->drm, pipe_mask & ~((1 << I915_MAX_PIPES) - 1)); in intel_dp_tunnel_atomic_add_group_state()
H A Dintel_dbuf_bw.c20 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
H A Dintel_dvo.c422 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init_dev()
H A Dintel_display_irq.c533 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument
600 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument
624 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument
651 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument
H A Dintel_pmdemand.c41 int ddi_clocks[I915_MAX_PIPES];
H A Dskl_watermark.c42 struct skl_ddb_entry ddb[I915_MAX_PIPES];
43 unsigned int weight[I915_MAX_PIPES];
44 u8 slices[I915_MAX_PIPES];
742 u8 dbuf_mask[I915_MAX_PIPES];
3760 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_dbuf_is_misconfigured()
3781 I915_MAX_PIPES, crtc->pipe)) in skl_dbuf_is_misconfigured()
H A Dintel_bw.c47 unsigned int data_rate[I915_MAX_PIPES];
48 u8 num_active_planes[I915_MAX_PIPES];
H A Dintel_display_types.h1873 struct intel_dp_mst_encoder *stream_encoders[I915_MAX_PIPES];
H A Dintel_display.c7017 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_commit_modeset_enables()
7069 entries, I915_MAX_PIPES, pipe)) in skl_commit_modeset_enables()
7158 entries, I915_MAX_PIPES, pipe)); in skl_commit_modeset_enables()
7420 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()
H A Dintel_cdclk.c140 int min_cdclk[I915_MAX_PIPES];
142 u8 min_voltage_level[I915_MAX_PIPES];
H A Dintel_display_device.c1764 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); in __intel_display_device_info_runtime_init()
/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c92 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()