Searched refs:HCLK (Results 1 – 10 of 10) sorted by relevance
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
34 HCLK nodes: these represent the clock gates on individual35 lines from the HCLK clock tree and the gate for individual38 Requires properties for the HCLK nodes:
33 u32 HCLK; /* Hor Clock */ member
27 #define HCLK 8 macro
3 #define HCLK 1 macro
86 while (ios->clock < HCLK / div) in __toshsd_set_ios()640 mmc->f_min = HCLK / 512; in toshsd_probe()641 mmc->f_max = HCLK; in toshsd_probe()
11 #define HCLK 33000000 /* 33 MHz (PCI clock) */ macro
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */232 /* The PCLK domain uses HCLK right off */
509 par->HCLK = (1000000000 + (lineclock / 2)) / lineclock; in kyrofb_set_par()
517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre", in register_core_and_bus_clocks()