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Searched refs:GIC (Results 1 – 25 of 59) sorted by relevance

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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-platform-devices-ampere-smpro65 …| GIC (other) | 5 | 0 | ERR0 | 0 …
67 …| GIC (other) | 5 | 1 | ERR1 | 0 …
69 …| GIC (other) | 5 | 2 | ERR2 | 0 …
71 …| GIC (other) | 5 | 3 | ERR3 | 0 …
73 …| GIC (other) | 5 | 4 | ERR4 | 0 …
75 …| GIC (other) | 5 | 5 | ERR5 | 0 …
77 …| GIC (other) | 5 | 6 | ERR6 | 0 …
79 …| GIC (other) | 5 | 7 | ERR7 | 0 …
81 …| GIC (other) | 5 | 8 | ERR8 | 0 …
83 …| GIC (other) | 5 | 9 | ERR9 | 0 …
[all …]
/linux/drivers/net/ethernet/renesas/
H A Dravb_ptp.c188 ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0); in ravb_ptp_extts()
240 ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); in ravb_ptp_perout()
252 ravb_modify(ndev, GIC, GIC_PTME, 0); in ravb_ptp_perout()
294 gis &= ravb_read(ndev, GIC); in ravb_ptp_interrupt()
337 ravb_write(ndev, 0, GIC); in ravb_ptp_stop()
/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
/linux/Documentation/virt/kvm/devices/
H A Darm-vgic.rst27 Base address in the guest physical address space of the GIC distributor
32 Base address in the guest physical address space of the GIC virtual cpu
110 a GIC without the security extensions expose group 0 and group 1 active
132 this GIC instance, ranging from 64 to 1024, in increments of 32.
138 -EBUSY Value has already be set, or GIC has already been initialized
H A Dvcpu.rst51 -ENODEV PMUv3 not supported or GIC not initialized
58 virtual GIC implementation, this must be done after initializing the in-kernel
70 -ENODEV PMUv3 not supported or GIC not initialized
120 -ENODEV PMUv3 not supported or GIC not initialized
152 -ENODEV PMUv3 not supported or GIC not initialized
183 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
H A Darm-vgic-v3.rst176 and restore the entire GIC internal state (which is defined by the
289 this GIC instance, ranging from 64 to 1024, in increments of 32.
/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb.dts34 * This is the core tile with the CPU and GIC etc for the
64 * to the GIC on the core tile.
H A Darm-realview-eb-mp.dtsi119 * to the GIC on the core tile.
181 * GIC.
H A Darm-realview-pb1176.dts300 /* Primary DevChip GIC synthesized with the CPU */
529 /* This GIC on the board is cascaded off the DevChip GIC */
H A Darm-realview-pb11mp.dts85 /* Primary TestChip GIC synthesized with the CPU */
660 * This GIC on the Platform Baseboard is cascaded off the
661 * TestChip GIC
H A Darm-realview-pba8.dts50 /* Primary GIC PL390 interrupt controller in the test chip */
H A Darm-realview-pbx-a9.dts108 /* Primary GIC PL390 interrupt controller in the test chip */
/linux/Documentation/devicetree/bindings/arm/omap/
H A Dmpu.txt5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
/linux/arch/arm64/boot/dts/apm/
H A Dapm-shadowcat.dtsi118 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
120 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
121 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
122 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
123 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
H A Dapm-storm.dtsi109 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
110 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
111 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
112 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
113 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
/linux/arch/arm64/kvm/vgic/
H A Dvgic-init.c155 aa64pfr0 |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); in kvm_vgic_create()
156 pfr1 |= SYS_FIELD_PREP_ENUM(ID_PFR1_EL1, GIC, GICv3); in kvm_vgic_create()
H A Dvgic.h447 return kvm_has_feat(kvm, ID_AA64PFR0_EL1, GIC, IMP); in kvm_has_gicv3()
/linux/Documentation/devicetree/bindings/arm/
H A Dxen.txt20 A GIC node is also required.
/linux/arch/arm64/boot/dts/realtek/
H A Dkent.dtsi133 <0xff000000 0x0 0xff000000 0x200000>; /* GIC */
/linux/tools/testing/selftests/arm64/fp/
H A DREADME75 (Depending on the hardware GIC implementation, you may also need
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos9810.dtsi259 /* Hypervisor Virtual Timer interrupt is not wired to GIC */
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8dxl.dtsi93 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
H A Dimx8qxp.dtsi160 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
/linux/Documentation/arch/arm64/
H A Dcpu-hotplug.rst33 e.g. The GIC redistributor for each CPU must be accessed by the driver during
/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v2.dtsi119 reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */

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