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Searched refs:GENMASK_ULL (Results 1 – 25 of 418) sorted by relevance

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/linux/drivers/infiniband/hw/irdma/
H A Ddefs.h320 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
321 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
322 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
323 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
324 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
325 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
326 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
327 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
328 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
330 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
[all …]
H A Duda_d.h19 #define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
20 #define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
21 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42)
25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
26 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)
27 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
29 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
31 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
33 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
35 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
[all …]
/linux/drivers/iommu/riscv/
H A Diommu-bits.h26 #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)
27 #define RISCV_IOMMU_QUEUE_LOG2SZ_FIELD GENMASK_ULL(4, 0)
28 #define RISCV_IOMMU_QUEUE_INDEX_FIELD GENMASK_ULL(31, 0)
36 #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0)
37 #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60)
41 #define RISCV_IOMMU_CAPABILITIES_VERSION GENMASK_ULL(7, 0)
58 #define RISCV_IOMMU_CAPABILITIES_IGS GENMASK_ULL(29, 28)
61 #define RISCV_IOMMU_CAPABILITIES_PAS GENMASK_ULL(37, 32)
88 #define RISCV_IOMMU_DDTP_IOMMU_MODE GENMASK_ULL(3, 0)
195 #define RISCV_IOMMU_IOCOUNTOVF_HPM GENMASK_ULL(31, 1)
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx_fw_if.h194 #define EVTREG_ID GENMASK_ULL(8, 3)
201 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
206 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
207 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
212 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
217 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
222 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
227 #define RESP_FWD_BASE GENMASK_ULL(56, 9)
228 #define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28)
252 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
[all …]
H A Dnpc.h417 #define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40)
423 #define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41)
426 #define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1)
427 #define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3)
428 #define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5)
431 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
434 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)
436 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)
438 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7)
440 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10)
[all …]
H A Drvu_npc_hash.h104 GENMASK_ULL(63, 0),
105 GENMASK_ULL(63, 0),
108 GENMASK_ULL(63, 0),
109 GENMASK_ULL(63, 0),
115 GENMASK_ULL(63, 0),
116 GENMASK_ULL(63, 0),
119 GENMASK_ULL(63, 0),
120 GENMASK_ULL(63, 0),
127 [0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
128 [1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
[all …]
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.h145 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
175 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
195 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
214 #define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)
215 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
244 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
251 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
254 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
255 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
257 #define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)
[all …]
/linux/tools/perf/util/arm-spe-decoder/
H A Darm-spe-pkt-decoder.h45 #define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
49 #define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
55 #define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
60 #define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))
61 #define SPE_HDR_EXTENDED_INDEX(h0, h1) (((h0) & GENMASK_ULL(1, 0)) << 3 | \
73 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
74 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48)
77 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
79 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56)
87 #define SPE_CTX_PKT_HDR_INDEX(h) ((h) & GENMASK_ULL(1, 0))
[all …]
/linux/drivers/platform/mellanox/
H A Dmlxbf-tmfifo-regs.h18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
35 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
36 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
44 #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)
[all …]
/linux/drivers/mmc/host/
H A Dcavium.h121 #define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8)
122 #define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0)
130 #define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36)
133 #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)
136 #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)
137 #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)
138 #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38)
139 #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)
140 #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)
143 #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60)
[all …]
/linux/drivers/fpga/
H A Ddfl.h72 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
75 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
76 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
78 #define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */
79 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
100 #define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */
103 #define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */
104 #define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */
106 #define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */
109 #define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dwow.h8 #define RTW89_KEY_TKIP_PN_IV16 GENMASK_ULL(15, 0)
9 #define RTW89_KEY_TKIP_PN_IV32 GENMASK_ULL(47, 16)
11 #define RTW89_KEY_PN_0 GENMASK_ULL(7, 0)
12 #define RTW89_KEY_PN_1 GENMASK_ULL(15, 8)
13 #define RTW89_KEY_PN_2 GENMASK_ULL(23, 16)
14 #define RTW89_KEY_PN_3 GENMASK_ULL(31, 24)
15 #define RTW89_KEY_PN_4 GENMASK_ULL(39, 32)
16 #define RTW89_KEY_PN_5 GENMASK_ULL(47, 40)
18 #define RTW89_IGTK_IPN_0 GENMASK_ULL(7, 0)
19 #define RTW89_IGTK_IPN_1 GENMASK_ULL(15, 8)
[all …]
/linux/drivers/infiniband/hw/erdma/
H A Derdma_hw.h102 #define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56)
103 #define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32)
106 #define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28)
107 #define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0)
110 #define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0)
172 #define ERDMA_CMD_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)
173 #define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK GENMASK_ULL(47, 32)
174 #define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24)
175 #define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16)
176 #define ERDMA_CMD_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)
[all …]
/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_lan_txrx.h65 #define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11)
67 #define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0)
96 #define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50)
98 #define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30)
100 #define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4)
102 #define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0)
104 #define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48)
106 #define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34)
108 #define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16)
110 #define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4)
[all …]
/linux/arch/x86/include/asm/
H A Dsev-common.h60 #define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0)
65 #define GHCB_MSR_GPA_VALUE_MASK GENMASK_ULL(51, 0)
74 (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \
81 (((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
100 ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \
104 #define GHCB_MSR_PSC_REQ_TO_GFN(msr) (((msr) & GENMASK_ULL(51, 12)) >> 12)
105 #define GHCB_MSR_PSC_REQ_TO_OP(msr) (((msr) & GENMASK_ULL(55, 52)) >> 52)
110 (((u64)(val) & GENMASK_ULL(63, 32)) >> 32)
119 ((((u64)(v) & GENMASK_ULL(7, 0)) << 32) | \
126 (((u64)(v) & GENMASK_ULL(63, 32)) >> 32)
[all …]
/linux/include/linux/irqchip/
H A Darm-gic-v5.h21 #define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)
147 #define GICV5_IRS_IST_BASER_ADDR_MASK GENMASK_ULL(55, 6)
154 #define GICV5_ISTL1E_L2_ADDR_MASK GENMASK_ULL(55, 12)
198 #define GICV5_ITS_DT_BASER_ADDR_MASK GENMASK_ULL(55, 3)
204 #define GICV5_ITS_DIDR_DEVICEID GENMASK_ULL(31, 0)
216 #define GICV5_ITS_SYNCR_DEVICEID GENMASK_ULL(31, 0)
222 #define GICV5_DTL1E_L2_ADDR_MASK GENMASK_ULL(55, 3)
223 #define GICV5_DTL1E_SPAN GENMASK_ULL(63, 60)
226 #define GICV5_DTL2E_ITT_L2SZ GENMASK_ULL(2, 1)
228 #define GICV5_DTL2E_ITT_ADDR_MASK GENMASK_ULL(55, 3)
[all …]
H A Darm-gic-v3.h173 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
199 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
200 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
248 #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
249 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
251 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
252 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
253 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
300 #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)
302 #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53)
[all …]
/linux/tools/testing/selftests/kvm/include/arm64/
H A Dgic_v3.h173 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
199 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
200 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
248 #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
249 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
251 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
252 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
253 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
300 #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)
302 #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53)
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_parser.c275 #define ICE_IM_PGKB_F0_IDX GENMASK_ULL(6, 1)
277 #define ICE_IM_PGKB_F1_IDX GENMASK_ULL(13, 8)
279 #define ICE_IM_PGKB_F2_IDX GENMASK_ULL(20, 15)
281 #define ICE_IM_PGKB_F3_IDX GENMASK_ULL(27, 22)
282 #define ICE_IM_PGKB_AR_IDX GENMASK_ULL(34, 28)
302 #define ICE_IM_ALU_OPC GENMASK_ULL(5, 0)
303 #define ICE_IM_ALU_SS GENMASK_ULL(13, 6)
304 #define ICE_IM_ALU_SL GENMASK_ULL(18, 14)
306 #define ICE_IM_ALU_SXK GENMASK_ULL(23, 20)
307 #define ICE_IM_ALU_SRID GENMASK_ULL(30, 24)
[all …]
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_mchbar_regs.h22 #define PKG_TDP GENMASK_ULL(14, 0)
23 #define PKG_MIN_PWR GENMASK_ULL(30, 16)
24 #define PKG_MAX_PWR GENMASK_ULL(46, 32)
25 #define PKG_MAX_WIN GENMASK_ULL(54, 48)
26 #define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
27 #define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
/linux/drivers/net/ethernet/huawei/hinic3/
H A Dhinic3_mbox.h13 #define MBOX_MSG_HEADER_SRC_GLB_FUNC_IDX_MASK GENMASK_ULL(12, 0)
16 #define MBOX_MSG_HEADER_AEQ_ID_MASK GENMASK_ULL(17, 16)
17 #define MBOX_MSG_HEADER_MSG_ID_MASK GENMASK_ULL(21, 18)
18 #define MBOX_MSG_HEADER_CMD_MASK GENMASK_ULL(31, 22)
19 #define MBOX_MSG_HEADER_MSG_LEN_MASK GENMASK_ULL(42, 32)
20 #define MBOX_MSG_HEADER_MODULE_MASK GENMASK_ULL(47, 43)
21 #define MBOX_MSG_HEADER_SEG_LEN_MASK GENMASK_ULL(53, 48)
24 #define MBOX_MSG_HEADER_SEQID_MASK GENMASK_ULL(61, 56)
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_type.h206 #define IAVF_RXD_LEGACY_RSS_M GENMASK_ULL(63, 32)
208 #define IAVF_RXD_LEGACY_L2TAG1_M GENMASK_ULL(33, 16)
210 #define IAVF_RXD_FLEX_PTYPE_M GENMASK_ULL(25, 16)
212 #define IAVF_RXD_FLEX_PKT_LEN_M GENMASK_ULL(45, 32)
240 #define IAVF_RXD_LEGACY_FLTSTAT_M GENMASK_ULL(13, 12)
242 #define IAVF_RXD_LEGACY_PTYPE_M GENMASK_ULL(37, 30)
244 #define IAVF_RXD_LEGACY_LENGTH_M GENMASK_ULL(51, 38)
272 #define IAVF_RXD_FLEX_L2TAG1_M GENMASK_ULL(31, 16)
274 #define IAVF_RXD_FLEX_RSS_HASH_M GENMASK_ULL(63, 32)
280 #define IAVF_RXD_LEGACY_L2TAG2_M GENMASK_ULL(63, 32)
[all …]
/linux/drivers/iommu/amd/
H A Damd_iommu_types.h100 #define FEATURE_HATS GENMASK_ULL(11, 10)
101 #define FEATURE_GATS GENMASK_ULL(13, 12)
102 #define FEATURE_GLX GENMASK_ULL(15, 14)
104 #define FEATURE_PASMAX GENMASK_ULL(36, 32)
115 #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5)
120 #define FEATURE_NUM_INT_REMAP_SUP GENMASK_ULL(9, 8)
237 #define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40)
256 #define MMIO_CMD_HEAD_MASK GENMASK_ULL(18, 4) /* Command buffer head ptr field [18:4] */
258 #define MMIO_CMD_TAIL_MASK GENMASK_ULL(18, 4) /* Command buffer tail ptr field [18:4] */
315 #define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G)
[all …]
/linux/drivers/ras/amd/atl/
H A Ddenormalize.c490 cs_id = FIELD_GET(GENMASK_ULL(63, 13), denorm_ctx->current_spa) << 3; in get_logical_coh_st_fabric_id_for_current_spa()
498 cs_id = FIELD_GET(GENMASK_ULL(63, 14), denorm_ctx->current_spa) << 4; in get_logical_coh_st_fabric_id_for_current_spa()
506 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
513 cs_id = FIELD_GET(GENMASK_ULL(63, 13), denorm_ctx->current_spa) << 3; in get_logical_coh_st_fabric_id_for_current_spa()
521 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
530 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
538 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
539 cs_id |= FIELD_GET(GENMASK_ULL(9, 8), denorm_ctx->current_spa); in get_logical_coh_st_fabric_id_for_current_spa()
545 cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2; in get_logical_coh_st_fabric_id_for_current_spa()
618 temp_addr_b = GENMASK_ULL(low_bit - 1, intlv_bit) & ctx->ret_addr; in denorm_addr_df3_6chan()
[all …]
/linux/lib/tests/
H A Dtest_bits.c23 static_assert(assert_type(unsigned long long, GENMASK_ULL(63, 0)) == U64_MAX);
76 KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0)); in genmask_ull_test()
77 KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0)); in genmask_ull_test()
78 KUNIT_EXPECT_EQ(test, 0x000000ffffe00000ull, GENMASK_ULL(39, 21)); in genmask_ull_test()
79 KUNIT_EXPECT_EQ(test, 0xffffffffffffffffull, GENMASK_ULL(63, 0)); in genmask_ull_test()
83 GENMASK_ULL(0, 1); in genmask_ull_test()
84 GENMASK_ULL(0, 10); in genmask_ull_test()
85 GENMASK_ULL(9, 10); in genmask_ull_test()

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