1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * This header file defines the register offsets and bit fields 4 * of ENETC4 PF and VFs. Note that the same registers as ENETC 5 * version 1.0 are defined in the enetc_hw.h file. 6 * 7 * Copyright 2024 NXP 8 */ 9 #ifndef __ENETC4_HW_H_ 10 #define __ENETC4_HW_H_ 11 12 #define NXP_ENETC_VENDOR_ID 0x1131 13 #define NXP_ENETC_PF_DEV_ID 0xe101 14 #define NXP_ENETC_PPM_DEV_ID 0xe110 15 16 /**********************Station interface registers************************/ 17 /* Station interface LSO segmentation flag mask register 0/1 */ 18 #define ENETC4_SILSOSFMR0 0x1300 19 #define SILSOSFMR0_TCP_MID_SEG GENMASK(27, 16) 20 #define SILSOSFMR0_TCP_1ST_SEG GENMASK(11, 0) 21 #define SILSOSFMR0_VAL_SET(first, mid) (FIELD_PREP(SILSOSFMR0_TCP_MID_SEG, mid) | \ 22 FIELD_PREP(SILSOSFMR0_TCP_1ST_SEG, first)) 23 24 #define ENETC4_SILSOSFMR1 0x1304 25 #define SILSOSFMR1_TCP_LAST_SEG GENMASK(11, 0) 26 #define ENETC4_TCP_FLAGS_FIN BIT(0) 27 #define ENETC4_TCP_FLAGS_SYN BIT(1) 28 #define ENETC4_TCP_FLAGS_RST BIT(2) 29 #define ENETC4_TCP_FLAGS_PSH BIT(3) 30 #define ENETC4_TCP_FLAGS_ACK BIT(4) 31 #define ENETC4_TCP_FLAGS_URG BIT(5) 32 #define ENETC4_TCP_FLAGS_ECE BIT(6) 33 #define ENETC4_TCP_FLAGS_CWR BIT(7) 34 #define ENETC4_TCP_FLAGS_NS BIT(8) 35 /* According to tso_build_hdr(), clear all special flags for not last packet. */ 36 #define ENETC4_TCP_NL_SEG_FLAGS_DMASK (ENETC4_TCP_FLAGS_FIN | \ 37 ENETC4_TCP_FLAGS_RST | ENETC4_TCP_FLAGS_PSH) 38 39 /***************************ENETC port registers**************************/ 40 #define ENETC4_ECAPR0 0x0 41 #define ECAPR0_RFS BIT(2) 42 #define ECAPR0_TSD BIT(5) 43 #define ECAPR0_RSS BIT(8) 44 #define ECAPR0_RSC BIT(9) 45 #define ECAPR0_LSO BIT(10) 46 #define ECAPR0_WO BIT(13) 47 48 #define ENETC4_ECAPR1 0x4 49 #define ECAPR1_NUM_TCS GENMASK(6, 4) 50 #define ECAPR1_NUM_MCH GENMASK(9, 8) 51 #define ECAPR1_NUM_UCH GENMASK(11, 10) 52 #define ECAPR1_NUM_MSIX GENMASK(22, 12) 53 #define ECAPR1_NUM_VSI GENMASK(27, 24) 54 #define ECAPR1_NUM_IPV BIT(31) 55 56 #define ENETC4_ECAPR2 0x8 57 #define ECAPR2_NUM_TX_BDR GENMASK(9, 0) 58 #define ECAPR2_NUM_RX_BDR GENMASK(25, 16) 59 60 #define ENETC4_PMR 0x10 61 #define PMR_SI_EN(a) BIT((16 + (a))) 62 63 /* Port Pause ON/OFF threshold register */ 64 #define ENETC4_PPAUONTR 0x108 65 #define ENETC4_PPAUOFFTR 0x10c 66 67 /* Port Station interface promiscuous MAC mode register */ 68 #define ENETC4_PSIPMMR 0x200 69 #define PSIPMMR_SI_MAC_UP(a) BIT(a) /* a = SI index */ 70 #define PSIPMMR_SI_MAC_MP(a) BIT((a) + 16) 71 72 /* Port Station interface promiscuous VLAN mode register */ 73 #define ENETC4_PSIPVMR 0x204 74 75 /* Port RSS key register n. n = 0,1,2,...,9 */ 76 #define ENETC4_PRSSKR(n) ((n) * 0x4 + 0x250) 77 78 /* Port station interface MAC address filtering capability register */ 79 #define ENETC4_PSIMAFCAPR 0x280 80 #define PSIMAFCAPR_NUM_MAC_AFTE GENMASK(11, 0) 81 82 /* Port station interface VLAN filtering capability register */ 83 #define ENETC4_PSIVLANFCAPR 0x2c0 84 #define PSIVLANFCAPR_NUM_VLAN_FTE GENMASK(11, 0) 85 86 /* Port station interface VLAN filtering mode register */ 87 #define ENETC4_PSIVLANFMR 0x2c4 88 #define PSIVLANFMR_VS BIT(0) 89 90 /* Port Station interface a primary MAC address registers */ 91 #define ENETC4_PSIPMAR0(a) ((a) * 0x80 + 0x2000) 92 #define ENETC4_PSIPMAR1(a) ((a) * 0x80 + 0x2004) 93 94 /* Port station interface a configuration register 0/2 */ 95 #define ENETC4_PSICFGR0(a) ((a) * 0x80 + 0x2010) 96 #define PSICFGR0_VASE BIT(13) 97 #define PSICFGR0_ASE BIT(15) 98 #define PSICFGR0_ANTI_SPOOFING (PSICFGR0_VASE | PSICFGR0_ASE) 99 100 #define ENETC4_PSICFGR2(a) ((a) * 0x80 + 0x2018) 101 #define PSICFGR2_NUM_MSIX GENMASK(5, 0) 102 103 /* Port station interface a unicast MAC hash filter register 0/1 */ 104 #define ENETC4_PSIUMHFR0(a) ((a) * 0x80 + 0x2050) 105 #define ENETC4_PSIUMHFR1(a) ((a) * 0x80 + 0x2054) 106 107 /* Port station interface a multicast MAC hash filter register 0/1 */ 108 #define ENETC4_PSIMMHFR0(a) ((a) * 0x80 + 0x2058) 109 #define ENETC4_PSIMMHFR1(a) ((a) * 0x80 + 0x205c) 110 111 /* Port station interface a VLAN hash filter register 0/1 */ 112 #define ENETC4_PSIVHFR0(a) ((a) * 0x80 + 0x2060) 113 #define ENETC4_PSIVHFR1(a) ((a) * 0x80 + 0x2064) 114 115 #define ENETC4_PMCAPR 0x4004 116 #define PMCAPR_HD BIT(8) 117 #define PMCAPR_FP GENMASK(10, 9) 118 119 /* Port capability register */ 120 #define ENETC4_PCAPR 0x4000 121 #define PCAPR_LINK_TYPE BIT(4) 122 123 /* Port configuration register */ 124 #define ENETC4_PCR 0x4010 125 #define PCR_HDR_FMT BIT(0) 126 #define PCR_L2DOSE BIT(4) 127 #define PCR_TIMER_CS BIT(8) 128 #define PCR_PSPEED GENMASK(29, 16) 129 #define PCR_PSPEED_VAL(speed) (((speed) / 10 - 1) << 16) 130 131 /* Port MAC address register 0/1 */ 132 #define ENETC4_PMAR0 0x4020 133 #define ENETC4_PMAR1 0x4024 134 135 /* Port operational register */ 136 #define ENETC4_POR 0x4100 137 #define POR_TXDIS BIT(0) 138 #define POR_RXDIS BIT(1) 139 140 /* Port status register */ 141 #define ENETC4_PSR 0x4104 142 #define PSR_RX_BUSY BIT(1) 143 144 /* Port traffic class a transmit maximum SDU register */ 145 #define ENETC4_PTCTMSDUR(a) ((a) * 0x20 + 0x4208) 146 #define PTCTMSDUR_MAXSDU GENMASK(15, 0) 147 #define PTCTMSDUR_SDU_TYPE GENMASK(17, 16) 148 #define SDU_TYPE_PPDU 0 149 #define SDU_TYPE_MPDU 1 150 #define SDU_TYPE_MSDU 2 151 152 #define ENETC4_PMAC_OFFSET 0x400 153 #define ENETC4_PM_CMD_CFG(mac) (0x5008 + (mac) * 0x400) 154 #define PM_CMD_CFG_TX_EN BIT(0) 155 #define PM_CMD_CFG_RX_EN BIT(1) 156 #define PM_CMD_CFG_PAUSE_FWD BIT(7) 157 #define PM_CMD_CFG_PAUSE_IGN BIT(8) 158 #define PM_CMD_CFG_TX_ADDR_INS BIT(9) 159 #define PM_CMD_CFG_LOOP_EN BIT(10) 160 #define PM_CMD_CFG_LPBK_MODE GENMASK(12, 11) 161 #define LPBCK_MODE_EXT_TX_CLK 0 162 #define LPBCK_MODE_MAC_LEVEL 1 163 #define LPBCK_MODE_INT_TX_CLK 2 164 #define PM_CMD_CFG_CNT_FRM_EN BIT(13) 165 #define PM_CMD_CFG_TXP BIT(15) 166 #define PM_CMD_CFG_SEND_IDLE BIT(16) 167 #define PM_CMD_CFG_HD_FCEN BIT(18) 168 #define PM_CMD_CFG_SFD BIT(21) 169 #define PM_CMD_CFG_TX_FLUSH BIT(22) 170 #define PM_CMD_CFG_TX_LOWP_EN BIT(23) 171 #define PM_CMD_CFG_RX_LOWP_EMPTY BIT(24) 172 #define PM_CMD_CFG_SWR BIT(26) 173 #define PM_CMD_CFG_TS_MODE BIT(30) 174 #define PM_CMD_CFG_MG BIT(31) 175 176 /* Port MAC 0/1 Maximum Frame Length Register */ 177 #define ENETC4_PM_MAXFRM(mac) (0x5014 + (mac) * 0x400) 178 179 /* Port internal MDIO base address, use to access PCS */ 180 #define ENETC4_PM_IMDIO_BASE 0x5030 181 182 /* Port MAC 0/1 Interrupt Event Register */ 183 #define ENETC4_PM_IEVENT(mac) (0x5040 + (mac) * 0x400) 184 #define PM_IEVENT_TX_EMPTY BIT(5) 185 #define PM_IEVENT_RX_EMPTY BIT(6) 186 187 /* Port MAC 0/1 Pause Quanta Register */ 188 #define ENETC4_PM_PAUSE_QUANTA(mac) (0x5054 + (mac) * 0x400) 189 190 /* Port MAC 0/1 Pause Quanta Threshold Register */ 191 #define ENETC4_PM_PAUSE_THRESH(mac) (0x5064 + (mac) * 0x400) 192 193 #define ENETC4_PM_SINGLE_STEP(mac) (0x50c0 + (mac) * 0x400) 194 #define PM_SINGLE_STEP_CH BIT(6) 195 #define PM_SINGLE_STEP_OFFSET GENMASK(15, 7) 196 #define PM_SINGLE_STEP_OFFSET_SET(o) FIELD_PREP(PM_SINGLE_STEP_OFFSET, o) 197 #define PM_SINGLE_STEP_EN BIT(31) 198 199 /* Port MAC 0 Interface Mode Control Register */ 200 #define ENETC4_PM_IF_MODE(mac) (0x5300 + (mac) * 0x400) 201 #define PM_IF_MODE_IFMODE GENMASK(2, 0) 202 #define IFMODE_XGMII 0 203 #define IFMODE_RMII 3 204 #define IFMODE_RGMII 4 205 #define IFMODE_SGMII 5 206 #define PM_IF_MODE_REVMII BIT(3) 207 #define PM_IF_MODE_M10 BIT(4) 208 #define PM_IF_MODE_HD BIT(6) 209 #define PM_IF_MODE_SSP GENMASK(14, 13) 210 #define SSP_100M 0 211 #define SSP_10M 1 212 #define SSP_1G 2 213 #define PM_IF_MODE_ENA BIT(15) 214 215 /* Port external MDIO Base address, use to access off-chip PHY */ 216 #define ENETC4_EMDIO_BASE 0x5c00 217 218 /**********************ENETC Pseudo MAC port registers************************/ 219 /* Port pseudo MAC receive octets counter (64-bit) */ 220 #define ENETC4_PPMROCR 0x5080 221 222 /* Port pseudo MAC receive unicast frame counter register (64-bit) */ 223 #define ENETC4_PPMRUFCR 0x5088 224 225 /* Port pseudo MAC receive multicast frame counter register (64-bit) */ 226 #define ENETC4_PPMRMFCR 0x5090 227 228 /* Port pseudo MAC receive broadcast frame counter register (64-bit) */ 229 #define ENETC4_PPMRBFCR 0x5098 230 231 /* Port pseudo MAC transmit octets counter (64-bit) */ 232 #define ENETC4_PPMTOCR 0x50c0 233 234 /* Port pseudo MAC transmit unicast frame counter register (64-bit) */ 235 #define ENETC4_PPMTUFCR 0x50c8 236 237 /* Port pseudo MAC transmit multicast frame counter register (64-bit) */ 238 #define ENETC4_PPMTMFCR 0x50d0 239 240 /* Port pseudo MAC transmit broadcast frame counter register (64-bit) */ 241 #define ENETC4_PPMTBFCR 0x50d8 242 243 #endif 244