Searched refs:ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (Results 1 – 12 of 12) sorted by relevance
645 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
107 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1270 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable() 1349 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
374 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
492 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1153 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
590 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1143 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_pcie_gart_enable() 1235 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_agp_enable()
2414 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_pcie_gart_enable() 2497 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_agp_enable()
4287 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable() 4373 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
850 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()