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Searched refs:DSPCNTR (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Di9xx_plane_regs.h15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) macro
H A Dintel_display.c8411 intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE); in i830_disable_pipe()
8413 intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE); in i830_disable_pipe()
8415 intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE); in i830_disable_pipe()
H A Dintel_color.c1082 tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_get_config()
/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c206 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
520 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
H A Dcmd_parser.c1324 info->ctrl_reg = DSPCNTR(display, info->pipe); in gen8_decode_mi_display_flip()
1391 info->ctrl_reg = DSPCNTR(display, info->pipe); in skl_decode_mi_display_flip()
H A Dhandlers.c1043 if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()